JPH07221414A - Semiconductor circuit board - Google Patents

Semiconductor circuit board

Info

Publication number
JPH07221414A
JPH07221414A JP1452594A JP1452594A JPH07221414A JP H07221414 A JPH07221414 A JP H07221414A JP 1452594 A JP1452594 A JP 1452594A JP 1452594 A JP1452594 A JP 1452594A JP H07221414 A JPH07221414 A JP H07221414A
Authority
JP
Japan
Prior art keywords
semiconductor circuit
cutting
substrate
circuit board
circuit pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1452594A
Other languages
Japanese (ja)
Inventor
Fumihiko Ogasawara
文彦 小笠原
Hiroyuki Miyake
弘之 三宅
Kazuhiro Sakasai
一宏 逆井
Akira Yamazawa
亮 山沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP1452594A priority Critical patent/JPH07221414A/en
Publication of JPH07221414A publication Critical patent/JPH07221414A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Structure Of Printed Boards (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To simply check defective parts at cutting and splitting step by forming check marks for the precision criterion of cutting and splitting only near the cross points of each scribe line. CONSTITUTION:Semiconductor patterns are formed in each semiconductor circuit pattern forming region on the surface of a glass substrate, 1 and 4 check marks 6 are formed near the cross points 5 of scribe lines 4 and one for each of 4 corners of each circuit substrate and 80mum inside the scribe line 4 with aluminum of wiring material. A L shaped check marks 6 500mum long, 20mum wide is formed, and the substrate is cut along the scribe lines with a general method and split into individual semiconductor circuit substrate. As the check marks 6 are formed at each of 4 corners of the circuit substrate, the checking is easier and more efficient and a substrate is utilized more efficiently compared with the conventional product.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、複数の半導体回路パ
ターンを形成してなる絶縁性基板から切断分割して使用
する半導体回路基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit board which is cut and divided from an insulating board having a plurality of semiconductor circuit patterns and used.

【0002】[0002]

【従来の技術】この種の半導体回路基板の切断分割に当
たっては、半導体回路パターンを形成してなる絶縁性基
板上に切断装置の切断位置認識用のアライメントマーク
を形成し、かかるマークに基づいて切断を行うという手
法が採られている。ところが、このアライメントマーク
は実際の切断箇所とは離れた位置に形成されることが多
いため、切断分割された各半導体回路基板における切断
分割の良否を判断するには必ずしも適しておらず、その
判断基準として利用することは困難であった。従って、
この手法において切断分割の良否を判断する場合には、
別途その判断を行う専用のマークを形成して切断分割不
良の検査を行う必要があり、煩わしさを伴うものであっ
た。
2. Description of the Related Art In cutting and dividing a semiconductor circuit board of this type, an alignment mark for recognizing a cutting position of a cutting device is formed on an insulating substrate having a semiconductor circuit pattern, and cutting is performed based on the mark. The method of doing is adopted. However, since this alignment mark is often formed at a position apart from the actual cutting position, it is not necessarily suitable for judging the quality of the cutting division in each of the divided semiconductor circuit boards. It was difficult to use as a standard. Therefore,
When judging the quality of cutting division with this method,
It is necessary to separately form a dedicated mark for making the determination and inspect for a defective cut division, which is troublesome.

【0003】一方、このような半導体回路基板の切断分
割工程等で発生する切断分割不良品の検査を容易に行う
方法としては、従来、各半導体回路パターン形成領域の
外周縁を取り囲むようなライン状の検査マークを形成す
る技術が提案されている(例えば特開昭56−1522
48号、特開平4−330758号公報参照)。
On the other hand, as a method for easily inspecting a defective cut / divided product generated in such a cut / division process of a semiconductor circuit board, conventionally, a line shape surrounding the outer peripheral edge of each semiconductor circuit pattern forming region is used. Japanese Patent Laid-Open No. 56-1522 has been proposed.
48, JP-A-4-330758).

【0004】この技術は、図3に示すように、絶縁性基
板a上に形成した複数の半導体回路基板パターン形成領
域bの周縁の外側であって且つ各回路パターンごとに切
断するためのスクライブ(切断)線cの内側となる領域
に、回路パターン形成領域を取り囲むように連続する検
査マークdを形成したものである。図中、eは半導体回
路を外部と接続するためのボンディングワイヤ等を付設
するボンディングパットを示す。また、上記検査マーク
dは半導体回路パターの配線材料等にて形成される。こ
のような検査マークdを形成した半導体回路基板は、切
断等の分割手段によりスクライブ線cにしたがって基板
aを切断分割した際に発生するひび割れや欠けが検査マ
ークdのライン内に到達しているか否かを調べることに
より、その不良品が検査されるようになっている。
In this technique, as shown in FIG. 3, a scribe for cutting each circuit pattern outside the periphery of a plurality of semiconductor circuit board pattern forming regions b formed on an insulating substrate a is provided. In the region inside the (cutting) line c, continuous inspection marks d are formed so as to surround the circuit pattern formation region. In the figure, e indicates a bonding pad for attaching a bonding wire or the like for connecting the semiconductor circuit to the outside. The inspection mark d is formed of a wiring material of a semiconductor circuit pattern or the like. In the semiconductor circuit substrate on which such inspection marks d are formed, are cracks or chips generated when the substrate a is cut and divided according to the scribe line c by dividing means such as cutting have reached the line of the inspection marks d. By checking whether or not the defective product is inspected.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記の
ような半導体回路基板においては、半導体回路基板パタ
ーン形成領域bの周縁の外側に、認識可能な一定の幅の
検査マークdをそのパターン形成領域bを取り囲むよう
に形成しているため、検査マークdを形成するためのス
ペースPを常に確保しなけばならず、そのマークの専有
面積分だけ基板の使用効率が低下するという問題があっ
た。しかも、ワイヤボンディングの際等において、図4
に示すようにボンディングパットe側のボンディングワ
イヤfの一部が下方にたわんで検査マークdと接触して
ショートによる不良が発生するという問題もあった。
However, in the semiconductor circuit board as described above, the inspection mark d having a recognizable constant width is provided outside the peripheral edge of the semiconductor circuit board pattern forming area b. However, since the space P for forming the inspection mark d must be secured at all times, there is a problem that the use efficiency of the substrate is reduced by the area occupied by the mark. Moreover, in wire bonding, etc., as shown in FIG.
There is also a problem that a part of the bonding wire f on the side of the bonding pad e bends downward as shown in FIG.

【0006】本発明は、上述したような従来技術の問題
点を解消することが可能で、切断分割工程における不良
品の検査を簡便に行うことができる半導体回路基板を提
供することを目的とする。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor circuit board which can solve the above-mentioned problems of the prior art and can easily inspect defective products in the cutting and dividing step. .

【0007】[0007]

【課題を解決するための手段】本発明の半導体回路基板
は、絶縁性基板上に複数の半導体回路パターンを形成し
た後に各半導体回路パターン形成領域の周縁に形成され
るスクライブ線に沿って個々に切断分割して使用する半
導体回路基板において、上記絶縁性基板上の半導体回路
パターン形成領域内の配線及びボンディングパッドが形
成されていない部位で且つ該回路パターン形成領域の最
外周縁に沿って形成する各スクライブ線の交差部分の近
傍となる部位のみに、切断分割精度の判定基準となる検
査マークを形成したことを特徴とするものである。
A semiconductor circuit board according to the present invention is formed by individually forming a plurality of semiconductor circuit patterns on an insulating substrate and then along scribe lines formed on the periphery of each semiconductor circuit pattern forming region. In the semiconductor circuit board to be used by cutting and dividing, it is formed on the insulating substrate in a region where wiring and bonding pad are not formed in the semiconductor circuit pattern forming area and along the outermost peripheral edge of the circuit pattern forming area. It is characterized in that an inspection mark serving as a criterion for determining the cutting division accuracy is formed only in a portion near the intersection of each scribe line.

【0008】ここで、本発明における検査マーク6の形
成箇所は、図1に示すように、絶縁性基板1上の半導体
回路パターン形成領域2内の配線及びボンディングパッ
ド3が形成されていない部位であると同時に、スクライ
ブ線4の交差部分5の近傍となる部位に相当する箇所
(領域)であればよい。より具体的には、矩形形状の回
路基板における4隅(コーナー部)であり、また、好ま
しくは、図2に示すようにスクライブ線4から内側への
距離yが100μm以内となる領域である。特に、スク
ライブ線4からの上記距離yは、スクライブ精度や切断
時のひび割れ、欠けの許容量に基づいて選定される。
Here, as shown in FIG. 1, the inspection mark 6 in the present invention is formed on the insulating substrate 1 in the semiconductor circuit pattern forming region 2 where the wiring and the bonding pad 3 are not formed. At the same time, it may be a location (area) corresponding to a location near the intersection 5 of the scribe line 4. More specifically, it is the four corners (corner portions) of the rectangular circuit board, and is preferably an area where the distance y from the scribe line 4 to the inside is 100 μm or less, as shown in FIG. In particular, the distance y from the scribe line 4 is selected based on the scribe accuracy and the allowable amount of cracks and chips at the time of cutting.

【0009】なお、上記スクライブ線4は、半導体回路
パターン形成領域2の最外周縁に沿って近接させて形成
されるものである。このようにスクライブ線を回路パタ
ーン形成領域の最外周縁に沿って形成できるのは、従来
のスクライブ線と回路パターン形成領域との間に確保し
ていた検査マーク形成用のスペースが不要となるからで
ある。
The scribe lines 4 are formed close to each other along the outermost peripheral edge of the semiconductor circuit pattern forming region 2. In this way, the scribe line can be formed along the outermost peripheral edge of the circuit pattern forming region because the space for forming the inspection mark, which has been secured between the conventional scribe line and the circuit pattern forming region, is unnecessary. Is.

【0010】検査マーク6は、その形状、サイズ等につ
いて適宜選定されるものであって特に限定されるもので
はないが、交差する2本のスクライブ線4にそれぞれ平
行する形状のものが好ましい。このましい態様として
は、例えば、各片が交差する2本のスクライブ線4とそ
れぞれ平行するL字状の形状であり、その各片の長さs
が500μm以上で(約2000μm以下)且つその幅
wが50μm以下(約10μm以上)のサイズからなる
ものである。
The inspection mark 6 is appropriately selected with respect to its shape, size, etc. and is not particularly limited, but it is preferable that the inspection mark 6 has a shape parallel to each of the two intersecting scribe lines 4. In this preferable mode, for example, each piece has an L-shape that is parallel to two intersecting scribe lines 4, and the length s of each piece is s.
Is 500 μm or more (about 2000 μm or less) and its width w is 50 μm or less (about 10 μm or more).

【0011】また、この検査マーク6の形成材料や形成
方法についても適宜選定されて特に制約されるものでは
ないが、例えば、半導体回路を構成する配線層等の金属
材料を用いる場合には、その回路パターンとの同時形成
が可能となり、マーク形成の煩雑さが殆どなくなるとい
う利点がある。なお、検査マーク6は、通常、絶縁性基
板上に直接形成されるが、検査時において識別可能であ
れば特にこれに限定されず、その他にも例えば絶縁性基
板上に絶縁膜を積層形成した後のその絶縁膜上に形成す
ることも可能である。また、検査マークは、絶縁性基板
上に形成する絶縁膜により形成してもよい。すなわち、
絶縁膜のうち本来の検査マーク形成位置に当たる部位に
は絶縁膜材料を着膜せず、絶縁性基板の表面がマーク形
状となって露出するよう絶縁層をパターン形成する。こ
の場合、絶縁膜は、絶縁膜部分と絶縁膜で形成されるマ
ーク部分(絶縁性基板の表面)とが判別できるような材
質等にて形成する必要がある。
Further, the material and method of forming the inspection mark 6 are appropriately selected and are not particularly limited. For example, when a metal material such as a wiring layer forming a semiconductor circuit is used, This has the advantage that it can be formed simultaneously with the circuit pattern, and the complexity of mark formation is almost eliminated. The inspection mark 6 is usually formed directly on the insulating substrate, but it is not particularly limited to this as long as it can be identified at the time of inspection. In addition, for example, an insulating film is laminated and formed on the insulating substrate. It can be formed later on the insulating film. Further, the inspection mark may be formed by an insulating film formed on the insulating substrate. That is,
The insulating film material is not deposited on the portion of the insulating film corresponding to the original inspection mark forming position, and the insulating layer is patterned so that the surface of the insulating substrate is exposed in the mark shape. In this case, the insulating film needs to be formed of a material or the like that can distinguish the insulating film portion and the mark portion (the surface of the insulating substrate) formed by the insulating film.

【0012】さらに、半導体回路基板における絶縁性基
板としては、この種の回路基板に使用され得るものであ
れば如何なるものであってもよい。この絶縁性基板がガ
ラス基板である場合、その切断分割(割断)の際にはス
クライブ線が交差する回路基板の角部においてひび割れ
や欠けが発生しやすいため、上記のような検査マーク6
によれば、このようなガラス製絶縁性基板における切断
分割精度の検査をより効率よく無駄なく行うことができ
る。
Further, the insulating substrate in the semiconductor circuit substrate may be any one that can be used in this type of circuit substrate. When the insulating substrate is a glass substrate, cracks and chips are likely to occur at the corners of the circuit board where the scribe lines intersect during the cutting division (cutting), so that the inspection mark 6 as described above is used.
According to this, it is possible to more efficiently and efficiently inspect the cutting division accuracy of such a glass insulating substrate.

【0013】[0013]

【作用】本発明の半導体回路基板によれば、その切断分
割をスクライブ線に沿って行った後に、上記特定の領域
のみに形成した検査マークを目視或いはTVカメラ等に
よる自動検査機器により観察して、その検査マークにひ
び割れや欠け等が入り込んでいるか否かを調べることに
より、切断分割の精度を検査することができる。この検
査により不良品は排除される。
According to the semiconductor circuit board of the present invention, after the cutting and dividing is performed along the scribe line, the inspection mark formed only in the specific region is visually or visually observed by an automatic inspection device such as a TV camera. The accuracy of cutting division can be inspected by checking whether the inspection mark has cracks or chips. This inspection eliminates defective products.

【0014】[0014]

【実施例】以下、実施例を挙げて本発明をさらに詳細に
説明する。
EXAMPLES The present invention will be described in more detail with reference to examples.

【0015】図1に示すように、厚さ1.1mmのガラ
ス基板1の表面における各半導体回路パターン形成領域
内に、薄膜形成手段等の常法により複数の半導体回路パ
ターンをそれぞれ形成する。また、このパターン形成と
同時に、半導体回路の配線材料であるアルミニウムを用
いて4つの検査マーク6を形成した。
As shown in FIG. 1, a plurality of semiconductor circuit patterns are formed in each semiconductor circuit pattern forming region on the surface of a glass substrate 1 having a thickness of 1.1 mm by a conventional method such as thin film forming means. Simultaneously with this pattern formation, four inspection marks 6 were formed using aluminum, which is a wiring material of the semiconductor circuit.

【0016】そして、各半導体回路パターン形成領域の
外周縁に対して常法によりスクライブ線4を形成する。
Then, the scribe line 4 is formed on the outer peripheral edge of each semiconductor circuit pattern forming region by a conventional method.

【0017】この実施例では、検査マーク6を、スクラ
イブ線4の交差部分5の近傍であってそのスクライブ線
4から80μm内側の位置で各回路基板の4隅に1つず
つ形成した。また、検査マーク6としては、各片の長さ
sが500μmで、その幅wが20μmの全体がL字形
状のものを形成した。従って、この検査マーク6は、ス
クライブ線4から内側への距離y(=x+w)が100
μmとなる幅をもつ領域内に形成したものになる。
In this embodiment, the inspection marks 6 are formed in the four corners of each circuit board at a position near the intersection 5 of the scribe lines 4 and 80 μm inside the scribe lines 4. As the inspection mark 6, a piece having a length s of 500 μm and a width w of 20 μm was formed into an L shape as a whole. Therefore, in this inspection mark 6, the distance y (= x + w) from the scribe line 4 to the inside is 100.
It is formed in a region having a width of μm.

【0018】次いで、この複数の半導体回路パターン及
び検査マーク等を形成した基板を、常套手段によりスク
ライブ線に沿って割断し、個々の半導体回路基板に分割
した。
Next, the substrate on which the plurality of semiconductor circuit patterns, the inspection marks and the like were formed was cut along a scribe line by a conventional means, and divided into individual semiconductor circuit substrates.

【0019】得られた各半導体回路基板について、それ
ぞれ検査マーク6を観察し、切断分割時のひび割れや欠
けの有無について検査した。この実施例では、絶縁性基
板1としてガラス基板を使用しているため、ひび割れや
欠けは回路基板の角部に多く発生していることが多い
が、検査マーク6を回路基板の4隅に形成していること
により上記の検査を容易に且つ効率よく行うことができ
た。また、検査マーク6を上記のような回路パターン形
成領域内に形成しているため、その形成領域の外側にマ
ークを形成していた従来品に比べて基板の有効利用が図
れる。
Each of the obtained semiconductor circuit boards was inspected for inspection marks 6 and inspected for cracks or chips during cutting and division. In this embodiment, since the glass substrate is used as the insulating substrate 1, cracks and chips are often generated at the corners of the circuit board, but the inspection marks 6 are formed at the four corners of the circuit board. By doing so, the above-mentioned inspection could be performed easily and efficiently. Further, since the inspection mark 6 is formed in the circuit pattern forming region as described above, the substrate can be effectively used as compared with the conventional product in which the mark is formed outside the forming region.

【0020】[0020]

【発明の効果】以上説明したように、本発明の半導体回
路基板は、切断分割精度の判定基準となる検査マーク
を、絶縁性基板上の半導体回路パターン形成領域内の配
線及びボンディングパッドが形成されていない部位で且
つ各スクライブ線の交差部分の近傍となる部位のみに形
成するものであるため、従来品のように半導体回路パタ
ーン形成領域の外側であってスクライブ線の内側である
部分に検査マーク形成用のスペースを余分に確保する必
要がなく、その分絶縁性基板の有効利用を図ることがで
きる。また、検査マークがボンディングパッドと回路基
板端縁部との間に存在しないため、ボンディングワイヤ
の一部が下方にたわんで検査マークと接触してショート
する等の従来品における問題を防止することができる。
As described above, in the semiconductor circuit board of the present invention, the inspection mark serving as the judgment standard of the cutting and dividing accuracy, the wiring and the bonding pad in the semiconductor circuit pattern forming region on the insulating substrate are formed. Since it is formed only on the unexposed portion and in the vicinity of the intersection of each scribe line, the inspection mark is placed on the portion outside the semiconductor circuit pattern forming area and on the inside of the scribe line as in the conventional product. It is not necessary to secure an extra space for formation, and the insulating substrate can be effectively used accordingly. Further, since the inspection mark does not exist between the bonding pad and the edge portion of the circuit board, it is possible to prevent a problem in the conventional product such that a part of the bonding wire bends downward and comes into contact with the inspection mark to cause a short circuit. it can.

【0021】このように本発明によれば、上記のごとき
特定の領域のみに検査マークを形成するだけで、かかる
検査マークを判定基準として切断分割工程における不良
品の検査を簡便に行うことができる。
As described above, according to the present invention, by only forming the inspection mark only in the specific area as described above, it is possible to easily inspect the defective product in the cutting and dividing step using the inspection mark as a criterion. .

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例に係る半導体回路基板を示
す概念平面図である。
FIG. 1 is a conceptual plan view showing a semiconductor circuit board according to an embodiment of the present invention.

【図2】 半導体回路基板における検査マークを説明す
るための図であって、aはその平面図、bはそのb−b
線断面図である。
2A and 2B are views for explaining an inspection mark on a semiconductor circuit board, in which a is a plan view thereof and b is its bb.
It is a line sectional view.

【図3】 従来の検査マークを形成した半導体回路基板
を示す概念平面図である。
FIG. 3 is a conceptual plan view showing a conventional semiconductor circuit board on which inspection marks are formed.

【図4】 図3のIV−IV線断面図であって、従来の
検査マークとボンディングワイヤによる不良品発生の状
態を説明するための図である。
FIG. 4 is a cross-sectional view taken along the line IV-IV of FIG. 3 and is a view for explaining a state where a defective product is generated by a conventional inspection mark and a bonding wire.

【符号の説明】[Explanation of symbols]

1…絶縁性基板、2…半導体回路パターン形成領域、3
…配線及びボンディングパッド、4…スクライブ線、5
…交差部分、6…検査マーク。
1 ... Insulating substrate, 2 ... Semiconductor circuit pattern formation region, 3
… Wiring and bonding pads, 4… Scribing lines, 5
… Intersection, 6… inspection mark.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/301 H05K 3/00 X P (72)発明者 山沢 亮 神奈川県海老名市本郷2274番地、富士ゼロ ックス株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication location H01L 21/301 H05K 3/00 XP (72) Inventor Ryo Yamazawa 2274 Hongo, Ebina City, Kanagawa Prefecture, Fuji Xerox Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板上に複数の半導体回路パター
ンを形成した後に各半導体回路パターン形成領域の周縁
に形成されるスクライブ線に沿って個々に切断分割して
使用する半導体回路基板において、 上記絶縁性基板上の半導体回路パターン形成領域内の配
線及びボンディングパッドが形成されていない部位で且
つ該回路パターン形成領域の最外周縁に沿って形成する
各スクライブ線の交差部分の近傍となる部位のみに、切
断分割精度の判定基準となる検査マークを形成したこと
を特徴とする半導体回路基板。
1. A semiconductor circuit board which is formed by forming a plurality of semiconductor circuit patterns on an insulating substrate and then individually cutting and dividing the semiconductor circuit pattern along a scribe line formed at the periphery of each semiconductor circuit pattern forming region. Only the portion in the semiconductor circuit pattern forming region on the insulating substrate where the wiring and bonding pad are not formed and near the intersection of the scribe lines formed along the outermost peripheral edge of the circuit pattern forming region A semiconductor circuit board, wherein an inspection mark serving as a judgment standard for cutting and dividing accuracy is formed on.
JP1452594A 1994-02-08 1994-02-08 Semiconductor circuit board Pending JPH07221414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1452594A JPH07221414A (en) 1994-02-08 1994-02-08 Semiconductor circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1452594A JPH07221414A (en) 1994-02-08 1994-02-08 Semiconductor circuit board

Publications (1)

Publication Number Publication Date
JPH07221414A true JPH07221414A (en) 1995-08-18

Family

ID=11863543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1452594A Pending JPH07221414A (en) 1994-02-08 1994-02-08 Semiconductor circuit board

Country Status (1)

Country Link
JP (1) JPH07221414A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001339049A (en) * 2000-05-30 2001-12-07 Mitsubishi Electric Corp Semiconductor device, photomask and manufacturing method thereof
JP2002032739A (en) * 2000-07-17 2002-01-31 Anritsu Corp Binarization processor
JP2006191111A (en) * 2005-01-04 2006-07-20 Samsung Electronics Co Ltd Original sheet for flexible printed circuit board with cutting pattern formed, and display including flexible printed circuit board having the same cut
US8404496B2 (en) 1999-11-11 2013-03-26 Fujitsu Semiconductor Limited Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state
JP2014216548A (en) * 2013-04-26 2014-11-17 京セラ株式会社 Multiple piece wiring board
CN109148559A (en) * 2017-06-28 2019-01-04 矽创电子股份有限公司 Crystal circle structure
KR102356589B1 (en) * 2021-05-13 2022-02-08 박경주 Apparatus and method for monitoring process based on marker identification

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8404496B2 (en) 1999-11-11 2013-03-26 Fujitsu Semiconductor Limited Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state
US8759119B2 (en) 1999-11-11 2014-06-24 Fujitsu Semiconductor Limited Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state
JP2001339049A (en) * 2000-05-30 2001-12-07 Mitsubishi Electric Corp Semiconductor device, photomask and manufacturing method thereof
JP4667559B2 (en) * 2000-05-30 2011-04-13 ルネサスエレクトロニクス株式会社 Semiconductor device, photomask, and method of manufacturing semiconductor device
JP2002032739A (en) * 2000-07-17 2002-01-31 Anritsu Corp Binarization processor
JP2006191111A (en) * 2005-01-04 2006-07-20 Samsung Electronics Co Ltd Original sheet for flexible printed circuit board with cutting pattern formed, and display including flexible printed circuit board having the same cut
JP2014216548A (en) * 2013-04-26 2014-11-17 京セラ株式会社 Multiple piece wiring board
CN109148559A (en) * 2017-06-28 2019-01-04 矽创电子股份有限公司 Crystal circle structure
KR102356589B1 (en) * 2021-05-13 2022-02-08 박경주 Apparatus and method for monitoring process based on marker identification

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