JPS61225894A - Manufacture of multilayer printed interconnection board - Google Patents
Manufacture of multilayer printed interconnection boardInfo
- Publication number
- JPS61225894A JPS61225894A JP6611085A JP6611085A JPS61225894A JP S61225894 A JPS61225894 A JP S61225894A JP 6611085 A JP6611085 A JP 6611085A JP 6611085 A JP6611085 A JP 6611085A JP S61225894 A JPS61225894 A JP S61225894A
- Authority
- JP
- Japan
- Prior art keywords
- reference position
- hole
- multilayer printed
- position display
- inner layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
(産業上の利用分野]
本発明は多層印刷配線板用基板を製造する方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method of manufacturing a substrate for a multilayer printed wiring board.
(従来の技術)
多層印刷配線板は内層回路が形成された内層回路板を、
必要に応じて複数枚プリプレグを介して位置合せをして
重ね会せ、更にプリプレグを介して両面又は片面に、片
面銅張り積層板又は鋼箔を重ね合せ、加熱加圧して全体
を一体積膚後、内層回路板の少なくとも2つの隅に設け
られたケガキ用ガイドマークを露出させ、ケガキ用ガイ
ドマークを基準として内層回路の基準位置表示マーク位
置をケガキ、このケガキ位置を目印としてエンドミル切
削等により基準位置表示マークを露出させ基準位置表示
マークの中心に穴明しこの穴を基準として両面鋼張積層
板のスルーホール形成、回路形成をおこない製造してい
る。(Prior art) A multilayer printed wiring board consists of an inner layer circuit board on which an inner layer circuit is formed,
If necessary, align and overlap multiple sheets through prepreg, then overlay single-sided copper-clad laminates or steel foil on both sides or one side through prepreg, and heat and press to form a single skin. After that, expose the marking guide marks provided at at least two corners of the inner layer circuit board, mark the reference position display mark position of the inner layer circuit using the marking guide mark as a reference, and use the marked position as a guide by cutting with an end mill, etc. The reference position display mark is exposed, a hole is drilled in the center of the reference position display mark, and this hole is used as a reference to form through holes and circuits in the double-sided steel clad laminate.
(発明が解決しようとする問題点ン
従来、基準位置表示マークへの穴#JAはマーク・の中
心をねらい穴明するため次のような問題があった。多層
印刷配線板用基板を積層する場曾、内層回路板はおおよ
そ500ff1mにつきα11IIffl程度の収縮を
するため、内層回路板のパターンをあらかじめsoom
mにつき0.11111!1程度の割合で設計値(最終
製品とし要求されるパターンの値)大きく作っておき、
積層後パターンが正確に仕上る様にするが、内層回路板
の収縮量はパターン形状によっても異なり、一方収縮量
を決めるためには多数の実験が必衰な几め、多層印刷配
線板用基板によっては内層回路の位ff1精度が極めて
悪くなり、NC穴明機によりスルーホール穴明した場合
、スルーホール穴と内層パターンとの確実な導通あるい
は絶縁が望めなくなる場合があった。第2図を用いて詳
しく説明する。(Problems to be Solved by the Invention) Conventionally, the hole #JA for the reference position display mark was aimed at the center of the mark, which caused the following problems. Since the inner layer circuit board shrinks by approximately α11Iffl per 500ff1m, the pattern of the inner layer circuit board should be zoomed in advance.
The design value (the value of the pattern required for the final product) is made larger at a ratio of about 0.11111!1 per m,
It is necessary to ensure that the pattern is accurately finished after lamination, but the amount of shrinkage of the inner layer circuit board varies depending on the pattern shape, and on the other hand, determining the amount of shrinkage requires a large number of experiments. The accuracy of ff1 in the inner layer circuit becomes extremely poor, and when through-holes are drilled using an NC drilling machine, reliable conduction or insulation between the through-holes and the inner layer pattern may not be expected. This will be explained in detail using FIG.
基準位置表示マークにあけらnた穴ykGo、Gtとし
%Go を原点とし、GoとGt f結ぶ直IV51
をX座標とし、G1(a、o)とすると、スルーホール
穴はG。を原点として穴明(必要な回路加工)される。Hole drilled in the reference position display mark ykGo, Gt, %Go as the origin, straight line IV51 connecting Go and Gtf
If the X coordinate is G1 (a, o), then the through hole is G. Holes are drilled (necessary circuit processing) using this as the starting point.
ここで内層回路板の収縮量が子側よシ小さいとすると、
本来あるべき(設計値) G。Here, if the amount of shrinkage of the inner layer circuit board is smaller than that of the child side, then
Should be (design value) G.
Gsピッチ;Aは製品のGoGピッチaよシ小となる。Gs pitch: A is smaller than GoG pitch a of the product.
その結果Goより最も遠いパターンでスルーホール穴と
パターンのずれ量が最大とな94通あるいは絶縁が不確
実となる。As a result, in the pattern farthest from Go, the amount of deviation between the through-hole hole and the pattern is maximum, resulting in 94 lines or insulation becomes uncertain.
本発明は、設計値に近い回路加工を簡単に行い得る多層
印刷配線板の製造性を提供するものである。The present invention provides manufacturability of a multilayer printed wiring board in which circuit processing close to design values can be easily performed.
(問題点を解決するための手段)
本発明は、内層回路、少なくとも2ケの基準位置表示マ
ークが形成された内層回路板を備えた多層印刷配線板用
基板を%X線により基準位置表示マークを透視し、基準
位置表示マーク間ピッチを測定し、設計値と照合し、基
準位置表示マークの位置に補正値を加えて穴明し、この
穴を基準にし必要な回路加工を行うこと1r:特徴とす
るものである。(Means for Solving the Problems) The present invention provides reference position display marks on a multilayer printed wiring board substrate equipped with an inner layer circuit board and an inner layer circuit board on which at least two reference position display marks are formed using %X-rays. Measure the pitch between the reference position display marks, compare it with the design value, add a correction value to the position of the reference position display mark, drill a hole, and perform the necessary circuit processing using this hole as a reference.1r: This is a characteristic feature.
すなわち第2図のような場合では設計値Aは実測値aよ
り小であるから、Goの穴はG1方向に(a−A)/2
移動して穴明(設計値にせ致して設定さnている穴明機
で穴明)することによシ、スルーホール穴とパターンと
のfrt、iNは[F]t−(oyo)に穴明した場合
比較して半分にすることが可能である。In other words, in the case shown in Figure 2, the design value A is smaller than the actual measurement value a, so the Go hole is (a-A)/2 in the G1 direction.
By moving and drilling (drilling with a drilling machine set according to the design value), the frt between the through-hole hole and the pattern, iN is [F]t-(oyo). If it is clear, it is possible to halve it by comparison.
移動する距離は(a−A)/2〜(a−A)/4である
ことが好ましい。The moving distance is preferably (a-A)/2 to (a-A)/4.
第2図は本発明に用いらnる装置を示すもので以下図面
により説明する。FIG. 2 shows an apparatus used in the present invention, which will be explained below with reference to the drawings.
1はマグネスケール等の測長機能を有するXYテーブル
で、製品2が搭載されるテーブル面については、X線減
衰の少ない、ガラスプラスチック等で作られるXYテー
ブル1は製品を固定するクランプ3t−有し、テーブル
Inに製品2とテーブルが粗位置決めできる様、XY軸
に平行なlJ#(又はガイド)を入れらnておりXYテ
ーブル1の垂線上に、XWI照射管4の中心軸と撮像管
5の中心軸が乗り、かつXYテーブルをはさむべく両管
を配置し、撮像管5よりX軸方同圧l1ill離れて平
行にドリル6を配置する。1 is an XY table with a length measurement function such as Magnescale, and the table surface on which the product 2 is mounted is made of glass plastic, etc., which has low X-ray attenuation. In order to roughly position the product 2 and the table, a lJ# (or guide) parallel to the XY axes is installed on the table In, and the central axis of the XWI irradiation tube 4 and the image pickup tube are placed on the perpendicular to the XY table 1. Both tubes are arranged so that the center axis of the image pickup tube 5 rests thereon and the XY table is sandwiched therebetween, and a drill 6 is arranged parallel to the image pickup tube 5 at the same pressure l1ill in the X-axis direction.
さらに撮像管5の中心位置はモニターテレビ7表示面の
どの位置になるかをあらかじめ調べておく。Furthermore, it is determined in advance where the center position of the image pickup tube 5 will be on the display surface of the monitor television 7.
この様な装置において、XYテーブル1上に標線に製品
端面をあわせて製品2を置き、クランプ3により製品を
固定し次にXYテーブル1を移動し、撮像管5のはぼ直
下に別に設けているケガキ用ガイドマークが来る様にす
る。°標線とケガキ用ガイドマークの相対位fitは、
ケガキ用ガイドマークが内層回路形成段階であらかじめ
決っているので、マグネスケールで測長すれば容易粗位
置決めできる。In such a device, a product 2 is placed on an XY table 1 with the end face of the product aligned with the marked line, the product is fixed with a clamp 3, the XY table 1 is moved, and a separate product is placed directly under the image pickup tube 5. Make sure that the scribing guide marks shown are aligned. °The relative position of the gauge line and the marking guide mark is as follows:
Since the marking guide marks are predetermined at the stage of forming the inner layer circuit, rough positioning can be easily determined by measuring the length with a Magnescale.
次にxI!11’を照射し、モニターテレビにケガキ用
ガイドマークを写し出し、そニターテレビ7であらかじ
め撮像管5の中心位置として、もとめてお−た位置にガ
イドマークが来る様、XYテーブル1を微調整した後、
基準位を表示マークの座標をもとめる。Next xI! 11' was irradiated, a guide mark for marking was projected on the monitor TV, and the XY table 1 was finely adjusted on the monitor TV 7 so that the guide mark was placed at the position that had been determined in advance as the center position of the image pickup tube 5. rear,
Display the reference position and find the coordinates of the mark.
もう一つの基準位置表示マークの座標も同様にしてもと
める。The coordinates of the other reference position display mark are determined in the same manner.
基準位置表示マーク間ピッチtat−設計値Aと照甘し
補正値1a−AI/2と補正の方向を決める。簡単のた
めa>Aで第2図の様な状態に製品2があるとし、撮像
管5の中心憩をXYテーブル1との交点を(0,0)と
し、ドリル6とXYテーブル1との交点t−(j、o
)としa〉Iとし、さらKGo(o、o)、 Gt(a
、o)とすると、穴明をし、Gl の穴明け(a−1,
o)でもn −A a+A
(a−12)すなわち(−# +−T−,O)でも良い
。以上簡単のため色々の条件をつけたが補正値の大きさ
、方向、座標値Fi電子計算機と連動させることにより
容易にもとめることができる。The direction of correction is determined by the pitch tat between the reference position display marks - the design value A and the illumination correction value 1a - AI/2. For simplicity, it is assumed that the product 2 is in a state as shown in Fig. 2 with a>A, the intersection of the center point of the image pickup tube 5 with the XY table 1 is (0,0), and the intersection between the drill 6 and the XY table 1. Intersection t-(j, o
) and a〉I, then KGo(o, o), Gt(a
, o), then make a hole and make a hole for Gl (a-1,
o) or n −A a+A (a−12), that is, (−# +−T−, O). Various conditions have been added for the sake of simplicity, but the magnitude, direction, and coordinate values of the correction value Fi can be easily determined by linking with an electronic computer.
Go の穴を基準として、設Ct値に合致して設定さn
ている穴明後で穴明は及び必要な回路加工を行う。Set n to match the set Ct value using the Go hole as a reference.
After drilling the holes, perform drilling and necessary circuit processing.
(発明の効果)
本発明の方法に於又は同一の内層回路板を用いた多層印
刷配線板用基板でも、基準位置表示マークの穴を適切に
補正し穴明することにより、内層パターンとスルーホー
ルの穴とのすn111を半減させることが可能とな9、
精度向上が可能となる。(Effects of the Invention) In the method of the present invention, or even in a multilayer printed wiring board board using the same inner layer circuit board, by appropriately correcting and drilling the hole of the reference position display mark, the inner layer pattern and the through hole can be adjusted. It is possible to reduce the amount of n111 by half with the hole 9,
Accuracy can be improved.
さらに基準位置表示マークをX線により直接透視するの
で、エンドミル等によるマークの露出作業も不妥となる
。Furthermore, since the reference position display mark is directly viewed through X-rays, the work of exposing the mark using an end mill or the like becomes unsuitable.
第1図は本発明で使用さnる基準位置表示マークへの穴
明装置の側面図、第2図は多層印刷配線板用基板にスル
ーホール穴明した状態を示す平面図である。
符号の説明
I XYテーブル 2 製品
3 クランプ 4 X#照射管5 撮像管
6 ドリル
7 モニターテレビFIG. 1 is a side view of a device for drilling a reference position indicating mark used in the present invention, and FIG. 2 is a plan view showing a state in which through-holes are drilled in a substrate for a multilayer printed wiring board. Explanation of symbols I XY table 2 Product 3 Clamp 4 X# irradiation tube 5 Image tube
6 Drill 7 Monitor TV
Claims (1)
形成された内層回路板を備えた多層印刷配線板用基板を
、X線により基準位置表示マークを透視し、基準位置表
示マーク間ピッチを測定し、設計値と照合し、基準位置
表示マークの位置に補正値を加えて穴明し、この穴を基
準にし必要な回路加工を行うことを特徴とする多層印刷
配線板用基板の製造法。1. A multilayer printed circuit board equipped with an inner layer circuit board on which at least two reference position display marks are formed, see through the reference position display marks using X-rays, and measure the pitch between the reference position display marks. A method for manufacturing a substrate for a multilayer printed wiring board, which comprises: checking the design value, adding a correction value to the position of the reference position display mark, drilling a hole, and performing necessary circuit processing using the hole as a reference.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6611085A JPS61225894A (en) | 1985-03-29 | 1985-03-29 | Manufacture of multilayer printed interconnection board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6611085A JPS61225894A (en) | 1985-03-29 | 1985-03-29 | Manufacture of multilayer printed interconnection board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61225894A true JPS61225894A (en) | 1986-10-07 |
Family
ID=13306421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6611085A Pending JPS61225894A (en) | 1985-03-29 | 1985-03-29 | Manufacture of multilayer printed interconnection board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61225894A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0360193A (en) * | 1989-07-28 | 1991-03-15 | Tanaka Kikinzoku Kogyo Kk | Manufacture of multilayer printed circuit board |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5546563A (en) * | 1978-09-30 | 1980-04-01 | Matsushita Electric Works Ltd | Guide mark for perforating multilayer printed circuit board |
JPS5578597A (en) * | 1978-12-08 | 1980-06-13 | Fujitsu Ltd | Method of fabricating multilayer printed circuit board |
JPS56126999A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Reference pattern position automatic detecting system in internal layer of multilayer printed board or like |
JPS57101907A (en) * | 1980-12-17 | 1982-06-24 | Fujitsu Ltd | Drilling control method of numerical control drilling machine |
-
1985
- 1985-03-29 JP JP6611085A patent/JPS61225894A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5546563A (en) * | 1978-09-30 | 1980-04-01 | Matsushita Electric Works Ltd | Guide mark for perforating multilayer printed circuit board |
JPS5578597A (en) * | 1978-12-08 | 1980-06-13 | Fujitsu Ltd | Method of fabricating multilayer printed circuit board |
JPS56126999A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Reference pattern position automatic detecting system in internal layer of multilayer printed board or like |
JPS57101907A (en) * | 1980-12-17 | 1982-06-24 | Fujitsu Ltd | Drilling control method of numerical control drilling machine |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0360193A (en) * | 1989-07-28 | 1991-03-15 | Tanaka Kikinzoku Kogyo Kk | Manufacture of multilayer printed circuit board |
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