JPH1146068A - Evaluation of process of manufacturing multilayered interconnection board - Google Patents

Evaluation of process of manufacturing multilayered interconnection board

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Publication number
JPH1146068A
JPH1146068A JP20120197A JP20120197A JPH1146068A JP H1146068 A JPH1146068 A JP H1146068A JP 20120197 A JP20120197 A JP 20120197A JP 20120197 A JP20120197 A JP 20120197A JP H1146068 A JPH1146068 A JP H1146068A
Authority
JP
Japan
Prior art keywords
hole
inspection
pattern
board
evaluation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20120197A
Other languages
Japanese (ja)
Other versions
JP3651539B2 (en
Inventor
Kaiji Nakazawa
開司 仲澤
Hideo Uehara
日出男 上原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20120197A priority Critical patent/JP3651539B2/en
Publication of JPH1146068A publication Critical patent/JPH1146068A/en
Application granted granted Critical
Publication of JP3651539B2 publication Critical patent/JP3651539B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To inspect a multilayered board for evaluation use, which is transferred separately from multilayered boards, which are products and is manufactured at the time of the rise of a process line of manufacturing a multilayered interconnection board, comprising processes of manufacturing the multilayered interconnection board, and to evaluate the conditions of treatments of the processes. SOLUTION: A multilayered interconnection board is manufactured by such a method that before a rise of a process line of manufacturing the multilayer interconnection board, which comprises a wiring board lamination process, a through-hole prime-perforating process, a through-hole plating process and a surface and rear layer-patterning process, an internal layer board arranged with patterns 2 for void inspection use is held between surface and rear boards to laminate wiring boards, a multilayered board 10 for evaluation use with patterns 3 for hole deviation inspection use and patterns 4 for through-hole continuity inspection use, which are respectively formed on the surface and rear of this laminated board, is manufactured separately from multilayered boards, which are products, the above respective patterns 2, 3 and 4 for inspection use of the board 10 are inspected and the conditions of treatments of the above respective processes and the states of the processes are evaluated by the result of this inspection.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多層配線基板の製
造プロセスの評価方法に係り、とくに基板の積層−スル
ーホールの下孔明け−下孔めっきプロセス−表裏面層パ
ターニングプロセスの評価方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a manufacturing process of a multilayer wiring board, and more particularly, to a method for evaluating a substrate lamination, a through hole drilling, a pilot plating process, and a front and back layer patterning process.

【0002】多層配線基板の製造プロセスラインのこれ
らのプロセスを経て完成された多層配線基板を検査し、
その検査結果から各プロセスの処理条件を評価する方法
では、ラインに検査結果をフィードバックするのが遅く
なったり、不良品を発生したプロセス元が判りにくいな
どの問題があって、専門の検査員でなくとも誰でも同一
基準で基板の検査ができて処理条件の評価が同一の尺度
で迅速かつ容易にできることが要望されている。
Inspection of a multilayer wiring board completed through these processes in a multilayer wiring board manufacturing process line,
In the method of evaluating the processing conditions of each process from the inspection results, there are problems such as slow feedback of the inspection results to the line and it is difficult to identify the process source that caused the defective product. It is desired that at least anyone can inspect a substrate on the same basis and evaluate processing conditions quickly and easily on the same scale.

【0003】[0003]

【従来の技術】多層配線基板は、別プロセスにより片面
に内層となる配線パターンを形成した配線基板を用意
し、複数の配線基板の間にプリプレグを挟んで位置合わ
せして重ね、それを熱圧着して積層し多層配線基板とす
る。
2. Description of the Related Art A multi-layered wiring board is prepared by preparing a wiring board having an inner layer wiring pattern formed on one side by a separate process, aligning a plurality of wiring boards with a prepreg sandwiched therebetween, and thermocompression bonding. To form a multilayer wiring board.

【0004】多層配線基板を製作する製造プロセスライ
ンは、前記配線基板を積層する積層プロセスと、大小径
のスルーホール(大径はリード部品を接続し、小径は層
間を接続する)の下孔明けプロセスと、その下孔にめっ
きを施すめっきプロセスと、積層された多層配線基板の
表裏層にスルーホールランドを含む配線パターンを形成
するパターニングプロセスとを含んで構成されている。
A manufacturing process line for manufacturing a multilayer wiring board includes a laminating process for laminating the wiring boards and a drilling of large and small diameter through holes (a large diameter connects lead components, and a small diameter connects between layers). It is configured to include a process, a plating process of plating a lower hole thereof, and a patterning process of forming a wiring pattern including through-hole lands on the front and back layers of the laminated multilayer wiring board.

【0005】従来の評価方法は、これらのプロセスを経
て完成された製品(多層配線基板)を抜き取り、ボイド
発生の有無、スルーホールの位置ずれやスルーホールの
導通検査によるめっき不良(必要に応じてサンプリング
断面検査を行う)を検査し、その検査結果から各プロセ
スの処理や加工条件を評価する。
In the conventional evaluation method, a product (multilayer wiring board) completed through these processes is extracted, and the presence or absence of voids, displacement of through-holes, and plating defects by inspection of continuity of through-holes (if necessary) Sampling cross-section inspection is performed), and the processing and processing conditions of each process are evaluated based on the inspection result.

【0006】検査は、専門の検査員あるいはライン作業
者自身で行っている。
[0006] The inspection is performed by a specialized inspector or a line worker himself.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、このよ
うな上記評価方法によれば、製品完成後に抜き取ったサ
ンプル品では、仕様が異なれば大きさ、基板の積層数、
スルーホールなどの位置及び数、配線パターンの形状な
どが一定していないため統一した尺度で評価ができない
とか、多層配線基板の種類が多様化し見逃しなどの検査
ミスもあって欠陥箇所の検出力が低いとか、また例えば
スルーホールの数が少ないと評価する母数が小さくなる
ため多数のサンプル品が必要になるといった問題があっ
た。
However, according to the above-mentioned evaluation method, the size, the number of laminated substrates, and
The position and number of through holes, etc., and the shape of the wiring pattern are not constant and cannot be evaluated on a unified scale, or the type of multilayer wiring board is diversified and there are inspection errors such as missing For example, there is a problem that a large number of sample products are required because the parameter to be evaluated is low or the number of through holes is small, for example.

【0008】上記問題点に鑑み、本発明は製造プロセス
ラインの立ち上がり時に製品とは別に流して製作した評
価用多層基板を検査し、各プロセスの処理条件を評価す
る多層配線基板の製造プロセスの評価方法を提供するこ
とを目的とする。
In view of the above problems, the present invention examines a multilayer wiring board manufactured separately from a product at the start of a manufacturing process line and evaluates the processing conditions of each process. The aim is to provide a method.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、本発明の多層配線基板の製造プロセスの評価方法に
おいては、配線基板の積層プロセスとスルーホールの下
孔明けプロセスとスルーホールめっきプロセスと表裏面
層パターニングプロセスとを含む多層配線基板の製造プ
ロセスラインの立ち上がり前に、表裏基板との間にボイ
ド検査用パターンを配置した内層基板を挟んで積層し、
該積層基板の表裏面に孔ずれ検査用パターンとスルーホ
ール導通検査用パターンとを形成した評価用多層基板を
製品とは別に製作し、該評価用多層基板の前記それぞれ
の検査用パターンを検査し、該検査結果により前記それ
ぞれのプロセスの処理条件及び状態を評価するように構
成する。
In order to achieve the above object, a method for evaluating a multilayer wiring board manufacturing process according to the present invention comprises a wiring board laminating process, a through-hole preparation process, and a through-hole plating process. Before the start of the manufacturing process line of the multilayer wiring board including the front and back layer patterning process, the inner layer substrate on which the void inspection pattern is arranged is laminated between the front and back substrates,
A multilayer board for evaluation in which a pattern for hole displacement inspection and a pattern for through-hole continuity inspection are formed on the front and back surfaces of the laminated substrate is manufactured separately from the product, and the respective inspection patterns of the multilayer board for evaluation are inspected. The processing conditions and state of each of the processes are evaluated based on the inspection result.

【0010】このように構成することにより、基板積層
前に形成されたボイド検査用パターンで積層プロセスに
おける残留ガスによるボイド発生の有無がチェックでき
る。また、積層基板の四隅の一隅を基準に周縁部に明け
たスルーホールの下孔で孔ずれ検査用パターンを形成
し、その位置ずれを検査することにより、下孔明けプロ
セスにおけるドリルヘッドの直交方向の位置出し不良及
び加工テーブルへのセット不良をチェックすることがで
きる。
With this configuration, it is possible to check the presence or absence of voids due to residual gas in the laminating process by using the void inspection pattern formed before laminating the substrates. In addition, a hole misalignment inspection pattern is formed with a prepared hole of the through hole formed in the peripheral portion with reference to one of the four corners of the laminated substrate, and the misalignment is inspected. Can be checked for positioning failure and setting failure on the processing table.

【0011】また、表裏面層パターニングプロセスにお
いて、スルーホール導通検査用パターンは、複数のスル
ーホールを表裏面層で交互に連続接続した1本の配線と
して形成することにより、その両端2点の導通検査でめ
っきプロセスにおけるスルーホールのめっき不良をチェ
ックすることができる。
In the front and back layer patterning process, the through hole continuity test pattern is formed as a single wiring in which a plurality of through holes are connected alternately and continuously on the front and back layers, so that the continuity at two points at both ends is formed. Inspection can check the plating failure of the through hole in the plating process.

【0012】[0012]

【発明の実施の形態】以下、図面に示した実施例に基づ
いて本発明の要旨を詳細に説明する。本発明の多層配線
基板の製造プロセスの評価方法は、製造プロセスライン
の立ち上がり時に製品とは別に流して製作した評価用多
層基板を検査し、その検査結果により配線基板の積層プ
ロセスと、スルーホールの下孔明けプロセスと、該下孔
のめっきプロセスと、表裏面に配線パターンを形成する
パターニングプロセスの処理条件や状態を評価する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention will be described below in detail with reference to the embodiments shown in the drawings. The evaluation method of the manufacturing process of the multilayer wiring board of the present invention inspects an evaluation multilayer board manufactured separately from a product at the start of the manufacturing process line, and based on the inspection result, a wiring board laminating process and a through hole. The processing conditions and conditions of the pilot hole forming process, the plating process of the pilot hole, and the patterning process of forming a wiring pattern on the front and back surfaces are evaluated.

【0013】評価用多層基板の検査対象としては、単層
とは異なり積層された多層配線基板であることからボイ
ド発生の有無と、下孔の位置ずれ、又はスルーホールに
対するスルーホールランドの位置ずれと、スルーホール
の電気的導通不良である。
The inspection target of the multilayer board for evaluation is not a single layer but a stacked multilayer wiring board. Therefore, the presence or absence of voids, the displacement of the prepared hole, or the displacement of the through-hole land with respect to the through-hole are examined. And electrical conduction failure of the through hole.

【0014】図1は本発明の一実施例の評価用基板の平
面図を示す。図は、大きさが縦510mm×横340m
m、厚さが2mmで表裏層を含め6層の評価用多層基板
10を例示する。評価用多層基板10の四隅に図示しな
い孔明け装置の加工テーブルにセットする直径5mmの
位置決め孔1を配置し、その内側の領域(点線で囲まれ
た領域A)にボイド検査用パターン2(図2の部分拡大
図参照)と、孔ずれ検出用パターン3(図3の部分拡大
図参照)と、スルーホール導通検査用パターン4(図4
の部分拡大図参照)を配置する。
FIG. 1 is a plan view of an evaluation board according to an embodiment of the present invention. The figure shows a size of 510 mm long x 340 m wide
An example of the evaluation multi-layer substrate 10 having a thickness of 2 mm and a thickness of 2 mm and including front and back layers is illustrated. Positioning holes 1 having a diameter of 5 mm to be set on a processing table of a not-shown drilling device are arranged at four corners of the multilayer substrate 10 for evaluation, and a void inspection pattern 2 (see FIG. 2), a hole shift detecting pattern 3 (see a partial enlarged view of FIG. 3), and a through-hole continuity inspection pattern 4 (see FIG. 4).
(Refer to the partially enlarged view of Figure 2).

【0015】まず、ボイド検査用パターン2について説
明する。(図1,図2参照) ボイド発生要因の1つは、積層プロセスにおいて、溶融
したプリプレグの流れが悪くて内層とプリプレグ間にガ
スが残って密着不足となるためで、製品基板ではべた状
の配線パターンで囲まれた部分に生じ易く、製品基板の
中央部分に発生し易い。
First, the void inspection pattern 2 will be described. (Refer to FIG. 1 and FIG. 2) One of the void generation factors is that the flow of the molten prepreg is poor in the lamination process, and the gas remains between the inner layer and the prepreg, resulting in insufficient adhesion. It is easy to occur in the portion surrounded by the wiring pattern and easily in the center of the product substrate.

【0016】そのため、ボイド検査用パターン2は、図
1乃至図2に示すように、4つのかぎ形パターン21a
を互いに対称に幅5mmの隙間G(ガス抜き通路)を開
けて1辺が30mm方形の四隅に配置し、内側に1辺が
20mm方形のパターンのない領域S(図2)を有する
格子状べたパターン21で構成し、ボイドが発生し易い
内層(例えば、第3または第4内層)の中央領域B(図
1)に複数箇所配置する。(図1は3箇所を破線でなく
実線で示す) このボイド検査用パターンを検査することにより、ボイ
ド発生の有無を検査することができる。
Therefore, as shown in FIGS. 1 and 2, the void inspection pattern 2 has four key-shaped patterns 21a.
Are symmetrically arranged with a gap G (gas vent passage) having a width of 5 mm, arranged at four corners having a side of 30 mm square, and a grid-shaped solid having a region S (FIG. 2) having a side of 20 mm square without a pattern inside. A plurality of patterns 21 are arranged in a central region B (FIG. 1) of an inner layer (for example, a third or fourth inner layer) in which voids are easily generated. (In FIG. 1, three locations are indicated by solid lines instead of broken lines.) By inspecting the void inspection pattern, the presence or absence of voids can be inspected.

【0017】つぎに、孔ずれ検出用パターン3について
説明する。(図1,図3参照) 下孔の位置ずれの要因の1つは、孔明け精度である。孔
明け装置のドリルヘッドの直交方向の位置出し不良や加
工テーブルへのセット不良が原因となり、積層厚さが厚
いほどドリルが曲がって裏面では位置ずれする場合もあ
る。
Next, the hole shift detecting pattern 3 will be described. (See FIGS. 1 and 3.) One of the causes of the misalignment of the pilot hole is the drilling accuracy. Due to poor positioning of the drill head of the drilling device in the orthogonal direction and poor setting on the processing table, the thicker the lamination thickness, the more the drill may bend and the rear surface may be displaced.

【0018】孔ずれ検出用パターン3は、スルーホール
の下孔明けプロセスにおいて、積層基板の四隅を含む周
縁部に複数の下孔3aを明けて構成する。図3に示すよ
うに、この下孔3aの直径は製品と同じ最小径の0.3
5mm(斜線部分)とし、1辺が最小寸法0.75mm
の正方形のスルーホールランド3bの中心に明ける。
The hole shift detecting pattern 3 is formed by drilling a plurality of pilot holes 3a in a peripheral portion including four corners of the laminated substrate in a through hole drilling process. As shown in FIG. 3, the diameter of the prepared hole 3a is 0.3 mm, which is the same minimum diameter as the product.
5 mm (shaded area), one side is 0.75 mm minimum dimension
At the center of the square through-hole land 3b.

【0019】下孔3aは、積層基板の四隅の一隅を基準
(原点P)にステッピングして明けるため一定方向にず
れる傾向があり、原点Pから離れるほどずれが累積され
る。そのため、下孔は四隅のどの隅を原点Pにしても検
査可能なように領域Aの四隅を含んで例えば、2辺の6
箇所に均等配置する。
The pilot hole 3a tends to shift in a certain direction because the hole is formed by stepping one of the four corners of the laminated substrate with respect to the reference (origin P), and the deviation tends to accumulate as the distance from the origin P increases. For this reason, the prepared hole includes four corners of the area A, for example, including two corners of 6 so that inspection can be performed even if any of the four corners is the origin P.
Place them evenly in the place.

【0020】この孔ずれ検出用パターンを検査すること
により、スルーホールがスルーホールランドの中心にな
い場合、スルーホールの位置ずれかスルーホールランド
の位置ずれかの何れかであり、それぞれを検査し判定す
る。あるいは、スルーホールが表裏面間で横ずれしてい
ないか検査する。
By inspecting the hole misalignment detection pattern, if the through hole is not located at the center of the through hole land, it is either the misalignment of the through hole or the misalignment of the through hole land. judge. Alternatively, it is inspected whether the through-hole is laterally shifted between the front and back surfaces.

【0021】つぎに、スルーホール導通検査用パターン
4について説明する。(図1,図4参照) スルーホールのめっき不良を検査するために、積層基板
を中央領域Bで2分した両側の領域C,Dのそれぞれに
スルーホール導通検査用パターン4を配置する。なお、
領域D内のスルーホール導通検査用パターン4は図示を
省略している。
Next, the through hole conduction inspection pattern 4 will be described. (See FIGS. 1 and 4.) In order to inspect plating defects in the through-holes, the through-hole continuity inspection pattern 4 is arranged in each of the two regions C and D obtained by dividing the laminated substrate into two in the central region B. In addition,
The through hole continuity inspection pattern 4 in the region D is not shown.

【0022】このスルーホール導通検査用パターン4
は、下孔明けプロセスにおいて、横方向Xにピッチ2.
54mm、縦方向Yにピッチ5.08mmで配置される
0.75mm角のスルーホールランド4bの中心に小径
0.35mmの下孔4aを明け、さらにめっきプロセス
においてこの下孔4aにめっき(図示略)を施し、さら
に公知のフォトリソグラフィ技術により表裏面の銅箔を
エッチングして配線パターンを形成するパターニングプ
ロセスにおいて、スルーホールランド4bとスルーホー
ルランド4b間を表面層の接続パターン4b−1と裏面
層の接続パターン4b−2とで交互に接続して形成した
一本の配線で構成する。
This through hole continuity inspection pattern 4
Has a pitch of 2. in the lateral direction X in the piloting process.
A pilot hole 4a having a small diameter of 0.35mm is drilled at the center of a 0.75mm square through-hole land 4b arranged at a pitch of 5.08mm in the vertical direction 54mm and further plated in the pilot hole 4a in the plating process (not shown). ), And furthermore, in a patterning process of etching a copper foil on the front and back surfaces by a known photolithography technique to form a wiring pattern, a connection pattern 4b-1 of the surface layer and the back surface are formed between the through-hole lands 4b. It is composed of one line formed by connecting alternately with the layer connection pattern 4b-2.

【0023】この1本の配線、即ちスルーホール導通検
査用パターンの両端を導通検査することでスルーホール
めっきの不良を検査することができる。なお、縦方向Y
のピッチ5.08mmで配置された小径0.35mmの
下孔4aの中間にリード部品接続用の大径0.75mm
の下孔5aを明け、直径1.10mmのスルーホールラ
ンド5bを形成しておき、前記孔ずれ及び導通を検査し
ている。
By inspecting the continuity of both ends of this single wiring, that is, the pattern of the through-hole continuity inspection pattern, it is possible to inspect a defect of the through-hole plating. Note that the vertical direction Y
A large diameter 0.75 mm for connecting lead components is located in the middle of a prepared hole 4a having a small diameter of 0.35 mm and a pitch of 5.08 mm.
A through hole land 5b having a diameter of 1.10 mm is formed, and the hole displacement and conduction are inspected.

【0024】このように、製造プロセスラインの立ち上
がり時に製品とは別に流してボイド検査用パターンと、
孔ずれ検出用パターンと、スルーホール導通検査用パタ
ーンとを形成した評価用多層基板を検査し、その検査結
果により配線基板の積層プロセスと、スルーホールの下
孔明けプロセスと、該下孔のめっきプロセスと、表裏面
に配線パターンを形成するパターニングプロセスの処理
条件や状態を評価することができる。
As described above, at the start of the manufacturing process line, the pattern for void inspection is supplied separately from the product.
Inspect the multilayer board for evaluation on which the pattern for hole displacement detection and the pattern for through hole continuity inspection are formed, and based on the inspection results, a wiring board laminating process, a through hole pre-drilling process, and plating of the prepared hole. It is possible to evaluate the process and the processing conditions and conditions of the patterning process for forming a wiring pattern on the front and back surfaces.

【0025】また、評価用多層基板は前記検査用パター
ンを一定の基準で形成しているため、見逃しなどの検査
ミスも殆どなく、仕様の異なる多層配線基板に対しても
同じ検査用パターンで検査すため、各プロセスを統一し
た尺度で評価ができる。
Further, since the inspection pattern is formed on the evaluation multilayer substrate according to a predetermined standard, there is almost no inspection error such as oversight, and the same inspection pattern can be used to inspect multilayer wiring substrates having different specifications. Therefore, each process can be evaluated on a unified scale.

【0026】また、評価用多層基板に形成するスルーホ
ール導通検査用パターンのスルーホールを例えば、20
000個形成して1本の配線に接続することで母数を格
段に大きくできるため、スルーホールめっきプロセスの
評価の精度を一層に向上することができる。
Further, the through-holes of the through-hole continuity inspection pattern formed on the evaluation multilayer substrate are, for example, 20 holes.
By forming 000 pieces and connecting them to one wiring, the parameter can be significantly increased, so that the accuracy of the evaluation of the through-hole plating process can be further improved.

【0027】[0027]

【発明の効果】以上、詳述したように本発明によれば、
製造プロセスラインの立ち上がり前に流して製作した評
価用多層基板に一定基準で形成された検査用パターン
は、専門の検査員でなくとも誰でも同一尺度で検査がで
き、その検査結果を早期にラインの各プロセスにフィー
ドバックすることにより、不良品の発生したプロセスの
処理条件や状態の評価が迅速かつ容易にできるため、種
々の仕様の多層配線基板を高品質に安定して製作できる
といった産業上極めて有用な効果を発揮する。
As described in detail above, according to the present invention,
Inspection patterns formed according to a certain standard on a multilayer board for evaluation manufactured by flowing before the start of the manufacturing process line can be inspected on the same scale by anyone, even non-specialized inspectors, and the inspection results can be lined up at an early stage. By providing feedback to each of the above processes, it is possible to quickly and easily evaluate the processing conditions and conditions of the process in which a defective product has occurred. Demonstrate useful effects.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明による一実施例の評価用多層基板の平
面図
FIG. 1 is a plan view of an evaluation multilayer substrate according to an embodiment of the present invention.

【図2】 図1のボイド検査用パターンの部分拡大図FIG. 2 is a partially enlarged view of the void inspection pattern of FIG. 1;

【図3】 図1の孔ずれ検出用パターンの部分拡大図FIG. 3 is a partially enlarged view of a hole misalignment detection pattern in FIG. 1;

【図4】 図1のスルーホール導通検査用パターン及び
大径スルーホールの部分拡大図
FIG. 4 is a partially enlarged view of the through-hole continuity inspection pattern and the large-diameter through-hole of FIG. 1;

【符号の説明】[Explanation of symbols]

2:ボイド検査用パターン 3:孔ずれ検出用パターン 4:スルーホール導通検査用パターン 2: Void inspection pattern 3: Hole misalignment detection pattern 4: Through hole continuity inspection pattern

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 配線基板の積層プロセスとスルーホール
の下孔明けプロセスとスルーホールめっきプロセスと表
裏面層パターニングプロセスとを含む多層配線基板の製
造プロセスラインの立ち上がり前に、 表裏基板との間にボイド検査用パターンを配置した内層
基板を挟んで積層し、該積層基板の表裏面に孔ずれ検査
用パターンとスルーホール導通検査用パターンとを形成
した評価用多層基板を製品とは別に製作し、該評価用多
層基板の前記それぞれの検査用パターンを検査し、該検
査結果により前記それぞれのプロセスの処理条件及び状
態を評価することを特徴とする多層配線基板の製造プロ
セスの評価方法。
1. A multi-layer wiring board manufacturing process line including a wiring board laminating process, a through-hole drilling process, a through-hole plating process, and a front and back layer patterning process, before starting up between the front and back substrates. Laminate the inner layer substrate on which the void inspection pattern is arranged, and produce a multi-layer substrate for evaluation in which a hole deviation inspection pattern and a through hole continuity inspection pattern are formed on the front and back surfaces of the laminated substrate separately from the product, A method for evaluating a manufacturing process of a multilayer wiring board, comprising: inspecting the respective inspection patterns of the evaluation multilayer substrate; and evaluating processing conditions and states of the respective processes based on the inspection results.
【請求項2】 前記ボイド検査用パターンは、かぎ形パ
ターンを互いに対称に隙間を開けて方形の四隅に配置し
たべた状格子パターンで形成し、 前記孔ずれ検査用パターンは、前記積層基板の四隅を含
む周縁部の一隅を基準に該周縁部の複数箇所にスルーホ
ールで形成し、 前記スルーホール導通検査用パターンは、複数のスルー
ホール間を表面層の接続パターンと裏面層の接続パター
ンとで交互に接続して一本の配線で形成することを特徴
とする請求項1記載の多層配線基板の製造プロセスの評
価方法。
2. The void inspection pattern is formed by a solid lattice pattern in which key patterns are arranged at four corners of a square with a gap symmetrically formed therebetween, and the hole displacement inspection pattern is formed at four corners of the laminated substrate. The through-hole continuity inspection pattern is formed by connecting a plurality of through-holes with a connection pattern of a surface layer and a connection pattern of a back surface layer with respect to one corner of the periphery including the corner. The method for evaluating a multilayer wiring board manufacturing process according to claim 1, wherein the wirings are alternately connected to form a single wiring.
JP20120197A 1997-07-28 1997-07-28 Evaluation method for manufacturing process of multilayer wiring board Expired - Fee Related JP3651539B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20120197A JP3651539B2 (en) 1997-07-28 1997-07-28 Evaluation method for manufacturing process of multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20120197A JP3651539B2 (en) 1997-07-28 1997-07-28 Evaluation method for manufacturing process of multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH1146068A true JPH1146068A (en) 1999-02-16
JP3651539B2 JP3651539B2 (en) 2005-05-25

Family

ID=16437031

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3651539B2 (en)

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Publication number Priority date Publication date Assignee Title
JP2010267985A (en) * 2010-07-09 2010-11-25 Fuji Kiko Denshi Kk Multilayer printed wiring board, method of inspecting the multilayer printed wiring board, system of inspecting the multilayer printed wiring board, and method of manufacturing the multilayer printed wiring board
JP4602479B2 (en) * 2008-11-06 2010-12-22 富士機工電子株式会社 Multilayer printed wiring board, multilayer printed wiring board inspection method, multilayer printed wiring board inspection system, and multilayer printed wiring board manufacturing method
KR101454924B1 (en) * 2008-04-15 2014-10-27 현대자동차주식회사 PCB sample for evaluating quality
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Publication number Priority date Publication date Assignee Title
KR101454924B1 (en) * 2008-04-15 2014-10-27 현대자동차주식회사 PCB sample for evaluating quality
JP4602479B2 (en) * 2008-11-06 2010-12-22 富士機工電子株式会社 Multilayer printed wiring board, multilayer printed wiring board inspection method, multilayer printed wiring board inspection system, and multilayer printed wiring board manufacturing method
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JP2010267985A (en) * 2010-07-09 2010-11-25 Fuji Kiko Denshi Kk Multilayer printed wiring board, method of inspecting the multilayer printed wiring board, system of inspecting the multilayer printed wiring board, and method of manufacturing the multilayer printed wiring board
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CN105682379A (en) * 2016-01-25 2016-06-15 东莞联桥电子有限公司 Process for rapidly fabricating multi-layer circuit board

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