JPH04120767A - Logical ic - Google Patents

Abstract

PURPOSE:To prevent speed lowering of a Bi-CMOS circuit in low power supply voltage by performing high rate charging/discharging of a load capacity through the Bi-CMOS circuit in a parallel circuit of CMOS circuit and Bi-CMOS circuit and finally swinging the output potential upto the power supply voltage through the CMOS circuit. CONSTITUTION:A CMOS logical circuit 12 of 3 input NAND logic is connected between the input terminals 11 to 13 of a Bi-CMOS and an output terminal OUT. Since the CMOS logical circuit 12 is connected in parallel with the Bi- CMOS logical circuit 11, the CMOS logical circuit 12 makes an output terminals to perform a full swing to Vcc or GND after the Bi-CMOS logical circuit performs charging and discharging of a load at high speed. An ON current of an FET of a next stage to be connected to the output terminal OUT is lowered so as to be free from a danger of increased delay time, high speed operation of the Bi-CMOS logical gate is ensured even when an LSI is operated with a low power supply voltage.

Description

[Detailed Description of the Invention] [Industrial Application Fields] The present invention is applicable to large-scale logic integrated circuit design technology and logic L
The present invention relates to a technique that is particularly effective when applied to an intra-cell layout method of logic gates constituting an SI, and relates to a technique that is particularly effective when applied to a layout of a logic gate in which a Bi-0MO3 logic gate and a CMOS circuit are integrated, for example.

[Prior Art] In recent years, LSIs have been developed that have the advantages of both the low power consumption of CMOS circuits and the high speed of bipolar transistor circuits.
Bi-0MO3 logic gates have been put into practical use, and they are usually driven by a single 5V power supply like 0MO8 logic LSIs (v4 Baifukan, 1986).
Published on January and February 10th, "Ultra High Speed MOS Devices" No. 16
(See pages 2 to 167).

On the other hand, in recent years, as LSI miniaturization progresses, MO3L
In SI, if the power supply voltage remains constant at 5V, short channel effects, generation of hot electrons, decrease in breakdown voltage, etc. will occur.
Since various problems arise in device characteristics engineering, proposals have been made to lower the power supply voltage.

[Problems to be Solved by the Invention] However, in an LSI having a Bi-CMOS logic gate, when the power supply voltage is lowered from 5V to, for example, 3 to 3.5V in accordance with the miniaturization of the process, the base-emitter of the bipolar transistor Since the voltage VBE is constant (approximately 0.8V) regardless of the element size, the amplitude of the output signal of the Bi-CMOS logic gate is 2 for an input amplitude of 5V.
It becomes smaller by VBE, and there is a risk that the operating speed will decrease.

Therefore, a method has been proposed in which a BiCMOS circuit and a CMOS circuit are connected in parallel between the input and output terminals of a logic gate, and the same load is driven additively by a bipolar transistor and a FET (Japanese Patent Laid-Open No. 133721/1983). ).

However, this circuit system has the disadvantage that the cell area increases significantly.

That is, when designing the layout of a Bi-CMOS logic gate, the number of FETs having gates at the same potential becomes extremely large. There are two general methods that can be considered to efficiently layout this. One is to combine gate electrodes with the same potential into one line and connect multiple FETs in the direction of the gate electrode.
This is a method to reduce the wiring that connects gate electrodes of the same potential by arranging the gate electrodes. This method maintains the height in the pole direction at the same constant value as a CMOS circuit.

The former has the disadvantage that it is difficult to mix with CMOS circuits because the cell height is larger than that of CMOS circuits, and the latter has the disadvantage that the number of wirings connecting gate electrodes of the same potential increases, resulting in an increase in cell size. In either case, the degree of integration is reduced.

An object of the present invention is to provide a layout technique that can improve the degree of integration of Bi-CMOS logic gates that guarantees that the operating speed will not decrease even if the power supply voltage is lowered.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, a CMOS circuit and an 81-CMO circuit are connected between the input and output terminals.
A FET with multiple gate electrodes at the same potential in a Bi-CMOS logic gate formed by connecting S circuits in parallel.
The groups are arranged in a substantially straight line, and the F in the circuit is
The connection between the ET and the bipolar transistor is made using only the high melting point metal layer which is the first wiring layer, and the connection between the circuits is made with the low resistance wiring layer above the second layer, and this wiring is as described above. Made it possible to pass over high melting point metal wiring.

[Operation] According to the above-described means, the CMOs connected in parallel to each other
Of the S circuit and the Bi-CMOS circuit, the Bi-CMOS circuit charges and discharges the load capacitance at high speed, and eventually -CMO3
Since the circuit fully swings the output potential to the power supply voltage, it is possible to prevent the speed of the Bi-CMOS circuit from decreasing at low power supply voltages.

In addition, since the FET groups having multiple gate electrodes of the same potential are arranged in a straight line, the wiring between gate electrodes is reduced.
In addition, it is possible to share the low resistance wiring for the circuit power supply on the second layer with the adjacent CMOS circuit, thereby reducing the layout area, reducing the cell area of the Bi-CMOS circuit, and increasing the degree of integration. can be improved.

[Embodiment FIG. 1 shows the present invention in a three-man NAND logic type Bi-
A circuit diagram of one embodiment as applied to a CMOS logic gate is shown.

In the figure, 1 is a bipolar transistor Ql connected in series between power supply voltage Vcc and GND.

A totem-pole output stage constituted by Q2, 2 is a CMO3 logic stage for forming a signal for driving the transistors Ql and Q2 of the output stage 1. This CMO3
Logic stage 2 includes three p-channel MO3FETs P1 to P3 connected in parallel between the power supply voltage terminal VcC and the base terminal of the transistor Q1, and connected in series between the base terminal of the transistor Q1 and the voltage GND. three n's
It consists of a three-way NAND logic section consisting of channel MOSFETs Nl-N3, and four n-channel MOSFETs N4 to N7 connected in series between the output terminal OUT of the circuit and the power supply voltage terminal (GND). ,
Among the MO3FETs N4 to N7, the gate terminals of N4 to N6 are connected to the n-channel MO8FET PI-P3.
Common input signals 11 to 3 are applied.

Further, the same voltage as the voltage applied to the base terminal of the transistor Q1 (the potential of the node n1) is applied to the gate terminal of the n-channel MO3FET I'J7,
MOSFET N is connected to the base terminal of transistor Q2.
The potential of the connection node n2 between 6 and N7 is applied. As a result, the transistors Ql and Q2 of the output stage 1 are controlled to be turned on and off in a complementary manner to each other, thereby charging and discharging the load. At this time, one of the transistors Ql and Q2 is always turned off, so that through current is prevented and power consumption can be reduced. Furthermore, since the load is driven by a bipolar transistor, it operates faster than a CMOS circuit.

In addition, the above CMO8 logic stage 2 (7) MO, 5FETN4
~N7 is the power supply voltage V c c-GNDnJH, :il
They may be connected in I-series, but the high level of the output terminal ○UT is higher than the base-emitter voltage Vcc than the power supply voltage Vcc.
BE is low, so in order to prevent the saturation of the transistor Q2 and increase the speed, the output terminal OUT and the power supply voltage terminal (GN
D), MOSFETs N4 to N7 are connected in series.

In this embodiment, a three-manufactured NAND logic CMO3 logic circuit 12 is connected between the Bi-CMO3 low 0M0 input terminals 11 to 3 and the output terminal UT. That is, n-channel MOSFETs P4 to P6 are connected in parallel between the power supply voltage Vcc and the output terminal ○UT, and the gate terminal is connected to the input terminal of the n-channel MOSFET.
The same input signals 11 to 3 as Pi to P3 are applied, respectively. In addition, the output terminal OUT and the power supply voltage GND
n-channel MOSFETs N8 to N10 are connected in series between
It is configured such that input signals 11 to I3 of FETs P4 to P6 are commonly applied.

In this way, the CMO3 logic circuit 12 is connected to the Bi-CMO
By being connected in parallel with the three logic circuits 11, B
After the i-CMOS logic circuit 11 charges and discharges the load at high speed, the CMO3 logic circuit 12 fully swings the output terminal to Vcc or GND. Therefore, the driving force of the load is high and the output can fully swing, i-0M.
An O3 logic gate is obtained. As a result, the output terminal OUT
There is no risk that the on-current of the next-stage FET connected to the gate will decrease and the delay time will increase, and even if the power supply voltage of the LSI is lowered, the high speed performance of the Bi-0 MO3 logic gate can be guaranteed.

FIG. 2 shows an example of a layout system when the three-manufactured NAND type Bi-0MO8 logic gate is formed into cells.

In the same figure, the symbol PSDI indicates an n-type diffusion layer that becomes the source and drain regions of the p-channel MO3FETPs P4 to P6 that constitute the circuit of FIG.
N-type diffusion layers which become source and drain regions of channel MOSFETs P1 to P3, and N5DI, N5D2. N
5D3 are each n-channel MO3FE
T Nl-N3 and N7. N8-N10 and N4-N
This is an n-type diffusion layer that becomes the source and drain regions of No. 6.

In this embodiment, the diffusion layers PSDI, PSD2, N5
DI to N5D3 are arranged so as to be aligned in one direction (vertical direction in the figure), and three common gate electrodes GTI to GT3 made of polysilicon or the like are placed thereon with an insulating film (not shown) interposed therebetween. are arranged parallel to each other. In other words, the gate electrodes of MOSFETs to which the same input signal is applied are combined into one, and multiple MOSFETs are connected in the direction of the gate electrode.
By arranging FETs, the wiring that connects gate electrodes of the same potential is omitted.

Active regions BIPI and BIP2 of bipolar transistors Ql and Q2 constituting an output stage are formed adjacent to the diffusion layers PSD2 and N5D2. C1, Bl
, El are the collector terminal, base terminal, and emitter terminal of the bipolar transistor Ql, respectively, and C2 . B2. E2
are the collector terminal, base terminal, and emitter terminal of the bipolar transistor Q2.

However, if the MOSFET diffusion layers are stacked vertically as described above, the cell becomes longer in the height direction, so power supply wiring (Vcc line and GND line) is placed outside (top and bottom) of the cell as in the conventional method. When this happens, a wasted blank area is created in the bipolar output stage formation areas BIPI and BIP2, and in an LSr that includes a mixture of Bi-0MO8 logic gates and CMO3 logic gates, the heights of the two gate cells are different. This results in wasted space as in the case of the bipolar formation region.

Therefore, in this embodiment, the wiring for connecting between the transistors inside the cell is formed of a high melting point metal layer such as tungsten.

That is, p-channel MO3FET PI-P3 and P
Tungsten wires W1 and W are connected between each source terminal of 4 to P6.
2 and connected by a p-channel MO3FET P
Each drain terminal of i to P3 and bipolar transistor Q
A tungsten wiring W3 is connected to the base terminal Bi of the base terminal Bi. A part of this tungsten wiring W3 is extended toward the diffusion layer N5DI and connected to the drain terminal of the n-channel MO3FET Nl. The drain terminals of the p-channel Mo5FETs P4 to P6 and the emitter terminal E1 of the bipolar transistor Q1 are connected by a tungsten wiring W4, and this tungsten wiring W4 is extended downward to connect the collector terminals C2 and n of the bipolar transistor Q2. It is connected to diffusion layers N5D2 and N5D3, which are the drain regions of channel MO3FETs N4 and N8.

Furthermore, the base terminal B2 of the bipolar transistor Q2
and the diffusion layer N5D3, which is the source region of the n-channel MO3FET N6, are connected by a tungsten wiring W5.
7 and Nl0(7)/-s regions are tungsten wiring W
are connected to each other by 6.

Note that the diffusion layer N5D1 serving as the drain region of the n-channel MO3FET N7 and the base terminal 82 of the bipolar transistor Q2 are connected to the tungsten wiring W7 and the polysilicon wiring PLI via the tungsten wiring W5.

Moreover, in this example, the above MOSFETs P1 to P
A power supply line (Vcc line) Ll made of the first aluminum layer extends from above the diffusion layer PSD2 of No. 3 to above the formation region BrP1 of the bipolar transistor Q1.
Also, from above the diffusion layer N5D2 of MOSFETs N8 to NIO, the formation region BIP of the bipolar transistor Q2 is
A power supply line (GND line) L2 made of a first aluminum layer, which is also a second wiring layer, is formed above 2.

Then, Vc to the collector terminal C1 of the transistor Q1
The power supply c is performed by connecting to the power supply line L1 via the tungsten buffer layer WBi. THI is connected to its buffer layer WBI and power supply line L1
This is a contact hole for making contact with. In addition, VC to the source terminals of p-channel MO3FETs PI to P6
Power is supplied to C by bringing the power line L1 into contact with the tungsten wirings W1, W2 through contact holes TH2, TH3.

On the other hand, emitter terminal E2 of bipolar transistor Q2
Application of the ground potential to the tungsten buffer layer WB2
This is done through the .

TH4 and TH5 are contact holes for bringing the buffer layer WB2 and the power supply line L2 into contact.

Furthermore, an n-channel MO3FET N3. The ground potential is applied to the source terminals of N7 and NIO by bringing the power supply line L2 into contact with the tungsten wiring W6 through the contact hole TH6.

In addition, the symbols shown in FIG. 2 are tungsten W1 to W7 and MOSFETs P1 to P6 and N
1 to the position of a contact hole provided for contacting the source and drain regions of NIO. Also, CH
II is a contact hole that provides a well potential around the p-channel MO3FETMO3FET, and CH22 is a contact hole that provides a substrate potential.

In the layout of the above embodiment, some of the cells are outside the power lines L1 and B2 (in the upper and lower parts in FIG. 2).
It stands out. However, since the connections between elements within the cell are made with tungsten wiring, the power supply line Ll,
It is possible to form a signal line made of an aluminum layer outside L2. In other words, the area above the cell can be used as a wiring channel area for forming signal lines using automatic wiring technology, which increases the degree of integration even though the area of the cell itself increases, reducing chip size. It becomes possible to do so.

Note that input signals are supplied to the Bi-CMOS gate cell configured as described above, for example, through the gate electrode GTI.
, GT2. The end portion of GT3 may be made to protrude into the channel region CNLI, and the aluminum signal line Ql-06 may be connected to the end portion via the tungsten wiring layers Wll to W13.

In addition, the output signal is taken out using a bipolar transistor Q.
An aluminum buffer layer ALB is formed on the tungsten wiring layer W4 that connects the emitter terminal E1 of Q2 and the collector terminal C2 of Q2, and is arranged in a direction perpendicular to the power lines L1 and L2 via this buffer layer ALB. The output signal line Q is made of the second aluminum layer, which is the third wiring layer.
It is preferable to contact the tungsten wiring layer W4 with the contact holes TH7, TH8 and CH13.

As shown in FIG. 2, the cell layout method according to an embodiment of the present invention is such that gate electrodes with the same potential are grouped into one line, and a plurality of FETs are arranged in the direction of the gate electrode to connect gate electrodes with the same potential. Although this is a method to reduce the number of interconnections to be connected, all interconnections between the FET and the bipolar transistor inside the cell are made of a first layer of a high melting point metal thin film such as tungsten. Therefore, the power supply wiring (
The low-resistance wiring lines L1 and L2 made of aluminum alloy or the like, which are the second wiring layer (Vcc, GND), can freely pass over the first layer, which is a high melting point metal thin film such as tungsten. This allows CMO3 with small cell height to
Even if they are placed adjacent to the circuit, the power supply wirings Ll and L2 can be shared, eliminating wasted space.

Furthermore, the outside of the area between the power supply lines LL and L2 is normally used as a wiring channel area between cells;
According to the layout of this example, the inter-cell wiring is composed of low resistance wiring made of aluminum alloy or the like above the second layer, so the emitter polysilicon and gate electrodes constituting the FETs and bipolar transistors in the cells It is also possible to freely pass over the first layer of high melting point metal thin film such as tungsten, which is the inter-element wiring within the cell. For example, P4 to P6 and N4 to N6 in Figure 2 protrude into the cell wiring channel region, but above these are intercell low resistance wirings made of aluminum alloy, etc. from the second layer onwards. can pass freely. That is,
Since P4 to P6 and N1 to N6 do not narrow the wiring channel area, the effective cell size is the same as the conventional Bi-CMO without P4 to P6 and N8 to NIO.
Equal to 3 circuits.

As described above, according to the circuit system of one embodiment of the present invention,
Since the output voltage fully swings up to the power supply voltage, the high speed performance of the Bj-CMO3 circuit can be achieved even at a low power supply voltage. Furthermore, according to the layout method of one embodiment of the present invention, the effective cell size is the same as that of a conventional Bi-CMOS circuit even though a large number of FETs are added, so a highly integrated semiconductor integrated circuit can be realized. .

Furthermore, according to one embodiment of the present invention, the first layer of high melting point metal thin film such as tungsten is used only for connection inside the cell, so it is easy to reduce the thickness, and the second and subsequent layers are made of aluminum. Since low-resistance wiring made of alloy or the like can be formed without complicating the process, multilayering is easy.

Furthermore, since the first layer of high-melting point metal such as tungsten does not interfere with the layout of low-resistance wiring made of aluminum alloy or the like in the second and subsequent layers, the source/drain of the FET and the first layer Even if a large number of connection holes are provided between high melting point metals such as tungsten, the cell size will not increase. Therefore, by increasing the number of connection holes, it is possible to reduce the parasitic resistance of the source and drain, thereby increasing the speed of the circuit.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above example, 3
The explanation was given using the B1-CMOS logic gate that constitutes human-powered NAND logic as an example, but it is also possible to use two- or four-person NAND
The present invention can also be applied to Bi-CMOS logic gates constituting logic, NOR logic, inverters, and the like.

The present invention applies not only to standard cell type logic LSIs, but also to gate arrays and other Bi-CMO3! It can be generally used for logic LSIs having logic gates.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, a logic LS with Bi-CMOS logic gates
In I, the degree of integration can be improved without reducing the operating speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a logic gate constituting a logic integrated circuit according to the present invention, and FIG. 2 is a plan view showing an embodiment of a layout method within a cell of the logic gate. TGI~TG3...Gate electrode, PSDI, PSD
2. N5DI~N5D3...MOSFET diffusion layer, Wl-W7...High melting point metal wiring layer, Fig.

Claims (1)

[Claims] 1. CMOS circuit and Bi-C with the same logic between input and output terminals
A logic integrated circuit comprising a logic gate formed by connecting MOS circuits in parallel, characterized in that connections between elements in each logic gate are made by wiring mainly made of a high melting point metal. . 2. The logic integrated circuit according to claim 1, wherein the MOSFETs to which the same signal is input are arranged along the same direction so that their gate electrodes form a straight line. 3. The logic integrated circuit according to claim 1 or 2, wherein a power supply line is provided inside the cell region in which the logic gate is formed, and a channel region is provided outside of the power supply line.