JPH01137647A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a parasitic transistor from latching up by connecting a first ground potential wiring for supplying a lower reference potential to an output buffer to a second ground potential wiring through a Schottky barrier diode. CONSTITUTION:Bonding pads 2, 2A-2D are provided on a substrate 1 made of P-type single crystalline silicon. Power source wirings 3, 4 for supplying a potential Vcc and ground potential wirings 4, 6 for supplying a potential Vss are extended on an output buffer 7A, an input buffer 7B. The wiring 4 supplies the potential Vss to the buffer 7A, and the wiring 6 supplies the potential Vss to the wiring 6, the buffer 7B and a basic cell 8A. When a plurality of the buffers 7A are simultaneously converted from ON to OFF, a large current flows through the wiring 4 to a substrate 1 thereby to raise a substrate potential. Accordingly, the wiring 4 is connected through a Schottky barrier diode to the wiring 6, thereby escaping the current of the wiring 4 to the wiring 6. As a result, it can prevent a parasitic transistor from latching up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a MISFET, and particularly to a semiconductor integrated circuit device using a P-type substrate.

[Prior art]

1 in achieving high integration of logic LSI such as gate arrays.
It is advantageous to configure the circuit with MI S FETs.

Furthermore, in order to reduce power consumption, P-channel MI
SFET and N-channel MISFET (C-MISFE
It is better to configure the circuit with T). However, it is more advantageous to use NPN bipolar transistors in order to increase the speed of circuit operation and increase drive capability. Therefore, in recent years, circuits such as output buffers that require large driving capability are constructed with C-MISFETs and NPN bipolar transistors. And, N.P.
In order to configure an N bipolar transistor, a P-type silicon substrate is used as the substrate.

By the way, in a logic LSI, so-called parallel processing is performed in which a plurality of pieces of information are processed simultaneously. Therefore, many input/output buffers, such as 8 bits, 16 bits, or 32 bits, are turned on and off at the same time. At this time, power supply wiring that supplies high-level reference potential Vcc, for example, 5V to the input/output buffer,
The potential of the power supply wiring that supplies the low-level reference potential V s s , for example, Ov, changes. In particular, since a large current is turned on and off in the output buffer, potential fluctuations due to the operation of the output buffer are large. Therefore, the power supply wiring that supplies the potential Vcc to the output buffer (hereinafter simply referred to as the power supply wiring) and the power supply wiring that supplies the W1 position Vss (hereinafter referred to as the ground potential wiring) are used to supply the potential Vcc to other circuits. A power supply wiring for supplying power and a ground potential wiring for supplying the potential Vss are separately provided for exclusive use.

[Problem that the invention seeks to solve]

As a result of studying the logic LSI, the inventor found the following problems.

This is because the ground potential wiring is connected to the board.

If many output buffers switch from on to off at the same time,
A large current flows into the substrate, raising the substrate potential.

At this time, a parasitic NPN transistor is formed on the substrate by the N-well region for forming the P-channel MI 5FET, the P-substrate, and the N1 source and drain of the N-channel MISFET, so this parasitic There is a problem in that the transistor turns on due to the current flowing into the substrate, causing latch-up. In order to prevent this latch-up, the ground potential wire of the output buffer is connected to the ground potential wire of another circuit, and the current when the output buffer switches from on to off is connected to the ground potential wire of the other circuit. It is possible to prevent the substrate potential from rising by discharging it to the potential wiring. However, with this, when the output buffer switches from on to off, the potential of the ground potential wiring connected to circuits other than the output buffer rises, causing internal logic gates, input cover sofas, etc. to malfunction. There is a problem.

An object of the present invention is to prevent latch-up and malfunction of a circuit, thereby increasing the reliability of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a first ground potential wiring that supplies a low reference potential to the output buffer of the half-spirit integrated circuit is provided extending over the semiconductor chip, and a first ground potential wiring that is not connected to the output buffer is provided separately from the first ground potential wiring. Two ground potential wirings are provided on the semiconductor chip, the first ground potential wiring and the second ground potential wiring,
It is connected via a Schottky barrier diode.

[Effect]

According to the above-mentioned means, the Schottky barrier diode has a threshold value of 0.3 to 0.0% lower than the threshold value of the parasitic transistor.
Since it is turned on at 5V and the current flowing through the ground potential wiring of the output buffer is released to other ground potential wiring, a parasitic transistor is not turned on and latch-up occurs. Further, at this time, the rise in potential of the ground potential wiring connected to circuits other than the output buffer is suppressed to a low value of 0.3 to 0.5 V or less, so that malfunction of the circuit does not occur.

For these reasons, the reliability of the semiconductor integrated circuit device can be improved.

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment I of the invention]

FIG. 1 is a plan view of a semiconductor chip constituting a semiconductor integrated circuit device according to Example 2 of the present invention.

In FIG. 1, reference numeral 1 denotes a substrate made of P-type single crystal silicon, and a bonding pad 2.2A formed on the periphery of a second layer of aluminum film, for example.

2B, 2G, and 2D are provided. The bonding pad 2 is for inputting and outputting signals.

The bonding pad 2A is for supplying the potential Vcc, for example, 5V, to the output buffer 7A. The bonding pad 2B is for supplying a potential Vss, for example Ov, to the output buffer 7A. The bonding pad 2C applies a potential Vc to the input cover sofa 7B and the basic cell 8A.
c For example, it is for feeding 5V. The bonding pad 2D is for supplying a potential Vss, for example Ov, to the input buffer 7B and the basic cell 8A.

The output buffer 7A and the input buffer 7B are P channel M
It is composed of ISFET, N-channel MISFET, NPN bipolar transistor, etc.

Some output buffers 7A operate independently of the on/off operations of other output buffers 7A, and there are 8, 16, and 7A output buffers.
In some cases, 32 or more can be turned on and off at the same time. And output buffer 7A, input cover sofa 7
On top of B are power supply wirings 3 and 5 made of, for example, a second layer of aluminum film, which supply the potential Vcc, and the potential Vss.
Ground potential wirings 4 and 6 for feeding power extend therethrough. Wiring 3
is for supplying the potential Vcc to the output buffer 7A, and the wiring 5 is for supplying the potential Vcc to the input buffer 7B and the basic cell 8A. This arrangement m3.
s is connected to an N-type well region where a P-channel MISFET is provided.

Further, the wiring 4 is for supplying the potential Vss to the output buffer 7A, and the wiring 6 is for supplying the potential Vss to the input buffer 7B and the basic cell 8A.

The wirings 4 and 6 are connected to the substrate (P- region) 1 in the vicinity of the N-channel MI S FET. The area surrounded by the wirings 3, 4, 5.6, the output buffer 7A, and the input buffer 7B is an internal logic area, in which a large number of basic cells 8A are arranged. 8 is a basic cell row formed by arranging basic cells 8A in a row. Basic cell 8A.

For example, it consists of two P-channel MISFETs and two N-channel MI 5FETs.

When multiple output buffers 7A are switched from on to off at the same time, a large current flows into the board 1 through the wiring 4,
To increase the substrate potential, a Schottky barrier diode SBD is connected between the wiring 4 and the wiring 6 as shown in FIG.
The wiring 4 is connected to the wiring 6 so that the current in the wiring 4 is released to the wiring 6. In FIG. 2, C is the capacitance of the bonding wire connected to the output terminal of the output buffer 7A, the lead, the wiring on the wiring board, the sum of the input capacitance of another LSI connected to the output terminal of the LSI, etc. Li is the wiring 4 and the bonding wire connected thereto.

This is the inductance of the lead, and L2 is the inductance of the wiring 6, the bonding wire connected thereto, and the lead. 9 and 10 are an inverter and a two-man NAND configured in the basic cell 8A.

For example, as shown in FIG.
2 P-channel MISFETs, 2 N-channel MIS
It is composed of a FET, two bipolar transistors, and two resistance elements R. The inverter 9 is one
As shown in the figure, one P-channel MISFET and one
It is composed of N-channel MISFETs. For example, as shown in Figure 5, a two-man NAND
channel MISFET and two N-channel MISFETs
It is made up of.

When 8, 16, or 32 output buffers 7A are switched simultaneously, the charges stored in the respective load capacitors C are released, so that a large current momentarily flows through the wiring 4. At this time, a back electromotive force is generated by the inductance L, so that the potential of the wiring 4 increases. However, since the wiring 4 is connected to the wiring 6 via the Schottky barrier diode SBD, and the threshold value of the Schottky barrier diode SBD is as low as 0.3 to 0.5V,
The potential of the part of the board 1 where the wiring 4 is connected is 0.3~
Before the voltage exceeds 0.5V, the current in the wiring 4 flows to the wiring 6 through the Schottky barrier diode SBD. On the other hand, since the potential applied to the wiring 6 through the shut-key barrier diode SBD is 0.3 to 0.5V or less, the potential of the wiring 6 never becomes higher than 0.3 to 0.5V. . A value of 0°3~0.5v means that the inverter 9
Since this value is sufficiently lower than the threshold value (1/2 Vcc) of two-person NANDIO, malfunctions will not occur.

Also, in the output buffer 7A itself, the output may be reversed if the potential of the wiring 4 increases, but since the potential of the wiring 4 is kept low, malfunctions of the output buffer 7A can be eliminated.

Next, the cross-sectional structure of the Schottky barrier diode SBD will be explained.

FIG. 6 is a cross-sectional view of the Schottky barrier diode SBD and its vicinity.

First, an overview of the structures of various elements will be explained. In FIG. 6, 11 is a P'' type buried layer, 12 is an N'' type buried layer,
13 is a P-type well region, and 14 is an N-type well region. In the P-type well region 13, there is an N-channel type MISFE.
A T and an NPN bipolar transistor (not shown) are configured. In the N-type well region 14, there is a P-channel MIS.
It constitutes a FET and a Schottky barrier diode SBD. 15 is a P channel stopper region, and 20 is a field insulating film. N-channel MISFET is N1
It consists of a type source, a drain 16, a gate insulating film 21, and a gate electrode 22. This N-channel MISF is placed around the N-channel MISFET of the output buffer 7A.
A P° type semiconductor region 18 is formed so as to surround almost the entire periphery of the ET. This P' type semiconductor region 18 is for making ohmic contact between the P' type well region 13 and the aluminum wiring 25 for applying the potential Vss thereto. The P-channel MISFET has a P° source, a drain 17, a gate insulating film 21, and a gate electrode 22.
It consists of An N' type semiconductor region 19 is formed near the P channel MISFET. The N° type semiconductor region 19 is for making ohmic contact between the N° type well region 14 and the aluminum wiring 29 for supplying the potential vcc thereto. Note 1
Although not shown, P that constitutes the output buffer 7A
This P-channel MISFET is surrounded by
An N-type semiconductor region 1 surrounds almost the entire circumference of the SFET.
There are 9. 23 is a first layer interlayer insulating film;
For example, it is made of a silicon oxide film formed by low pressure CVD.

Wirings 25, 26, 27, 28, and 29 made of a first layer of aluminum film extend over the insulating film 23. The wiring 25 is connected to the source of the N-channel MISFET of the output buffer and to the P-channel where this N-channel MISFET is provided.
The potential Vss is supplied to the type well region 13.

Further, the wiring 25 connects a Schottky barrier diode SBD, which will be described later, and a second layer aluminum wiring a4 that supplies the potential Vss to the output buffer 7A.

The wiring 26 is the output terminal of the output buffer 7A, and is the second
Flth aluminum wiring 32 and N-channel MISFE
The drains of T are connected. The wiring 27 supplies the potential Vss to the source of the N-channel MISFET formed in the basic cell 8A and to the P-type well region 13 in which the N-channel MISFET is provided. Further, the wiring 27 connects the N-type well region 14 in which the Schottky barrier diode SBD is formed and the second layer aluminum wiring 6 that supplies the potential vss to the input buffer 7B and the basic cell 8A. . The wiring 28 is an output terminal of the logic circuit configured in the basic cell 8A, and is connected to the second layer aluminum wiring 33. The wiring 29 is for supplying the potential vcc to the source of the P-channel MISFET of the basic cell 8A and the N-type well region 14 in which this P-channel MISFET is provided.

It is connected to the second layer aluminum wiring 5.

30 is a second layer interlayer insulating film, for example, plasma C
A phosphosilicate glass (PSG) film is laminated on a silicon oxide film formed by vD. 24 is a connection hole formed by removing the first layer insulating film 23;
is a connection hole formed by removing the second layer insulating film.

The Schottky barrier diode SBD includes an N-type well region 14 and platinum silicide (Pt) formed on the surface of the N-type well region 14.
-5i) 50. In this non-limiting example, a Schottky barrier diode S
A BD is formed in a part of the periphery of each output buffer 7A.

On the surface of the substrate 1 where the platinum silicide 50 is deposited, there is a P+ layer surrounding the N-channel MI 5FET.
A portion of the type semiconductor region 18 is exposed.

When the potential of the wiring 4 rises to 0.3 to 0.5 V or more by switching the output buffer 7A from on to off, the Schottky barrier diode SBD becomes conductive. Then, the current from the output buffer 7A released to the wiring 1IA4 flows through the wiring 25, the Schottky barrier diode SBD,
N− type well region 14, N′ type semiconductor region 19, wiring 2
7 and flows out to wiring 6.

Ru. That is, in the substrate 1, the N-type well region 1
The electric current will flow only through 4. therefore,
-The current shown by the dotted chain line does not flow.

Until the Schottky barrier diode SBD becomes conductive, the current in the wiring 4 will flow into the substrate 1.
By the time it reaches the parasitic bipolar transistor Q, it drops to almost "0" due to the resistance of the substrate 1. Therefore, the parasitic transistor Q does not turn on, and latch-up does not occur.

The portion of the P'-type semiconductor region 18 that adheres to the platinum silicide film 50 is formed by defining that region with a mask made of a resist film. After forming the first layer insulating film 23 and forming the connection hole 22, the platinum silicide film 50 is
It is formed by forming platinum on the entire surface by sputtering and annealing it to form a silicide. For this reason,
A platinum silicide layer 50 is formed not only on the Schottky barrier diode SBD but also on the surface exposed from the connection hole 24 of the substrate 1. Further, although not shown, a platinum silicide film 50 is formed on the surface of the gate electrode 22 to which the first layer aluminum wiring is connected.

As described above, according to the present embodiment (2), when the output buffer 7 is switched from on to off, the parasitic transistor Q does not operate.

The potential of the ground potential wiring 6 connected to the input cover sofa 7B and the gate of the basic cell 8A does not rise significantly.
Since the input buffer 7B and the gate of the basic cell 8A do not malfunction, reliability can be improved.

[Embodiment of the invention■]

FIG. 7 is a plan view of the Schottky barrier diode SBD in Example 2, and FIG. 8 is a cross-sectional view taken along the line XX in FIG. 7.

Embodiment (2) is an N-channel M constituting the output buffer 7A.
The IS FET is surrounded by a Schottky barrier diode SBD for each N-channel MISFET. This creates a Schottky barrier diode S
Since the switching speed of the BD becomes faster and the current capacity becomes larger, the current flowing into the substrate 1 becomes smaller.
Therefore, the increase in substrate potential can be suppressed to a low level.

The wiring 35 shown in FIG. 7 is made of a second layer of aluminum film, and is connected to the first layer of aluminum film 36 below through the connection hole 31, and this aluminum film 36 is further connected to the first layer of aluminum film 36 through the connection hole 24. It is connected to the gate electrode 22.

[Embodiment of the invention■]

FIG. 9 is a plan view of the semiconductor chip 1 in Example 2. FIG. 10 is a diagram for explaining that the logic gate of the basic cell is not affected by the on/off operation of the output buffer.

As shown in FIG. 9, in this embodiment (2), the output buffer 7
Wiring 3 that supplies potential Vcc to A, output buffer 7
Wiring 4 that supplies potential Vss to A, input buffer 7
In addition to the wiring 5 that supplies the potential Vcc to the input buffer 7B and the basic cell 8A, and the wiring 6 that supplies the potential Vss to the input buffer 7B and the basic cell 8A, a ground potential wiring 40 that is not connected to any circuit is connected to the input/output buffer circuit. ? It extends above A and 7B. The wiring 40 is made of, for example, a second layer of aluminum film. The wiring 40 is connected to a dedicated bonding pad 2E. This bonding pad 2E is included in the package with other bonding pads 2.2
A dedicated lead not connected to A, 2B, 2C, and 2D may be provided and connected to this. And wiring 4
0 is connected to the N-type semiconductor region 19 on the surface of the N-type well region 14 where the Schottky barrier diode SRD shown in FIG. 6 or 8 is provided. therefore.

As shown in FIG. 10, the Schottky barrier diode SBD has its anode side connected to the wiring 4 and its cathode side connected to the wiring 4.
It will be connected to 0. In FIG. 3, L is the inductance of the bonding wire and lead to which the wiring 40 is connected. When the output buffer 7A is switched from on to off and the potential of the wiring 4 increases, the Schottky barrier diode SBD becomes conductive and discharges the current of the wiring 4 to the wiring 40. At this time, the wiring 6 is connected to the wirings 4 and 4.
0, the input buffer 7B and the gate of the basic cell 8A connected to the wiring 6 are not affected by the operation of the output buffer 7A. Therefore, malfunction of logic gates 9 and 10 can be completely prevented.

[Embodiment 2 of the Invention] FIG. 11 is a sectional view of the N-channel MISFET portion of the output buffer in Embodiment 2.

In Example 2, as shown in FIG. 11, a Schottky barrier diode SBD is provided.

A P° type semiconductor region 41 is provided under the P type semiconductor region 18 surrounding the N-channel MISFET of the output buffer 7A. If you do it like this.

The N-channel MISFET has a P1 type half region 18.4
1 and 11, and when the output buffer 7A is switched from on to off,
N° type source, drain 16 to P- type unit region 1
3. The current leaking into the inside will no longer flow out from this point. Therefore, latch-up will not occur. The P'' type semiconductor region 41 can be formed in the same process as the P'' type base extraction region 42 of the bipolar transistor.

Incidentally, this bipolar transistor has an N''' type buried layer 12, an N- type collector region 14, a P'' type base lead region 42. N" type collector extraction region 43.N" type semiconductor region 44. P-type intrinsic base region 45. It consists of an N'' type emitter region 46. 47 is a base electrode made of a first layer of polycrystalline silicon film, 49 is an emitter electrode made of a second layer of polycrystalline silicon film, and 48 is a base electrode 47 and an emitter region. An insulating film made of a silicon oxide film insulating between the electrodes 49, a wiring 51 made of a first layer aluminum film connected to the emitter electrode 49, and a wiring 52 connected to the N-type semiconductor region 44. This is a wiring made of the first layer of aluminum film.

The gate electrode 22 of the MISFET is formed of a second layer of polycrystalline silicon film, which is the same layer as the emitter electrode 49.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

The Schottky barrier diode turns on at 0.3 to 0.5V, which is lower than the threshold of the parasitic transistor, and releases the current flowing through the output buffer's ground potential wiring to other ground potential wiring, so the parasitic transistor turns on. latch-up will not occur.

Further, since the rise in potential of the ground potential wiring connected to circuits other than the output buffer is as low as 0.3 to 0.5 V or less, malfunction of the circuit does not occur. For these reasons, the reliability of the semiconductor integrated circuit device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the semiconductor chip, and FIG. 2 is a circuit diagram for explaining the flow of current when the output buffer is switched from on to off. 3 to 5 are circuit diagrams of the gate. FIG. 6 is a sectional view of the vicinity of the Schottky barrier diode, and FIG. 7 is a plan view of the Schottky barrier diode surrounding the -MISFET. FIG. 8 is a sectional view taken along line XX in FIG. 7. Figure 9 is a plan view of the semiconductor chip, Figure 10 is a circuit diagram for explaining the current flow when the output buffer is switched from on to off, and Figure 11 is a diagram of the Schottky barrier diode. Nearby M
FIG. 2 is a cross-sectional view of an ISFET and a bipolar transistor. In the figure, SBD... Schottky barrier diode, 3
．． 4,5,6,40...aluminum wiring, 2,2A
, 2B, 2G, 2D, 2F...ponding pad,
7A...Output buffer, 7B...Input buffer, 1
3... P- type well region, 14... N° type well region, 11... P1 type buried layer, 12... N° type buried layer. Figure 2 Figure 3 Figure 4 cc

Claims (1)

[Claims] 1. A first ground potential wiring that supplies a low reference potential to an output buffer of a semiconductor integrated circuit is provided extending over the semiconductor chip, and separately from the first ground potential wiring, a first ground potential wiring is provided to supply a low reference potential to the output buffer of the semiconductor integrated circuit. A semiconductor integrated circuit device, characterized in that an unconnected second ground potential wiring is provided extending over the semiconductor chip, and the first ground potential wiring and the second ground potential wiring are connected via a Schottky barrier diode. 2. The semiconductor integrated circuit device according to claim 1, wherein the second ground potential wiring supplies a low reference potential to circuits other than the output buffer. 3. The second ground potential wiring is not connected to any circuit in addition to the first ground potential wiring that supplies low reference potential to the output buffer and the ground potential wiring that supplies low reference potential to circuits other than the output buffer. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided so as to extend over a semiconductor chip. 4. On the semiconductor chip, there is a P-channel MISFET.
2. The semiconductor integrated circuit device according to claim 1, further comprising an N-channel MISFET, and an NPN bipolar transistor.