JPH04119693A - Manufacture of multi-wire wiring board - Google Patents
Manufacture of multi-wire wiring boardInfo
- Publication number
- JPH04119693A JPH04119693A JP24054290A JP24054290A JPH04119693A JP H04119693 A JPH04119693 A JP H04119693A JP 24054290 A JP24054290 A JP 24054290A JP 24054290 A JP24054290 A JP 24054290A JP H04119693 A JPH04119693 A JP H04119693A
- Authority
- JP
- Japan
- Prior art keywords
- laminated
- layer
- wire
- board
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 20
- 239000012790 adhesive layer Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims 1
- 239000000853 adhesive Substances 0.000 abstract description 16
- 238000007747 plating Methods 0.000 abstract description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 7
- 239000010949 copper Substances 0.000 abstract description 7
- 239000004744 fabric Substances 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 6
- 239000003822 epoxy resin Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 5
- 229920000647 polyepoxide Polymers 0.000 abstract description 5
- 239000004698 Polyethylene Substances 0.000 abstract description 3
- -1 polyethylene Polymers 0.000 abstract description 3
- 229920000573 polyethylene Polymers 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 description 12
- 239000000203 mixture Substances 0.000 description 6
- 229910000831 Steel Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 210000000689 upper leg Anatomy 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマルチワイヤ配線板参由移マ罎の製造法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a multi-wire wiring board.
マルチワイヤ配線板の製造法として、公開特許公報昭５
８−５３８８５号に示されているように、熱硬化性接着
剤層を設けた絶縁基板に、絶縁電線を回路パターンに従
い布線し、オーバレイ層を積層プレスして、絶縁電線を
熱硬化性接着剤層に埋込んだ後、絶縁電線を横切るスル
ーホールをあけ、スルーホール内壁に無電解金属めっき
を形成させて製造している。As a method for manufacturing multi-wire wiring boards, published patent publication 1973
As shown in No. 8-53885, insulated wires are laid according to the circuit pattern on an insulated substrate provided with a thermosetting adhesive layer, an overlay layer is laminated and pressed, and the insulated wires are bonded with thermosetting adhesive. After being embedded in a chemical layer, a through hole is made across the insulated wire, and electroless metal plating is formed on the inner wall of the through hole.
近年ますます高密度化している電子機器にマルチワイヤ
配線板を適用するためには、従来より高密度の配線を行
なう必要がでてきた。すなわち、従来のマルチワイヤ配
線板の配線密度が２．５４Ｗ間隔のスルーホール間に３
本程度であったが、今度はそれ以上の配線密度が必要と
されている。In order to apply multi-wire wiring boards to electronic devices that have become increasingly dense in recent years, it has become necessary to conduct wiring at a higher density than before. In other words, the wiring density of the conventional multi-wire wiring board is 3 wires between the through holes spaced at 2.54W.
However, now a higher wiring density is required.
スルーホール間隔も２．５４ｗ間隔から１．２７ｗ間隔
へと移行しつつあり、また、スルーホール径もそれに従
って小径化への傾向にある。この様な状況下で布線後、
積層工程での絶縁電線始、終点部の動きによる絶縁電線
とスルーホール間での接続不良の心配がある。Through-hole spacing is also shifting from 2.54w to 1.27w, and the through-hole diameter is also trending toward smaller diameters accordingly. After wiring under these circumstances,
There is a risk of poor connection between the insulated wire and the through hole due to movement of the beginning and end of the insulated wire during the lamination process.
本発明は７、以りの橡な欠点を解決［７、絶縁電腿始、
終点部の動きを抑えた高密度のマルチワイヤ配線板の製
造法を折伏するものである。The present invention solves the following disadvantages [7. Insulated electric thighs,
This is a breakthrough in the manufacturing method of high-density multi-wire wiring boards that suppresses movement of the end points.
（課題を解決するだめの手段）
本発明は、熱硬化性接ｔｉ削屡を設けた絶縁基払に、絶
縁電、線を回路バタ・〜ンに従い布線１２、オーバーレ
イ層を積層ブレス１．た後、絶縁電線を１１ｉ９るスル
ーボールをあ１３、スルーホール内壁に無１解金属めっ
きを形成さセるマルチワイヤ配線板σ製造法において、
熱硬化性接着副層を設けたｖＡ糾基板に絶縁電線を回路
パターンζこ従い布線した８熱硬化性接着剤ｊｌを１Ｉ
ｊＩＩする。ｔなわぢ、布線層を熱硬化性接着側層で挟
む、−とを特徴とするもσである。(Another Means to Solve the Problems) The present invention provides a laminated brace 1, in which an insulated wire is laid out according to a circuit pattern, and an overlay layer is formed on an insulating base provided with a thermosetting adhesive layer. After that, in the multi-wire wiring board σ manufacturing method, a through ball is formed by attaching an insulated wire 11i9, and a no-solution metal plating is formed on the inner wall of the through hole.
Insulated wires were wired according to the circuit pattern ζ on the vA paste board provided with the thermosetting adhesive sublayer.
jII. t cable, the wiring layer is sandwiched between thermosetting adhesive side layers, and -.
熱硬化性接着副層を１けた絶縁基板に絶絹電Ｖを回路パ
ターンら二従い布線しまた後、熱硬化性接１削層を積層
して、布線ｌｉｔ各熱硬化性接＠割層で朽むことにより
１、布線後、メーバーレイプレス時σ加圧および「・ジ
ン７ｌ」・−による絶縁電線始６終？部の動きが抑えら
れ、絶縁電線とスルーホール間での接続不良を防止でき
る。After wiring Zetsukuden V according to the circuit pattern on an insulating substrate with a thermosetting adhesive sub-layer, a thermosetting adhesive sub-layer is laminated, and each thermosetting adhesive sub-layer is wired. 1. After wiring, insulated wire by σ pressurization and "・Jin 7L"・- after wiring? movement of the parts is suppressed, and poor connection between the insulated wire and the through hole can be prevented.
（実施例１）
１）ガラス布エポキシ樹脂銅張積層板Ｍ ＣＬ −Ｅ１
６８（日立化成工業株式会社、商品名）をエツチングで
内層回路を形成し、絶縁層を積層ブレスして絶縁基板を
作成する８
２）接￥Ｉ割ｃＥ＾−０５Ｎ（日立化成工業株式会社、
商品名）を１）の絶縁基板に１７０℃、２０ｋｇ／−で
ＩＯ分間積層プレスするい
３）ＮＣ布線機によ、て、絶縁１ｉ線を２）の構成物上
に布線する。(Example 1) 1) Glass cloth epoxy resin copper-clad laminate M CL-E1
68 (Hitachi Chemical Co., Ltd., trade name) is etched to form an inner layer circuit, and an insulating layer is laminated and pressed to create an insulating substrate.
(trade name) on the insulating substrate of 1) for IO minutes at 170° C. and 20 kg/-. 3) Using an NC wiring machine, the insulated 1i wire is wired on the structure of 2).
４〉接着ＭＧＥＡ−０５ＮＡＳ−１５０（日立化成工巣
株式会社、商品名）を３）の構成物に重ね、１７０”Ｃ
，２２ｋｇ／ｃｄで５分間積層プレスする。4> Layer adhesive MGEA-05NAS-150 (Hitachi Chemical Kosu Co., Ltd., trade name) on the composition of 3), and
, 22 kg/cd for 5 minutes.
５）ガラス布エポキシ樹脂のプリプレグＧＥＡ−１６８
Ｎ（日立化成工業株式会社、商品名）を４）の構成物に
重ね、１６５℃、２２ｋｇ／ｆｆｌで４０分間積層プレ
スする。5) Glass cloth epoxy resin prepreg GEA-168
N (manufactured by Hitachi Chemical Co., Ltd., trade name) was layered on the component 4) and laminated and pressed at 165° C. and 22 kg/ffl for 40 minutes.
Ｇ）めっきマスクとして、粘着剤付ポリエチレンフィル
ムのヒタレックスＳ−５００Ｘ−９（日立化成工業株式
会社、商品名）を５）の構成物にラミネー１へし、スル
ーホールとなるべきところに六をあけした後、厚（ｊ用
無電解鋼めっき液に浸漬して、穴内壁に約４０ｍの銅層
を形成する。G) As a plating mask, apply adhesive-coated polyethylene film Hitalex S-500X-9 (Hitachi Chemical Co., Ltd., trade name) to the composition of 5) on laminate 1, and make holes 6 where the through holes should be. After that, the copper layer is immersed in a thick electroless steel plating solution to form a copper layer of about 40 m on the inner wall of the hole.
７）めっきマスクを剥Ｍ１−５て、マルチワイヤ配祈板
を得る。7) Peel off the plating mask M1-5 to obtain a multi-wire distribution board.
（実施例２）
】）ガラス布エポキシ銅張積層板ＭＣＬ−Ｅ１６８ （
Ｂ立化成工業株式会社、商品名）をエツチングで内層回
路を形成し、絶縁層（特許願６３−２９５７３３）積層
ブレスＬ２１、絶縁基板を作成する２）１着剤（特許１
１６２−３１８３８４＞を１）で得た絶縁基板＆：１２
Ｏ℃、４眩／−、ロール達度０６４ｍ／分でロールラミ
＄−１・する。(Example 2) ])Glass cloth epoxy copper clad laminate MCL-E168 (
Form an inner layer circuit by etching B Rikkasei Kogyo Co., Ltd. (trade name) to create an insulating layer (patent application 63-295733), laminated press L21, and an insulating substrate. 2) 1 adhesive (patent 1)
162-318384> obtained in 1) &:12
0°C, 4 dazzle/-, roll reach 064 m/min, roll lamination $-1.
３）ＮＣ布線−によって、絶縁電線を２）で得た構成物
上に布線する。3) Wire an insulated wire on the structure obtained in 2) by NC wiring.
４）接着剤（特許１ｉ１６２−３１８３８４）を３）の
構成物に重ね１００’Ｃ，６ｋｉｒ／１ｆｆｌ、 ロー
ル速度０．３ｒｎ／分でロールラミネートする、５）４
）の構成物を１２０℃の雰囲気中で３０分間予備加熱を
行う。4) Apply adhesive (patent 1i162-318384) to the composition of 3) and roll laminate at 100'C, 6kir/1ffl, roll speed 0.3rn/min, 5)4
) is preheated in an atmosphere at 120° C. for 30 minutes.
６）５）の構成物を１２０℃、１８ｋｇ／ｃｉで３０分
間積層プレスを行う。6) The composition of 5) is laminated and pressed at 120° C. and 18 kg/ci for 30 minutes.
７）６）の構成物を１６０℃の雰囲気中で１時間加熱を
行う。7) The composition of 6) is heated in an atmosphere at 160° C. for 1 hour.
８）ガラス布エポキシ樹脂のプリプレグＧＥＡ１６８Ｎ
（日立化成工業株式会社、商品名）を７）の構成物に重
ね１７５℃、２２ｋｇ／−で２５分間積層プレスする。8) Glass cloth epoxy resin prepreg GEA168N
(Hitachi Chemical Co., Ltd., trade name) was stacked on the composition of 7) and laminated and pressed at 175°C and 22 kg/- for 25 minutes.
９）めっきマスクとして、粘着剤付ポリエチレンフィル
ムのヒタレックスｌ−５００Ｘ−９（日立化成工業株式
会社 商品名）を８）の構成物にラミネートし、スルー
ホールとなるべきところに穴あけした後、厚付用無電解
鋼めっき液に浸漬して、穴内壁に約４０μの銅層を形成
する。9) As a plating mask, laminate the adhesive-coated polyethylene film Hitalex 1-500X-9 (trade name, Hitachi Chemical Co., Ltd.) to the component in 8), drill holes where the through holes should be, and then A copper layer of about 40 μm is formed on the inner wall of the hole by immersing it in an electroless steel plating solution.
１０）めっきマスクを剥離して、マルチワイヤ配線板を
得る。10) Peel off the plating mask to obtain a multi-wire wiring board.
この様にして製造したマルチワイヤ配線板の絶縁電線始
、終点部の動きによる絶縁電線とスルーホール間での接
続不良はなかった。In the multi-wire wiring board manufactured in this way, there was no connection failure between the insulated wires and the through holes due to movement of the insulated wire start and end points.
以上説明したように、マルチワイヤ配線板で熱硬化性接
着剤層を設けた絶縁基板に、絶縁電線を回路パターンに
従い布線した後、熱硬化性接着剤層を積層して、布線層
を熱硬化性接着剤層で挟むことによって、従来の電気的
性能を維持もしくはそれ以上の性能を存した上で、絶縁
電線、スルホール間の接続信輔性にも優れたマルチワイ
ヤ配線板の製造法を提供することができる。As explained above, after insulated wires are wired according to the circuit pattern on an insulated substrate provided with a thermosetting adhesive layer using a multi-wire wiring board, a thermosetting adhesive layer is laminated to form a wiring layer. We developed a method for manufacturing multi-wire wiring boards that maintains or exceeds conventional electrical performance by sandwiching them between thermosetting adhesive layers, and also has excellent connection reliability between insulated wires and through-holes. can be provided.
茫１１６
第１図は本考瘉の一実施例を示すマルチワイヤ配線板の
断面図、第２図は従来のマルチワイヤ配線板の断面図。
１ 絶縁基板 ２ 熱硬化性接着剤３ オーバ
ーレイ ４ 絶縁ｆｉｔ線５ スルーホール
６ 絶縁層116 FIG. 1 is a sectional view of a multi-wire wiring board showing an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional multi-wire wiring board. 1 Insulated substrate 2 Thermosetting adhesive 3 Overlay 4 Insulated fit wire 5 Through hole
6 Insulating layer
Claims (1)
回路パターンに従い布線し、オーバーレイ層を積層プレ
スした後、絶縁電線を横切るスルーホールをあけ、スル
ーホール内壁に無電解金属を形成させるマルチワイヤ配
線板において、熱硬化性接着剤層を設けた絶縁基板に、
絶縁電線を回路パターンに従い布線した後、熱硬化性接
着剤層を積層して、布線層を熱硬化性接着剤層で挟むこ
とを特徴とするマルチワイヤ配線板の 製造法。1. Insulated wires are wired according to the circuit pattern on an insulated substrate provided with a thermosetting adhesive layer, and after the overlay layer is laminated and pressed, a through hole is made across the insulated wire, and electroless metal is formed on the inner wall of the through hole. In multi-wire wiring boards, an insulating substrate with a thermosetting adhesive layer is
A method for producing a multi-wire wiring board, which comprises: wiring insulated wires according to a circuit pattern, then laminating a thermosetting adhesive layer, and sandwiching the wiring layer between the thermosetting adhesive layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24054290A JPH04119693A (en) | 1990-09-11 | 1990-09-11 | Manufacture of multi-wire wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24054290A JPH04119693A (en) | 1990-09-11 | 1990-09-11 | Manufacture of multi-wire wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04119693A true JPH04119693A (en) | 1992-04-21 |
Family
ID=17061084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24054290A Pending JPH04119693A (en) | 1990-09-11 | 1990-09-11 | Manufacture of multi-wire wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04119693A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588392A (en) * | 1978-12-27 | 1980-07-04 | Hitachi Chemical Co Ltd | Method of fabricating high packing density circuit board using wire as necessary wiring pattern |
| JPS5853885A (en) * | 1981-09-25 | 1983-03-30 | 日立化成工業株式会社 | Method of producing multiwire circuit board |
-
1990
- 1990-09-11 JP JP24054290A patent/JPH04119693A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5588392A (en) * | 1978-12-27 | 1980-07-04 | Hitachi Chemical Co Ltd | Method of fabricating high packing density circuit board using wire as necessary wiring pattern |
| JPS5853885A (en) * | 1981-09-25 | 1983-03-30 | 日立化成工業株式会社 | Method of producing multiwire circuit board |
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