JP4292638B2 - Wiring board manufacturing method - Google Patents
Wiring board manufacturing method Download PDFInfo
- Publication number
- JP4292638B2 JP4292638B2 JP23484999A JP23484999A JP4292638B2 JP 4292638 B2 JP4292638 B2 JP 4292638B2 JP 23484999 A JP23484999 A JP 23484999A JP 23484999 A JP23484999 A JP 23484999A JP 4292638 B2 JP4292638 B2 JP 4292638B2
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- JP
- Japan
- Prior art keywords
- via hole
- resin
- wiring board
- manufacturing
- organic solvent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【０００１】
【発明の属する技術分野】
本発明は、配線板の製造方法に関するものである。
【０００２】
【従来の技術】
各種電子機器の小型化に伴って、高密度実装技術の要求が強くなり、半導体チップを配線板に直接実装したチップオンボードや複数の半導体チップを搭載したマルチチップパッケージ用配線板が提案されている。また、多くの入出力端子数を有する半導体パッケージに使用される配線板が提案されている。これらの配線板はいずれも高密度配線が必要なため、異なる導体層上の導体の接続には、スルーホールだけでなく非貫通ビアホールを用いている。
このような配線板は、多層化するために、回路を形成した基板の上に絶縁層を形成し、その表面に回路を形成して、ビアホールによる接続を行い、ビアホールに樹脂を埋め、これを繰り返して多層化している。ビアホールを樹脂で埋めるのは、その上に絶縁層を形成しさらに導体を形成するのに、表面にそのビアーホールの凹凸の影響がでないようにするためである。
【０００３】
【発明が解決しようとする課題】
ところで、このような従来の配線板を製造するときに、非貫通のビアホールに熱硬化性樹脂や光硬化型樹脂を穴埋め印刷すると、非貫通ビアホールのアスペクト比が大きかったり穴埋め樹脂の粘度が高かったりして、ビアホール内に樹脂が十分に充填されていなかった。このために、電子部品を搭載してはんだリフローを行う時に、樹脂が充填されていない箇所に、クラックやふくれなどの不具合が発生していた。
【０００４】
本発明は、信頼性に優れた配線板の製造方法を提供することを目的とする。
【０００５】
【課題を解決するための手段】
本発明の配線板の製造方法は、回路を形成した基板の上に、絶縁樹脂層を形成し、その表面に回路を形成して、ビアホールによる接続を行う工程を繰り返して多層化する配線板の製造方法において、ビアホール内に絶縁樹脂層と相溶性のある有機溶剤をビアホール上面まで充填した後に、絶縁樹脂層を形成することを特徴とする。また、上記において、絶縁樹脂層を形成した後、絶縁樹脂が硬化する前に、放置及び真空脱泡を行なうことを特徴とする。
【０００６】
本発明者らは、鋭意検討の結果、樹脂と相溶性のある有機溶剤でビアホール内を濡らしておき、その上から樹脂を塗布すれば、樹脂が有機溶剤に溶解して多少薄まりはするものの、ビアホール内を樹脂で完全に充填することができるという知見を得て、本発明をなすことができた。
【０００７】
【発明の実施の形態】
基板の絶縁基材には、ポリイミド樹脂やエポキシ樹脂などのプラスチックフィルムやガラス布、ガラス不織布にポリイミドやエポキシ、ポリエステル樹脂を含浸・硬化したものが使用できる。
【０００８】
ビアホールは、エキシマレーザー、炭酸ガスレーザーを照射した後、電気銅メッキや無電解銅メッキによって穴内壁を金属化して形成することができる。また、絶縁基材にポリイミドフィルムを用いた場合、アルカリ性のヒドラジン／トリエタノールアミン水溶液に浸漬することによって、穴明けすることもできる。
【０００９】
ビアホールに充填する有機溶剤には、充填する樹脂に相溶すれば特に制限するものではなく、トルエン、キシレン、メチルエチルケトン、酢酸セルソルブ、ジメチルアセトアミドなどが使用できる。
この有機溶剤をビアホールに充填する方法は、ビアホールの箇所だけ溶剤がとおるように塗膜を形成したスクリーン印刷版の上から溶剤を流したり、ディスペンサなどを用いてディップする等のいずれの方法でも構わないが、ビアホール上面まで充填することが望ましい。
【００１０】
また、樹脂には、熱硬化性樹脂として、エポキシ樹脂、ポリイミド樹脂を主成分とするものや、光硬化型樹脂として、エポキシ系ソルダレジストインクなどが使用可能である。
この樹脂を塗布してビアホール内に有機溶剤と相溶した樹脂で埋まった後に、有機溶剤がビアホール内に残留していると、ビアホール内のボイド、穴埋め不足になる可能性があるので、硬化前に真空脱泡することが望ましい。
【００１１】
【実施例】
実施例
図１（ａ）に示すように、１２μｍの銅箔２をガラス布にエポキシ樹脂を含浸させた基材３の両面に貼り合わせた厚さ０．１ｍｍの銅張り積層板であるＭＣＬ−Ｅ−６７９（日立化成工業株式会社製、商品名）のビアホールとなる箇所の銅箔をエッチング除去して直径０．１ｍｍの開口部１を形成した後、その開口部１にレーザーを照射して直径０．１ｍｍのビアホール５を形成した。
次に、図２（ｂ）に示すように、ビアホール５内部と銅箔２の全面に、厚さ１０μｍの無電解めっき銅４を形成した後、図１（ｃ）に示すように、不要な箇所の銅をエッチング除去して、配線パターン６を形成した。
次に、図１（ｄ）に示すように、無電解めっきしたビアホール５内に、有機溶剤７としてソルダーレジスト用の希釈剤であるレジューサーＪ（太陽インキ製造株式会社、商品名）を穴上部までディスペンサーで充填した。
次に、図１（ｅ）に示すように、樹脂８として光感光性のソルダーレジストであるＰＳＲ−４０００（太陽インキ製造株式会社製、商品名）を全面にスクリーン印刷法で塗布し、ソルダーレジストが有機溶剤に相溶するに十分な時間として２０分間放置した後、有機溶剤を蒸散させるために、真空脱泡し、加熱乾燥し、半硬化の状態にした後に、フォトマスクを重ねて紫外線を照射し、現像し、加熱硬化してソルダーレジストを形成した配線板を作製した。
この配線板のビアホール５内の樹脂８のボイドは０％であった。また、チップ接着用ペーストを塗布し、チップを接着した後、２６０℃、１分間のリフローテストを行っても、ふくれは発生しなかった。
【００１２】
比較例
ソルダーレジストをスクリーン印刷する前に、有機溶剤７をビアホール５に充填しなかったこと以外は実施例と同様にして配線板を作製した。
その結果、ビアホール５内の樹脂８のボイドは１２％であった。また、チップ接着用ペーストを塗布しチップを接着した後、２６０℃、１分間のリフローテストを行った結果、ふくれの発生率は２８％であった。
【００１３】
【発明の効果】
以上に説明したとおり、本発明によって、信頼性に優れた配線板の製造方法を提供することができる。
【図面の簡単な説明】
【図１】（ａ）〜（ｅ）は、それぞれ本発明の位置実施例を説明するための各工程における断面図である。
【符号の説明】
１．開口部 ２．銅箔
３．基材 ４．無電解めっき銅
５．ビアホール ６．配線パターン
７．有機溶剤 ８．樹脂[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board.
[0002]
[Prior art]
With the miniaturization of various electronic devices, the demand for high-density mounting technology has increased, and a chip-on-board in which a semiconductor chip is directly mounted on a wiring board and a multi-chip package wiring board in which a plurality of semiconductor chips are mounted have been proposed. Yes. In addition, a wiring board used for a semiconductor package having a large number of input / output terminals has been proposed. Since all of these wiring boards require high-density wiring, not only through holes but also non-through via holes are used to connect conductors on different conductor layers.
In order to increase the number of layers in such a wiring board, an insulating layer is formed on a substrate on which a circuit is formed, a circuit is formed on the surface, a connection is made with a via hole, a resin is filled in the via hole, Repeatedly multi-layered. The reason for filling the via hole with the resin is to prevent the surface from being affected by the unevenness of the via hole when the insulating layer is formed thereon and the conductor is further formed.
[0003]
[Problems to be solved by the invention]
By the way, when manufacturing such a conventional wiring board, if a thermosetting resin or a photocurable resin is filled in a non-through via hole, the aspect ratio of the non-through via hole is large or the viscosity of the filling resin is high. Thus, the via hole was not sufficiently filled with the resin. For this reason, when electronic components are mounted and solder reflow is performed, defects such as cracks and blisters occur in places where the resin is not filled.
[0004]
An object of this invention is to provide the manufacturing method of the wiring board excellent in reliability.
[0005]
[Means for Solving the Problems]
The method of manufacturing a wiring board according to the present invention includes a wiring board that is formed into a multilayer by repeatedly forming an insulating resin layer on a substrate on which a circuit is formed, forming a circuit on the surface, and performing connection using via holes. In the manufacturing method, an insulating resin layer is formed after filling the via hole with an organic solvent compatible with the insulating resin layer up to the upper surface of the via hole . In the above, after the insulating resin layer is formed, the insulating resin is allowed to stand and vacuum deaerated before being cured.
[0006]
As a result of intensive studies, the inventors have wetted the inside of the via hole with an organic solvent compatible with the resin, and if the resin is applied from above, the resin dissolves in the organic solvent and thins somewhat, Obtaining the knowledge that the via hole can be completely filled with resin, the present invention has been achieved.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
As the insulating base material of the substrate, a plastic film such as polyimide resin or epoxy resin, a glass cloth, or a glass nonwoven fabric impregnated and cured with polyimide, epoxy, or polyester resin can be used.
[0008]
The via hole can be formed by irradiating an excimer laser or a carbon dioxide gas laser and then metallizing the inner wall of the hole by electrolytic copper plating or electroless copper plating. Moreover, when a polyimide film is used for the insulating substrate, holes can be formed by immersing in an alkaline hydrazine / triethanolamine aqueous solution.
[0009]
The organic solvent to be filled in the via hole is not particularly limited as long as it is compatible with the resin to be filled, and toluene, xylene, methyl ethyl ketone, cellosolve acetate, dimethylacetamide and the like can be used.
The method of filling the via hole with the organic solvent may be any method such as pouring the solvent over the screen printing plate on which the coating film is formed so that the solvent only passes through the via hole, or dipping using a dispenser. Although there is no, it is desirable to fill up to the upper surface of the via hole.
[0010]
In addition, as the resin, it is possible to use an epoxy resin or a polyimide resin as a main component as a thermosetting resin, or an epoxy solder resist ink as a photocurable resin.
After this resin is applied and filled in the via hole with a resin that is compatible with the organic solvent, if the organic solvent remains in the via hole, voids in the via hole and filling of the hole may be insufficient. It is desirable to perform vacuum degassing.
[0011]
【Example】
EXAMPLE As shown in FIG. 1 (a), MCL-, which is a copper clad laminate having a thickness of 0.1 mm, in which a 12 μm copper foil 2 is bonded to both surfaces of a base material 3 in which a glass cloth is impregnated with an epoxy resin. Etching and removing the copper foil at the location to be a via hole of E-679 (trade name, manufactured by Hitachi Chemical Co., Ltd.) to form an opening 1 having a diameter of 0.1 mm, and then irradiating the opening 1 with a laser A via hole 5 having a diameter of 0.1 mm was formed.
Next, as shown in FIG. 2B, after the electroless plated copper 4 having a thickness of 10 μm is formed on the inside of the via hole 5 and the entire surface of the copper foil 2, it is unnecessary as shown in FIG. The copper pattern was removed by etching to form a wiring pattern 6.
Next, as shown in FIG. 1 (d), reducer J (Taiyo Ink Manufacturing Co., Ltd., trade name), which is a diluent for the solder resist, is used as the organic solvent 7 in the electrolessly plated via hole 5. Filled with a dispenser.
Next, as shown in FIG. 1 (e), PSR-4000 (trade name, manufactured by Taiyo Ink Manufacturing Co., Ltd.), which is a photosensitive solder resist, is applied as resin 8 to the entire surface by screen printing. In order to evaporate the organic solvent, it was left for 20 minutes as a sufficient time for the solution to be compatible with the organic solvent. Irradiated, developed, and heat cured to produce a wiring board on which a solder resist was formed.
The void of the resin 8 in the via hole 5 of this wiring board was 0%. Moreover, even if a reflow test was performed at 260 ° C. for 1 minute after applying the chip bonding paste and bonding the chips, no blistering occurred.
[0012]
Comparative Example A wiring board was prepared in the same manner as in Example except that the organic solvent 7 was not filled in the via hole 5 before screen printing the solder resist.
As a result, the void of the resin 8 in the via hole 5 was 12%. Further, after applying the chip bonding paste and bonding the chips, a reflow test was performed at 260 ° C. for 1 minute. As a result, the occurrence rate of blistering was 28%.
[0013]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a method for manufacturing a wiring board having excellent reliability.
[Brief description of the drawings]
FIGS. 1A to 1E are cross-sectional views in respective steps for explaining a position example of the present invention.
[Explanation of symbols]
1. Opening part 2. Copper foil Base material 4. 4. Electroless plated copper Via hole 6. Wiring pattern7. Organic solvent 8. resin
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23484999A JP4292638B2 (en) | 1999-08-23 | 1999-08-23 | Wiring board manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23484999A JP4292638B2 (en) | 1999-08-23 | 1999-08-23 | Wiring board manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001060769A JP2001060769A (en) | 2001-03-06 |
| JP4292638B2 true JP4292638B2 (en) | 2009-07-08 |
Family
ID=16977330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23484999A Expired - Fee Related JP4292638B2 (en) | 1999-08-23 | 1999-08-23 | Wiring board manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4292638B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2005078947A1 (en) * | 2004-02-13 | 2007-10-18 | 日本電気株式会社 | Digital radio equipment |
| KR100916647B1 (en) | 2007-11-26 | 2009-09-08 | 삼성전기주식회사 | Manufacturing method of PCB |
| KR100916649B1 (en) | 2007-11-26 | 2009-09-08 | 삼성전기주식회사 | Manufacturing method of PCB |
| KR100916646B1 (en) | 2007-11-26 | 2009-09-08 | 삼성전기주식회사 | Manufacturing method of PCB |
| JP2010278294A (en) * | 2009-05-29 | 2010-12-09 | Fujikura Ltd | Flexible printed circuit board and method of manufacturing the same |
| KR101097628B1 (en) * | 2010-06-21 | 2011-12-22 | 삼성전기주식회사 | Printed circuit substrate and method of manufacturing the same |
| KR101075630B1 (en) * | 2010-08-26 | 2011-10-21 | 삼성전기주식회사 | Resist coating apparatus for preparation of printed circuit board |
| KR101119306B1 (en) | 2010-11-04 | 2012-03-16 | 삼성전기주식회사 | Method of manufacturing a circuit board |
| CN110392491B (en) * | 2019-07-26 | 2021-06-04 | 生益电子股份有限公司 | PCB solder mask manufacturing method for preventing residual ink in blind hole |
-
1999
- 1999-08-23 JP JP23484999A patent/JP4292638B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001060769A (en) | 2001-03-06 |
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