JPH04118954A - Multi-pin semiconductor package - Google Patents

Multi-pin semiconductor package

Info

Publication number
JPH04118954A
JPH04118954A JP23924190A JP23924190A JPH04118954A JP H04118954 A JPH04118954 A JP H04118954A JP 23924190 A JP23924190 A JP 23924190A JP 23924190 A JP23924190 A JP 23924190A JP H04118954 A JPH04118954 A JP H04118954A
Authority
JP
Japan
Prior art keywords
semiconductor package
leads
main body
package
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23924190A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sato
博之 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23924190A priority Critical patent/JPH04118954A/en
Publication of JPH04118954A publication Critical patent/JPH04118954A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Abstract

PURPOSE:To realize a semiconductor package which can be provided with numerous leads without enlarging its main body and is easily mountable by providing terminals for signal input-output and power supply on the upper surface of the main body and also providing terminals for signal input-output and power supply on the lower surface of the main body. CONSTITUTION:Leads 2 and 3 are respectively provided on the upper and lower surfaces of the main body 1 of this semiconductor package. The leads are connected to the wiring pattern 5 of a mounting board of the package through auxiliary leads 4 passed through holes bored through the board 6. The auxiliary leads 4 also support the semiconductor package 1. Therefore, numerous leads can be provided without unnecessarily increasing the size of the package 1 and without reducing the interval between each lead. In addition, mounting of the package becomes easier and the occurrence of troubles, such as short circuit, etc., between adjacent leads can be prevented, since it is not necessary to reduce the interval between each lead.

Description

【発明の詳細な説明】 〔産業上の利用分野１ 本発明は、半導体パッケージの多ピン化に関する。[Detailed description of the invention] [Industrial application field 1 The present invention relates to increasing the number of pins in a semiconductor package.

〔従来の技術〕[Conventional technology]

従来の半導体パッケージは、第４図に示す様に、ある単
一平面上に信号の入出力及び電源用の端子（以後、リー
ドと呼ぶ）が配置されていた。In a conventional semiconductor package, as shown in FIG. 4, signal input/output and power supply terminals (hereinafter referred to as leads) are arranged on a single plane.

［発明が解決しようとする課題１ しかし、近年半導体装置で構成する回路は大規模化し、
それに伴って必要となる半導体パッケージのリードの数
も増えている。また、回路規模は小さいが多くのリード
が必要とされる場合も増えている。[Problem to be solved by the invention 1 However, in recent years, circuits made of semiconductor devices have become larger in scale,
Along with this, the number of leads required for semiconductor packages is also increasing. Furthermore, there are also increasing cases where a large number of leads are required although the circuit scale is small.

ところが、従来の半導体パッケージは、そのリードがあ
る単一平面上に配置されている為、多くのリードを設け
る為には、半導体パッケージを大きくしたり、リードの
間隔を狭くするしかなかった。However, in a conventional semiconductor package, the leads are arranged on a single plane, so the only way to provide a large number of leads is to make the semiconductor package larger or narrow the spacing between the leads.

しかし、半導体パッケージを大きくすると、それだけの
面積を実装基盤上に確保しなければならない。よって実
装基盤が大きくなり、ひいてはそれを使用する装置自体
が大きくなってしまう。また、リードの間隔を狭くする
と、半田付等の実装が難しくなってくる。However, if the semiconductor package is made larger, a corresponding area must be secured on the mounting board. Therefore, the mounting base becomes large, and the device itself that uses it becomes large. Furthermore, if the spacing between the leads is narrowed, mounting by soldering etc. becomes difficult.

そこで、このような問題を解決する方法として本発明の
目的とするところは、半導体パッケージにおいて、半導
体パッケージ本体の上面に信号の入出力及び電源用の端
子を設け、さらに下面にも信号の入出力及び電源用の端
子を設ける事で、半導体パッケージの本体を大きくする
事なく多くのリードを設け、かつ実装の容易な半導体パ
ッケージを実現するところにある。Therefore, an object of the present invention as a method for solving such problems is to provide a semiconductor package with signal input/output and power supply terminals on the top surface of the semiconductor package body, and to provide signal input/output terminals on the bottom surface as well. By providing power supply terminals, it is possible to provide a large number of leads without increasing the size of the semiconductor package body, and to realize a semiconductor package that is easy to mount.

［課題を解決するための手段］ 本発明の多ピン半導体パッケージは、 （ａ）半導体パッケージにおいて、 （ｂ）半導体パッケージ本体の上面に信号の入出力及び
電源用の端子を設け、 （Ｃ）上記半導体パッケージの下面にも信号の入出力及
び電源用の端子を設けることを特徴とする。[Means for Solving the Problems] The multi-pin semiconductor package of the present invention includes (a) a semiconductor package, (b) terminals for signal input/output and power supply provided on the top surface of the semiconductor package body, and (C) the above-mentioned A feature is that terminals for signal input/output and power supply are also provided on the bottom surface of the semiconductor package.

［実　施　例］ 第１図に本発明による多ピン半導体パッケージの実施例
を示す。[Embodiment] FIG. 1 shows an embodiment of a multi-pin semiconductor package according to the present invention.

図中１は半導体パッケージ本体である。２は半導体パッ
ケージ上面に設けたリードである。３′は半導体パッケ
ージ下面に設けたリードである。第２図は本発明による
半導体パッケージを実装基盤に取付けた実装例である。In the figure, 1 is the semiconductor package body. 2 is a lead provided on the top surface of the semiconductor package. 3' is a lead provided on the bottom surface of the semiconductor package. FIG. 2 is a mounting example in which a semiconductor package according to the present invention is attached to a mounting board.

また、第３図は実装例の断面図である。図中４は実装用
の補助リードである。５は実装基盤上の配線パターン、
６は実装基盤である。Moreover, FIG. 3 is a sectional view of an example of implementation. 4 in the figure is an auxiliary lead for mounting. 5 is the wiring pattern on the mounting board,
6 is the implementation base.

この実装例では、実装基盤に穴をあけ、半導体パッケー
ジのリードと実装基盤の配線パターンとは、補助リード
で接続する。また、この補助リードは、半導体パッケー
ジをもささえている。In this mounting example, a hole is made in the mounting board, and the leads of the semiconductor package and the wiring pattern of the mounting board are connected by auxiliary leads. This auxiliary lead also supports the semiconductor package.

この様な構造を採る事により、半導体パッケージの大き
さを必要以上に大きくする事なく、またリードの間隔を
狭くせずに、多くのリードを設ける事が可能となる。ま
た、リードの間隔を狭くする必要がない為、実装が容易
になり、隣接するリード間の半田による短絡等の不良も
起こしにくくなる。By adopting such a structure, it is possible to provide a large number of leads without increasing the size of the semiconductor package more than necessary or reducing the spacing between the leads. Furthermore, since there is no need to narrow the spacing between the leads, mounting becomes easier and defects such as short circuits due to solder between adjacent leads are less likely to occur.

よって、半導体パッケージの上面及び下面にリードを設
ける事により、半導体パッケージの本体を大きくする事
なく、多くのリードを設け、かつ実装の容易な半導体パ
ッケージを実現する事が可能となる。Therefore, by providing leads on the top and bottom surfaces of the semiconductor package, it is possible to provide a semiconductor package that has many leads and is easy to mount without increasing the size of the semiconductor package body.

［発明の効果］ 以上に記したように、本発明によって多くのリードを設
け、かつ実装の容易な半導体パッケージを実現する事が
可能となる。[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor package that has many leads and is easy to mount.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明による多ピン半導体パッケージの構成図
。 第２図は本発明による多ピン半導体パッケージの実装例
を示す図。 第３図は本発明による多ピン半導体パッケージの実装例
の断面図。 第４図は従来の半導体パッケージ図。 半導体パッケージ本体。 半導体パッケージ上面に設けたリード。 半導体パッケージ下面に設けたリード。 実装用の補助リードである。 実装基盤上の配線パターン。 ・実装基盤 ・従来の半導体パッケージのリード。 以 上FIG. 1 is a configuration diagram of a multi-pin semiconductor package according to the present invention. FIG. 2 is a diagram showing an example of mounting a multi-pin semiconductor package according to the present invention. FIG. 3 is a sectional view of a mounting example of a multi-pin semiconductor package according to the present invention. Figure 4 is a diagram of a conventional semiconductor package. Semiconductor package body. A lead provided on the top surface of a semiconductor package. A lead provided on the bottom of a semiconductor package. This is an auxiliary lead for mounting. Wiring pattern on the mounting board.・Leading of mounting bases and conventional semiconductor packages. that's all

Claims (1)

【特許請求の範囲】 （ａ）半導体パッケージにおいて、 （ｂ）半導体パッケージ本体の上面に信号の入出力及び
電源用の端子を設け、 （ｃ）上記半導体パッケージの下面にも信号の入出力及
び電源用の端子を設けることを特徴とする多ピン半導体
パッケージ。[Claims] (a) In a semiconductor package, (b) Signal input/output and power supply terminals are provided on the top surface of the semiconductor package body, (c) Signal input/output and power supply terminals are also provided on the bottom surface of the semiconductor package. A multi-pin semiconductor package characterized by having terminals for
JP23924190A 1990-09-10 1990-09-10 Multi-pin semiconductor package Pending JPH04118954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23924190A JPH04118954A (en) 1990-09-10 1990-09-10 Multi-pin semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23924190A JPH04118954A (en) 1990-09-10 1990-09-10 Multi-pin semiconductor package

Publications (1)

Publication Number Publication Date
JPH04118954A true JPH04118954A (en) 1992-04-20

Family

ID=17041842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23924190A Pending JPH04118954A (en) 1990-09-10 1990-09-10 Multi-pin semiconductor package

Country Status (1)

Country Link
JP (1) JPH04118954A (en)

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