JPH0411892B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a logic evaluation circuit that can serially send evaluation data to a CPU in soft simulation of an in-circuit emulator (hereinafter referred to as ICE). belongs to.

[Conventional technology] When developing microprocessor application equipment,
By streamlining the debugging of hardware and software that occurs during development, the development period can be shortened.

When debugging software, the hardware that executes the software may not yet be complete, and it may be difficult to generate test conditions in the hardware. In such a case, it would be more efficient if simulation could be performed without using the memory or I/O of the user system.

To achieve this, some conventional ICEs are equipped with evaluation memory whose addresses correspond one-to-one with the memory and I/O of the user system.

When performing a simulation with the user system disconnected, the bus connected to the user system side is switched to the evaluation memory side when a preset condition is met. Evaluation data is then sent from the evaluation memory to the CPU.

[Problems to be Solved by the Invention] In such a conventional technique, data for only one access can be stored corresponding to each address of the memory or I/O of the user system.

Therefore, when the same address is repeatedly accessed as in I/O and different evaluation data are required, there is a problem that simulation cannot be performed.

The present invention provides a logic evaluation circuit in an ICE that can serially send evaluation data in response to any bus access by a CPU that includes the same address.

[Means for Solving the Problem] In order to achieve this object, in the present invention, when connected to the user system 1 which is the device under test,
In an in-circuit emulator for arbitrarily bus accessing the user system 1 and testing the hardware and software of the user system 1, the condition holding memory 4 holds setting conditions and the output of the condition holding memory 4. A comparator 5 compares the setting condition 52 and the status and address when the CPU 2 in the in-circuit emulator accesses the bus, and the setting condition 52 and the CPU 2
a data holding memory 6 that sends evaluation data to the bus 3 in synchronization with a match signal 81 sent from the comparator 5 when the address/status 51 of the two match, and a sequence counter 7 that sets the address 61 of the data holding memory 6. , a switch 8 that switches the bus 3 of the CPU 2 from the user system 1 side to the data holding memory 6 side in response to a coincidence signal 81. After the CPU 2 reads the evaluation data, the sequence counter 7 switches the bus 3 of the CPU 2 from the user system 1 side to the data holding memory 6 side.
Increment the address by +1.

[Operation] First, the configuration diagram of the embodiment according to the present invention will be explained as follows.
As shown in the figure.

1 in Fig. 1 is the user system which is the device under test;
2 is the CPU, 3 is the bus, 4 is the condition holding memory, 5
is a comparator, 6 is a data holding memory, 7 is a sequence counter, 8 is a switch, and 9 is a buffer.

Further, 51 is an address/status, 52 is a setting condition, 61 is an address, 71 is a strobe pulse, and 81 is a coincidence signal.

CPU2 executes and tests the program of user system 1 in place of the CPU of user system 1.
This is the CPU within the ICE. Bus 3 is an ICE bus.

The condition holding memory 4 stores conditions for sending evaluation data to the CPU 2.

The comparator 5 compares the address/status 51 sent from the CPU 2 with the setting condition 52 output from the condition holding memory 4.

Data holding memory 6 sends out evaluation data.
The address 61 of the data holding memory 6 is specified by the sequence counter 7.

The sequence counter 7 counts +1 at the trailing edge of the strobe pulse 71 when the CPU 2 reads the evaluation data. Then, the data holding memory 6 prepares the next evaluation data.

The switch 8 connects the bus 3 to the data holding memory 6 side using the coincidence signal 81 sent from the comparator 5. The buffer 9 sends the address/status 51 sent by the CPU 2 to the comparator 5 and the strobe pulse 71 to the sequence counter 7.

The operation of each part in FIG. 1 will be described below with reference to the flow of the embodiment shown in FIG. 2.

In step S1, the setting conditions 52 are input into the condition holding memory 4, and the evaluation data is input into the data holding memory 6 from the outside.

In step S2, execution of the program in the user system 1 is started.

In step S3, the CPU 2 accesses memory and the like. At this time, the address/status 51 of CPU2 is transmitted to comparator 5 through buffer 9.
sent to.

In step S4, the comparator 5 compares whether the setting condition 52 and the address status 51 match.

If NO, the bus 3 is connected to the user system 1 side and the process moves to step S8.

If YES, in step S5, the switch 8 switches the bus 3 to the data holding memory 6 side.

In step S6, the evaluation data is sent to the bus 3.

When CPU2 finishes reading the evaluation data,
In step S7, the trailing edge of the strobe pulse 71 causes the sequence counter 7 to count by +1. As a result, address 61 of data holding memory 6
is updated for the next evaluation data.

If the program of the user system 1 is not terminated at step S8, the program goes through steps S3 to S7 again.
At this time, the data holding memory 6 can send evaluation data different from the initial data to the bus 3.

Next, the timing of the switch 8 will be explained using the time chart shown in FIG.

3A shows the address/status 51 from the CPU 2, FIG. 3B shows the setting condition 52 from the condition holding memory 4, and FIG. 3C shows the match signal 81.

In FIG. 3, the address/status 51 from the CPU 2 is sequentially switched to ST0, ST1, ST2, and ST3. Here, if the setting condition 52 is set to ST2, the coincidence signal 81 becomes "1" at the timing shown in FIG.

Next, the switching state of the switching device 8 will be explained with reference to FIG. In FIG. 4A, the switch 8 connects the bus 3 and the user system 1, and in FIG. 4B, the switch 8 connects the bus 3 and the data holding memory 6.

When the coincidence signal 81 is "0" in FIG. 3C, the switch 8 is in the state of FIG. 4A, and when the coincidence signal 81 is "1" in FIG. It will be in the state shown in Figure A.

[Effects of the Invention] According to this invention, for bus access by any status including the same CPU address,
Since different evaluation data can be sent serially to the bus, I/O and interrupts can be evaluated, and the ICE has the effect of allowing complete software simulation.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment according to the present invention, and FIG.
The figure shows the flow for the embodiment, FIG. 3 is a time chart of the switch 8, and FIG. 4 is a switching state diagram of the switch 8. 1...User system, 2...CPU, 3...
Bus, 4...Condition holding memory, 5...Comparator, 51...Address/status, 52...Setting conditions, 6...Data holding memory, 61...Address, 7...Sequence counter, 71...Strobe pulse , 8...Switcher, 81... Match signal, 9... Buffer.

Claims (1)

[Scope of Claims] 1. An in-circuit emulator for testing the hardware and software of the user system by arbitrarily accessing the user system via a bus while connected to the user system as a device under test. a condition holding memory that holds setting conditions; a comparator that compares the setting conditions output from the condition holding memory with the status and address when the CPU in the in-circuit emulator accesses the bus; and the setting conditions. and a data holding memory that sends evaluation data to a bus in synchronization with a match signal sent from the comparator when the address and status of the CPU match; a sequence counter that sets the address of the data holding memory; and a sequence counter that sets the address of the data holding memory; a switch that switches the bus of the CPU from the user system side to the data holding memory side according to a signal, and after the CPU reads the evaluation data,
A logic evaluation circuit characterized in that a sequence counter increments an address of the data holding memory by +1.