JPH04111457A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH04111457A JPH04111457A JP2228262A JP22826290A JPH04111457A JP H04111457 A JPH04111457 A JP H04111457A JP 2228262 A JP2228262 A JP 2228262A JP 22826290 A JP22826290 A JP 22826290A JP H04111457 A JPH04111457 A JP H04111457A
- Authority
- JP
- Japan
- Prior art keywords
- board
- sub
- integrated circuit
- mother board
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 230000009191 jumping Effects 0.000 abstract description 7
- 238000011990 functional testing Methods 0.000 abstract description 4
- 238000013024 troubleshooting Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 2
- 238000012360 testing method Methods 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は多層金属基板構造の混成集積回路装置に関する
。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit device having a multilayer metal substrate structure.
（ロ）従来の技術
第４図を参照して従来の多層金属基板構造の混成集積回
路装置を説明する。(b) Prior Art A conventional hybrid integrated circuit device having a multilayer metal substrate structure will be described with reference to FIG.
同図は混成集積回路装置の断面構造を示し、混成集積回
路装置は２枚の絶縁金属基板（６２）（６４）、接着性
の絶縁樹脂層（６６）、導電路（６８）、パッド（７０
）、集積回路素子（７２）、チップ抵抗あるいはチップ
コンデンサ等のチップ素子（７４）、ケース材（７５）
、対の内部リード（７６）等で示されている。The figure shows a cross-sectional structure of a hybrid integrated circuit device, which consists of two insulating metal substrates (62) (64), an adhesive insulating resin layer (66), a conductive path (68), and a pad (70).
), integrated circuit elements (72), chip elements such as chip resistors or chip capacitors (74), case materials (75)
, a pair of internal leads (76), etc.
絶縁金属基板（６２）（６４）には陽極酸化処理したア
ルミニウム基板が主として使用され、絶縁樹脂層（６６
）を介して貼着しだ銅箔をホトエツチングする等して導
電路（６８）およびパッド（７０）が所定のパターンに
形成される。Anodized aluminum substrates are mainly used for the insulating metal substrates (62) and (64), and the insulating resin layer (66
), conductive paths (68) and pads (70) are formed in a predetermined pattern, such as by photo-etching the copper foil pasted through the copper foil.
集積回路素子（７２）は導電路（６８）の所定の位置に
Ａｇペースト等を使用して固着され、その他のチップ素
子（７４）および外部リード（参照番号を付さない）は
所定の導電路（６８）に半田固着される。The integrated circuit element (72) is fixed in a predetermined position on the conductive path (68) using Ag paste or the like, and the other chip elements (74) and external leads (no reference numbers) are attached to the predetermined conductive path (68). (68) is fixed by solder.
また、略り字形状の内部’Ｊ−１’ （７６）は、搭載
素子が対向するように２枚の絶縁金属基板（６２）（６
４）をケース材（７５）に固着したときに、それぞれの
絶縁金属基板（６２）（６４）のパラＩ’ （７０）に
固着された内部リード（７６）の他端が当接するように
パッド（７０）に半田固着される。内部リード（７６）
のこの当接部はリフローにより半田固着され、２枚の絶
縁金属基板（６２）（６４）上に形成された導電路（６
８）が相互接続される。In addition, the abbreviated-shaped interior 'J-1' (76) has two insulated metal substrates (62) (6) so that the mounted elements face each other.
4) is fixed to the case material (75), the pad is attached so that the other end of the internal lead (76) fixed to the para I' (70) of each insulated metal substrate (62) (64) comes into contact. (70) is fixed by solder. Internal lead (76)
This abutment part is fixed with solder by reflow, and is connected to the conductive path (6) formed on the two insulated metal substrates (62) (64).
8) are interconnected.
上記構造によれば、混成集積回路装置の投影面積を低減
することができる他、２枚の絶縁金属基板（６２）（６
４）の何れにも大電力の集積回路素子を搭載することが
できる。According to the above structure, in addition to being able to reduce the projected area of the hybrid integrated circuit device, the two insulated metal substrates (62) (6
4) A high-power integrated circuit element can be mounted on any of the above.
（ハ）発明が解決しようとする課題
しかしながら、上記構造の混成集積回路装置においては
、導電路の相互接続が可能な個所が絶縁金属基板端部に
限定されるため、所定の導電路を絶縁金属基板端部に導
かねばならない問題を有する。特にマイクロコンピュー
タを搭載する昨今の混成集積回路装置では相互接続を必
要とする導電路の数が膨大であるため、この導電路の引
き回しによって多大な素子実装面積が消費される欠点を
有している。(c) Problems to be Solved by the Invention However, in the hybrid integrated circuit device having the above structure, the locations where conductive paths can be interconnected are limited to the ends of the insulated metal substrate. This has the problem of having to be guided to the edge of the substrate. In particular, modern hybrid integrated circuit devices equipped with microcomputers have a huge number of conductive paths that need to be interconnected, and the disadvantage is that a large amount of device mounting area is consumed by routing these conductive paths. .
また、１６ビツト以上のマイクロコンピュータを搭載す
る場合には、そのデータバス、アドレスバスの幅は一回
のワイアボンディングによっては横断が不可能な大きさ
となるため、これらバスを横断する導電路の接続はこれ
までジャンピングワイア接続と称される技術により数時
に分けて行われている。このため、ジャンピングワイア
接続のための多数のパッドにより多大な素子実装面積が
消費される欠点も有している。In addition, when a microcomputer with 16 bits or more is installed, the width of the data bus and address bus becomes so large that it is impossible to cross them with a single wire bonding, so it is necessary to connect conductive paths that cross these buses. Until now, this has been done in several parts using a technique called jumping wire connection. Therefore, it also has the disadvantage that a large number of pads for connecting jumping wires consumes a large amount of device mounting area.
さらには、上記混成集積回路装置はそれぞれの絶縁金属
基板をケース材に固着した後に内部リードの半田固着が
行われるため、製造工程が煩雑であると共にその後の機
能試験が困難になるばかりか、トラブルシューティング
が不可能となる欠点を有している。Furthermore, in the above-mentioned hybrid integrated circuit device, the internal leads are soldered after each insulated metal substrate is fixed to the case material, which not only complicates the manufacturing process but also makes subsequent functional tests difficult. It has the disadvantage that shooting is impossible.
（ニ）課題を解決するための手段
本発明は上記課題に鑑みてなされたものであって、絶縁
金属基板により形成したマザー基板の所定の位置に、マ
ザー基板と同様に集積回路等を搭載すると共にジャンピ
ング接続のための導電路を備えたサブ基板を離間固着し
、サブ基板とマザー基板の導電路の相互接続をワイアボ
ンディングにより行うことによって、高密度かつ高集積
度の混成集積回路装置を捷供するものである。(d) Means for Solving the Problems The present invention has been made in view of the above problems, and includes mounting an integrated circuit, etc., in a predetermined position on a mother board formed of an insulated metal substrate, in the same way as the mother board. At the same time, a sub-board equipped with a conductive path for jumping connections is spaced and fixed, and the conductive paths of the sub-board and the mother board are interconnected by wire bonding, making it possible to create a high-density and highly integrated hybrid integrated circuit device. This is what we provide.
（ホ）作用
所定形状に導電路を形成したサブ基板をマザー基板の所
定位置に配置するため、サブ基板の任意の周端部にてサ
ブ基板とマザー基板の導電路の相互接続を行うことが可
能となり、マザー基板の導電路の引き回しが抑制される
。(e) Operation Since the sub-board with conductive paths formed in a predetermined shape is placed at a predetermined position on the mother board, the conductive paths of the sub-board and the mother board can be interconnected at any peripheral edge of the sub-board. This makes it possible to suppress the routing of conductive paths on the motherboard.
また、サブ基板の導電路によるマザー基板の導電路の長
スパンの接続が可能になり、同様にマザー基板の導電路
の引き回しが抑制されると共にジャンピング接続のため
のパッドが不要となる。Further, it becomes possible to connect a conductive path of the mother board over a long span using the conductive path of the sub-board, and similarly, routing of the conductive path of the mother board is suppressed, and pads for jumping connections are not required.
さらに、マザー基板上にサブ基板を離間固着するため、
マザー基板の全領域を素子実装に使用できる。Furthermore, in order to fix the sub board on the mother board at a distance,
The entire area of the motherboard can be used for mounting elements.
さらにまた、サブ基板とマザー基板の主面が同一方向に
面するため、サブ基板とマザー基板の導電路の相互接続
後の機能試験、トラブルシューティングが容易になる。Furthermore, since the main surfaces of the sub-board and the mother board face in the same direction, functional tests and troubleshooting after the interconnection of the conductive paths between the sub-board and the mother board are facilitated.
（へ）実施例
第１図乃至第３図を参照して本発明の一実施例を説明す
る。なお、第１図は実施例の平面図であリ、第２図は第
１図の１−１線断面図である。また、第３図はサブ基板
の平面図である。(f) Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 to 3. Note that FIG. 1 is a plan view of the embodiment, and FIG. 2 is a sectional view taken along line 1-1 in FIG. Moreover, FIG. 3 is a plan view of the sub-board.
第１図および第２図に示されるように、本発明の混成集
積回路装置はマザー基板（１０）上の所定位置にサブ基
板（３０）を離間配置する基板構造を有する
マザー基板（１０）には表面を陽極酸化処理した１５〜
２．０ｍｍ厚のアルミニウム基板が使用され、接着性の
絶縁樹脂層（図示しない）により貼着しだ銅箔をホトエ
ツチングする等して例えばアドレスバス、データバス、
制御バス等の導電路（１２）、集積回路素子（２２）の
電極とワイアボンディングするためのパッド（１４）、
外部リード用パッド（１６）、マザー基板（１０）とサ
ブ基板（３０）上にそれぞれ形成した導電路とを相互接
続するためのパッド（１８）およびサブ基板（３０）の
支持部材を固着するためのパッド（２０）等がその全面
に所定のパターンに形成される。As shown in FIGS. 1 and 2, the hybrid integrated circuit device of the present invention is mounted on a motherboard (10) having a substrate structure in which sub-boards (30) are spaced apart from each other at predetermined positions on the motherboard (10). 15~ whose surface was anodized
An aluminum substrate with a thickness of 2.0 mm is used, and an adhesive insulating resin layer (not shown) is attached, and a copper foil is photoetched to form, for example, an address bus, a data bus, etc.
A conductive path (12) such as a control bus, a pad (14) for wire bonding with an electrode of an integrated circuit element (22),
For fixing external lead pads (16), pads (18) for interconnecting the conductive paths formed on the motherboard (10) and the sub-board (30), and the supporting member of the sub-board (30). Pads (20) and the like are formed in a predetermined pattern on the entire surface.
マイクロコンピュータ、プログラマブル・ゲートアレイ
、メモリ等の集積回路素子（２２） （２４） （２６
）は所定のダイボンドパッド上にＡｇペーストを使用し
て固着され、特に発熱が多いパワー集積回路素子（２２
Ｎ２４）はヒートシンク（２８）を介して固着される。Integrated circuit elements such as microcomputers, programmable gate arrays, and memories (22) (24) (26
) is fixed using Ag paste on a predetermined die bond pad, and is used for power integrated circuit elements (22
N24) is fixed via a heat sink (28).
また、チップ抵抗あるいはチップコンデンサ等のチップ
素子（図示されていない）は半田固着される。なお、サ
ブ基板（３０）の直下に配置される集積回路素子（２６
）の電極のワイアボンディングはサブ基板（３０）の固
着前に行われる。Further, chip elements (not shown) such as chip resistors or chip capacitors are fixed by solder. Note that the integrated circuit element (26) disposed directly under the sub-board (30)
) Wire bonding of the electrodes is performed before fixing the sub-substrate (30).
次に、第３図を参照してサブ基板（３０）を説明する。Next, the sub-board (30) will be explained with reference to FIG.
同図は回路パターン形成および素子固着が完了したサブ
基板（３０）の平面構造を説明する図であり、サブ基板
（３０）はプレス成形により形成した孔（３２）および
タブ（３４）、接着性の絶縁樹脂層により片面、あるい
は両面に貼着しだ銅箔をホトエツチングする等して形成
した導電路（３６）、パッド（３８）（４０）（４２）
および所定のダイボンドパッド上にＡｇペーストを使用
して固着した集積回路素子（４６）等で示されている。This figure is a diagram explaining the planar structure of the sub-board (30) on which circuit pattern formation and element fixation have been completed. Conductive paths (36) and pads (38) (40) (42) formed by photo-etching copper foil adhered to one or both sides with an insulating resin layer.
and an integrated circuit element (46) fixed on a predetermined die bond pad using Ag paste.
サブ基板（３０）にはマザー基板（１０）への半田固着
と強度を考慮して、錫、クロム、ニッケル、鉄等を含有
する略０．５ｍｍ厚の銅合金が使用される。For the sub-board (30), a copper alloy with a thickness of approximately 0.5 mm containing tin, chromium, nickel, iron, etc. is used in consideration of solder adhesion to the mother board (10) and strength.
サブ基板（３０）の導電路（３６）はサブ基板（３０）
上の回路素子を相互接続し、バスＩ’ （４２）（１８
）を介してマザー基板（１０）上に形成した導電路（１
２）と相互接続し、さらにはパッド（４２）（１８）を
介して単にマザー基板（１０）上に形成した導電路（１
２）をジャンプ接続する。The conductive path (36) of the sub-board (30) is connected to the sub-board (30)
The circuit elements above are interconnected and bus I' (42) (18
) formed on the motherboard (10) via the conductive path (1
2) and furthermore simply formed on the motherboard (10) via the pads (42) (18).
2) Jump connect.
タブ（３４）は所定の工程において、その端部から略３
ｍｍの位置でサブ基板（３０）の面に直角に折り曲げら
れて、サブ基板（３０）とマザー基板（１０）の配置間
隔を略３ｍｍに規制する支持部（３４）となる。In a given process, the tab (34) is approximately 3
The supporting portion (34) is bent perpendicularly to the surface of the sub-board (30) at a position of mm, thereby regulating the arrangement interval between the sub-board (30) and the mother board (10) to approximately 3 mm.
なお、この支持部（３４）はサブ基板（３０）の金属の
絞り加工によって形成することも、個別の支持部材によ
っても形成することも、さらには単にサブ基板（３０）
の端部を折り曲げて形成することも可能である。また、
第３図は多面構成のサブ基板（３０）を示しているが単
面構成であっても差し支えない。Note that this support portion (34) may be formed by drawing the metal of the sub-board (30), or may be formed by an individual support member, or even simply by forming the support portion (34) on the sub-board (30).
It is also possible to form it by bending the end portion of it. Also,
Although FIG. 3 shows the sub-board (30) having a multi-sided configuration, it may also have a single-sided configuration.
再び第１図および第２図を参照して実施例をさらに詳細
に説明する。The embodiment will be described in further detail with reference to FIGS. 1 and 2 again.
マザー基板（１０）に形成したパッド（２０）にサブ基
板（３０）の支持部（３４）を半田固着すると、第１図
に図示するように、マザー基板（ｌＯ）に固着した所定
の集積回路素子（２４）がサブ基板（３０）に形成した
孔（３２）から露出すると共に集積回路素子（２４）と
パワＦ （４０）が隣接配置される。サブ基板（３０）
に孔（３２）を形成する理由は、サブ基板（３０）の電
子回路の構成要素である集積回路素子（２４）を特に放
熱特性に優れるマザー基板（１０）に固着するためであ
るが、マザー基板（１０）、サブ基板（３０）共に金属
基板を使用する本発明にあっては発熱素子を何れの基板
に配置するかは比較的自白であって、孔（３２）は本発
明に必須の構造ではない。When the support part (34) of the sub-board (30) is soldered and fixed to the pad (20) formed on the mother board (10), the predetermined integrated circuit fixed to the mother board (IO) is fixed as shown in FIG. The element (24) is exposed through the hole (32) formed in the sub-substrate (30), and the integrated circuit element (24) and the power F (40) are arranged adjacent to each other. Sub board (30)
The reason for forming the holes (32) in the sub-board (30) is to fix the integrated circuit element (24), which is a component of the electronic circuit on the sub-board (30), to the mother board (10), which has particularly excellent heat dissipation properties. In the present invention, in which metal substrates are used for both the substrate (10) and the sub-substrate (30), it is relatively obvious which substrate the heating element is placed on, and the hole (32) is an essential part of the present invention. It's not a structure.
また、集積回路素子（２２）にはパッド（１４）（４４
）が隣接配置され、その電極は必要に応じてサブ基板（
３０）、マザー基板（１０）の何れにも接続することが
可能になる。これら集積回路素子（２２）（２４）はそ
の電極面がサブ基板（３０）面と略等しい高さとなるよ
うにヒートシンク（２８）を介して固着され、ワイアボ
ンディング能率が考慮される。The integrated circuit element (22) also has pads (14) (44).
) are arranged adjacent to each other, and their electrodes are connected to the sub-substrate (
30) and the motherboard (10). These integrated circuit elements (22) and (24) are fixed via a heat sink (28) so that their electrode surfaces are approximately at the same height as the sub-substrate (30) surface, taking wire bonding efficiency into consideration.
さらに、サブ基板（３０）に形成したパッド（４２）と
マザー基板（１０）に形成したバンド（１８）とをワイ
アボンディングすることにより、サブ基板（３０）の電
子回路とマザー基板（１０）の電子回路の相互接続が行
われ、またマザー基板（１０）に形成した導電路（１２
）のジャンピング接続が行われる。Furthermore, by wire bonding the pad (42) formed on the sub-board (30) and the band (18) formed on the mother board (10), the electronic circuit of the sub-board (30) and the mother board (10) are bonded. The interconnections of the electronic circuits are made, and the conductive paths (12) formed on the motherboard (10) are
) jumping connections are made.
既に明らかなように、本発明の混成集積回路装置はマザ
ー基板（１０）上の所定位置にサブ基板（３０）を離間
配置する基板構造を有するため、サブ基板（３０）の固
着工程、サブ基板（３０）上の導電路とマザー基板（１
０）上の導電路の相互接続工程はマザー基板（１０）上
に固着される集積回路素子、あるいはチップ素子と同等
に行われ、ケーシングを除く製造、試験工程がマザー基
板（１０）上で完了する。また、本発明の混成集積回路
装置は最終的にケース材（図示しない）により封止され
るが、従来のケース材の中空構造内に収納することがで
きる。As is already clear, since the hybrid integrated circuit device of the present invention has a substrate structure in which the sub-board (30) is spaced apart from a predetermined position on the mother board (10), the fixing process of the sub-board (30), the sub-board (30) The conductive path on the motherboard (1
0) The interconnection process of the conductive paths above is performed in the same way as for integrated circuit elements or chip elements fixed on the motherboard (10), and the manufacturing and testing processes except for the casing are completed on the motherboard (10). do. Furthermore, although the hybrid integrated circuit device of the present invention is finally sealed with a case material (not shown), it can be housed within the hollow structure of a conventional case material.
以上本発明の一実施例を説明したが、本発明はサブ基板
の平面形状等に関して種々の変形が可能であって、実施
例に限定されるものではない。Although one embodiment of the present invention has been described above, the present invention can be modified in various ways with respect to the planar shape of the sub-board, etc., and is not limited to the embodiment.
（１）発明の効果
以上述べたように本発明の混成集積回路装置は（１）マ
ザー基板の導電路とサブ基板の導電路との相互接続を任
意の位置で行うことが可能なため導電路の引き回しによ
る実装面積の低下が回避される。(1) Effects of the Invention As described above, the hybrid integrated circuit device of the present invention has the following advantages: (1) Since the conductive path of the mother board and the conductive path of the sub-board can be interconnected at any position, the conductive path This avoids a reduction in mounting area due to routing.
（２）サブ基板の導電路によるマザー基板の導電路の長
スパンの接続が可能であるためジャンピング接続のため
のパッドが不要になり実装面積の低下が回避される。(2) Since a long span of the conductive path on the mother board can be connected by the conductive path on the sub-board, pads for jumping connections are not required, and a reduction in the mounting area can be avoided.
（３）マザー基板、サブ基板共に金属基板を使用するた
め発熱素子の配置が自白である。(3) Since metal substrates are used for both the mother board and the sub-board, the arrangement of the heating elements is obvious.
（４）マザー基板上にサブ基板を離間固着するためマザ
ー基板の全領域を素子実装に使用できる。(4) Since the sub-boards are spaced and fixed on the mother board, the entire area of the mother board can be used for mounting elements.
（５）サブ基板とマザー基板の主面が同一方向に面する
ため、サブ基板とマザー基板の導電路の相互接続後の機
能試験、トラブルシューティングが容易である。(5) Since the main surfaces of the sub-board and the mother board face in the same direction, it is easy to perform functional tests and troubleshooting after interconnecting the conductive paths between the sub-board and the mother board.
（６）集積回路としてチップ素子を使用するため高集積
度が達成される。(6) A high degree of integration is achieved because chip elements are used as integrated circuits.
（７）サブ基板に加工が容易な銅合金を使用するため離
間固着のための支持部を一体成形することができる。(7) Since a copper alloy that is easy to process is used for the sub-board, the supporting part for separating and fixing can be integrally molded.
第１図は本発明の一実施例の平面図、第２図は第１図の
Ｉ−Ｉ線断面図、第３図は本発明で使用されるサブ基板
の平面図、第４図は従来の混成集積回路装置の平面図。
１０・・・マザー基板、１２．３６・・・導電路、１４
．３８．４０．４４・・・パッド、 １６・・外部リ
ード用パッド、 １８．４２・・・内部接続用パッド
、 ２゜・・・支持部材用パッド、 ２２．２４．
４６・・・集積回路素子、 ３０・・・サブ基板、
３２・・・孔、 ３４・・・支持部材。FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2 is a sectional view taken along the line II in FIG. 1, FIG. 3 is a plan view of a sub-board used in the present invention, and FIG. 4 is a conventional FIG. 2 is a plan view of a hybrid integrated circuit device. 10...Mother board, 12.36...Conducting path, 14
．． 38.40.44... Pad, 16... Pad for external lead, 18.42... Pad for internal connection, 2°... Pad for support member, 22.24.
46... Integrated circuit element, 30... Sub board,
32... Hole, 34... Supporting member.
Claims (6)
し、その導電路の所定位置に少なくとも集積回路素子を
固着搭載したマザー基板と、 第２の絶縁金属基板上に所定形状に導電路を形成し、そ
の導電路の所定位置に集積回路素子および、あるいはチ
ップ抵抗、チップコンデンサ等のチップ素子を固着搭載
したサブ基板とから構成され、 前記サブ基板をマザー基板上の所定位置に、所定間隔離
間して固着すると共に、サブ基板とマザー基板の導電路
の接続をワイアボンディングにより行ったことを特徴と
する混成集積回路装置。(1) A motherboard in which a conductive path is formed in a predetermined shape on a first insulated metal substrate, and at least an integrated circuit element is fixedly mounted on a predetermined position of the conductive path; It is composed of a sub-board that forms a conductive path and firmly mounts an integrated circuit element and/or a chip element such as a chip resistor or a chip capacitor at a predetermined position on the conductive path, and the sub-board is mounted at a predetermined position on a mother board. A hybrid integrated circuit device, characterized in that the sub-board and the mother board are fixedly spaced apart from each other by a predetermined distance, and the conductive paths of the sub-board and the mother board are connected by wire bonding.
の導電路を介して行ったことを特徴とする請求項１記載
の混成集積回路装置。(2) The hybrid integrated circuit device according to claim 1, wherein the required conductive paths of the mother board are connected via conductive paths of a sub-board.
形成したことを特徴とする請求項１記載の混成集積回路
装置。(3) The hybrid integrated circuit device according to claim 1, wherein the second insulated metal substrate is made of copper or a copper alloy.
部に形成したタブを折り曲げてサブ基板の支持部とした
ことを特徴とする請求項１記載の混成集積回路装置。(4) The hybrid integrated circuit device according to claim 1, wherein the end of the sub-board is bent, or a tab formed at the end of the board is bent to serve as a supporting part of the sub-board.
小面積としたことを特徴とする請求項１記載の混成集積
回路装置。(5) The hybrid integrated circuit device according to claim 1, wherein the area of the sub-board is smaller than that of the mother board.
徴とする請求項１記載の混成集積回路装置。(6) The hybrid integrated circuit device according to claim 1, wherein a chip element is used as the integrated circuit element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2228262A JP2865400B2 (en) | 1990-08-31 | 1990-08-31 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2228262A JP2865400B2 (en) | 1990-08-31 | 1990-08-31 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04111457A true JPH04111457A (en) | 1992-04-13 |
| JP2865400B2 JP2865400B2 (en) | 1999-03-08 |
Family
ID=16873720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2228262A Expired - Fee Related JP2865400B2 (en) | 1990-08-31 | 1990-08-31 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2865400B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8044498B2 (en) | 2006-07-12 | 2011-10-25 | Genusion Inc. | Interposer, semiconductor chip mounted sub-board, and semiconductor package |
-
1990
- 1990-08-31 JP JP2228262A patent/JP2865400B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8044498B2 (en) | 2006-07-12 | 2011-10-25 | Genusion Inc. | Interposer, semiconductor chip mounted sub-board, and semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2865400B2 (en) | 1999-03-08 |
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