JPH04109771A - Horizontal synchronizing signal generation circuit - Google Patents

Abstract

PURPOSE:To synchronize an internal horizontal synchronizing signal with an external horizontal synchronizing signal early by inhibiting the input of a reset pulse to a horizontal synchronizing reference signal generating circuit when a discrimination circuit discriminates it that a phase difference is within a tracking enable range and giving the reset pulse to the horizontal synchronizing reference signal generating circuit when the discrimination circuit discriminates it that a phase difference is at the outside of the tracking enable range. CONSTITUTION:A reset pulse RP is given from an OR gate 45 to a decoder 42. The decoder 42 generates mask signal MS1, MS2 representing respectively dead bands 1,2 provided at a prescribed time width before and after a leading edge of a generated internal horizontal synchronizing reference signal HD1. The dead band 1 has a very narrow time width. The dead band 2 has a very wide time width. When the leading edge of an external horizontal synchronizing reference signal HD0 exists in the range of the dead band 1 or 2, no reset pulse RP is generated and only when the leading edge is at the outside of the dead band 1 or 2, the reset pulse RP is given to the decoder 42.

Description

BACKGROUND OF THE INVENTION The present invention relates to a horizontal synchronization signal generation circuit that generates and outputs an internal horizontal synchronization reference signal synchronized with an external horizontal synchronization reference signal applied from the outside.

Create an internal horizontal synchronization reference signal and an internal vertical synchronization reference signal that are synchronized with the external horizontal synchronization reference signal and external vertical synchronization reference signal given from the outside, and synchronize based on the created internal horizontal and vertical synchronization reference signals. The control circuit is used, for example, in a slave synchronization signal generator in a system with two master and slave synchronization signal generators (S S G), as shown in FIGS. 1 and 2.

In FIG. 1, a main synchronization signal generator 10 is a reference oscillator 11 that generates a reference clock signal (for example, 28 MHz).
Based on this reference clock signal, a horizontal synchronization reference signal HD for incremental scanning, a vertical synchronization reference signal VD, a synchronization pulse CP for color separation, etc. are created and output. Horizontal and vertical synchronization reference signals HD and vDo are applied to slave synchronization signal generator 2OA as external horizontal and vertical synchronization reference signals. The synchronization pulse CP is given to a color separation synchronization signal generator 12, and this generator 12
A synchronization signal for color separation is created by.

The slave synchronization signal generator 20A generates PLL (Phase
The above-mentioned synchronous control circuit including the LockedLoop) circuit 21 is built-in. This synchronous control circuit is a PLL circuit 2
External horizontal and vertical synchronization signals HD given from the main synchronization signal generator IO using clock signals generated from 1
and VDo to create internal horizontal and vertical synchronization signals synchronized with these, respectively.

Based on this, a CCD (Ch
horizontal and vertical drive signals φH and φV of CCD 22 and CCD 2
A sampling signal CDS of the read signal from 2 is created and output.

In FIG. 2, the slave synchronization signal is generated from the main synchronization signal generator lO! 20B, external horizontal and vertical synchronization signal HDo
and vDo, a clock signal (for example, 14 MHz) obtained by frequency-dividing the reference clock signal is provided. Since the slave synchronization signal generator 20B is supplied with a clock signal, it is not necessary to provide a PLL clock. The slave synchronization signal generator 20B uses the input clock signal to create internal horizontal and vertical synchronization reference signals that are synchronized with the external horizontal and vertical synchronization reference signals HD and vDo, respectively, and generates hybrid synchronization signals C and 5YNC from these signals. Create and output.

In FIG. 2, the main synchronizing signal generator 10 generates horizontal and vertical drive signals φH1φV, etc. for the CCD 22.

The system shown in FIGS. 1 and 2 includes, for example, a circuit (white balance adjustment circuit, γ It is applied to systems that are separated from the main body and have built-in circuits (including correction circuits, matrix circuits, encoders, etc.). When the system shown in FIG. 1 is applied, the slave synchronization signal generator 2OA is provided in the camera head, and the main synchronization signal generator 10 is provided in the video signal processing circuit. The system shown in FIGS. 1 and 2 also. The present invention is applied to a system consisting of a recorder such as a still e-video camera or a video camera that records captured video signals on a recording medium, and a playback device connected to the recorder. If the system shown in FIG. 2 is applied to this system.

The main synchronization signal generator 10 is used as a recorder, and the slave synchronization signal generator 2
0B will be built into each playback machine. In this case, the external horizontal and vertical synchronization reference signals HDo and ■Do may be supplied to the slave synchronization signal generator 20B separately from the video signal, or may be supplied superimposed on the video signal to the slave synchronization signal generator 20B.
B may be used for synchronous separation. The system shown in FIG. 1 is used when both generators 10 and 20A are located relatively far apart, and the system shown in FIG. 2 is used when both generators 10 and 20B are located relatively close to each other. Are suitable.

For the sake of clarity, only the horizontal synchronization reference signal will be mentioned. The slave synchronization signal generators 2OA and 20B shown in FIGS. A horizontal reset circuit is provided to synchronize the internal horizontal synchronization reference signal generated by the external horizontal synchronization reference signal with the external horizontal synchronization reference signal. This horizontal reset circuit basically resets the internal horizontal synchronization reference signal creation circuit at a predetermined timing of the external horizontal synchronization reference signal when the created internal horizontal synchronization reference signal is out of synchronization, and outputs the signal from this circuit. Forces the internal horizontal sync reference signal to be external horizontal sync 7! This is to synchronize with the quasi-signal.

As shown in FIG. 2, when the main synchronization signal generator 10 and the slave synchronization signal generator 20B use a common clock signal, the main synchronization signal generator 10
A phase difference occurs between the clock signal used in the slave synchronization signal generator 20B and the clock signal used in the slave synchronization signal generator 20B. Both generators lO
In order to prevent the occurrence of jitter due to the phase difference between the clock signals used in the horizontal reset circuit and 20B, a narrow dead zone of approximately ±1 period of the clock signal was conventionally provided in the horizontal reset circuit.

Is the internal synchronization reference signal and external synchronization reference signal synchronized?
If the period is within one clock signal period, the reset operation is not performed, and the reset is performed only when the synchronization difference exceeds that period.

However, in the slave synchronization signal generator 2OA incorporating the PLL circuit 21 shown in FIG. 1, it is not possible to adopt the above-mentioned concept of providing a narrow dead zone.

The PLL circuit detects a phase difference between an external horizontal synchronization reference signal and an internal horizontal synchronization reference signal, and controls the oscillation frequency of a voltage-controlled oscillator that outputs a clock signal in accordance with this phase difference. This is because in such a narrow dead zone as described above, reset is always performed, and correct phase comparison is not performed in the PLL circuit, and the oscillation frequency of the voltage controlled oscillator will not be appropriate. It may be possible to not perform the reset operation, but in that case P
There is a problem in that the transient response time of the PLL circuit is long until the LL circuit is stabilized and proper synchronization is achieved.

SUMMARY OF THE INVENTION Object of the Invention A first aspect of the invention is to perform appropriate reset processing in a horizontal synchronization signal generation circuit including a PLL circuit.

Therefore, it is an object of the present invention to enable early synchronization of an internal horizontal synchronization reference signal with an external horizontal synchronization reference signal.

The second invention is used for both a slave synchronization signal generator including a PLL circuit as shown in FIG. 1 and a slave synchronization signal generator that shares a lock signal with the main synchronization signal generator as shown in FIG. An object of the present invention is to provide a horizontal synchronization signal generation circuit that can perform the following functions.

Structure 1 of the Invention Operation and Effect The horizontal synchronization signal generation circuit according to the first invention includes a horizontal synchronization reference signal generation circuit that generates an internal horizontal synchronization reference signal based on an input clock signal and a reset pulse; a phase comparator that compares the phases of the synchronization reference signal and the internal horizontal synchronization reference signal output from the horizontal synchronization reference signal generation circuit and generates a voltage signal according to the phase difference; an output voltage signal of the phase comparator; a low-pass filter that passes low-frequency components of the low-pass filter, a voltage-controlled oscillator whose oscillation frequency is controlled by the output voltage signal of the low-pass filter and generates a clock signal to be applied to the horizontal synchronization reference signal generation circuit, and the internal horizontal synchronization circuit. A determination circuit that determines whether the phase difference between the reference signal and the external horizontal synchronization reference signal is within a range that can be tracked by the voltage controlled oscillator, and a reset pulse that is synchronized with a predetermined edge of the external horizontal synchronization reference signal. When the generated reset pulse generation circuit and the determination circuit determine that the phase difference is within the trackable range, the input of the reset pulse to the horizontal synchronization reference signal generation circuit is prohibited, and the The present invention is characterized by comprising a reset control circuit that applies the reset pulse to the horizontal synchronization reference signal generation circuit when it is determined that the phase difference is outside the followable range.

What is the tracking range of the above voltage controlled oscillator?

The phase difference between the internal horizontal synchronization reference signal and the external horizontal synchronization reference signal is between the maximum oscillation frequency and the minimum oscillation frequency of the voltage controlled oscillator, and the control voltage generated from the phase comparator accordingly. is within a two-phase difference between a first limit control voltage that causes the maximum oscillation frequency of the voltage controlled oscillator and a second limit control voltage that causes the minimum oscillation frequency of the voltage controlled oscillator. It will be checked.

In reality, a phase difference range serving as a determination criterion may be determined in the vicinity of a phase difference range corresponding to a followable range.

The above-mentioned horizontal synchronization reference signal generation circuit 1 phase comparator.

The low pass filter and voltage controlled oscillator constitute a PLL circuit.

When the phase difference between the internal horizontal synchronization reference signal and the external horizontal synchronization reference signal is outside the range that can be tracked by the voltage controlled oscillator, the PLL circuit does not stabilize easily, and the internal horizontal synchronization reference signal or the external horizontal synchronization It takes a considerable amount of time to synchronize to the reference signal. According to the first invention,
In such a case, a reset pulse is given to the horizontal synchronization reference signal generation circuit, and the internal horizontal synchronization reference signal generated from the horizontal synchronization reference signal generation circuit maintains a certain timing relationship with the external horizontal synchronization reference signal. From then on, the PLL circuit is in a stable state in which normal synchronization control is possible, and due to the original synchronization function of the PLL circuit, the internal horizontal synchronization reference signal is quickly synchronized with the external horizontal synchronization reference signal. will now be synchronized. Furthermore, when the phase difference is relatively small, it is well within the followable range of the voltage controlled oscillator, and at this time, resetting of the horizontal synchronization reference signal generation circuit is prohibited, so that the PLL is constantly reset. This prevents a situation in which the phase comparison in the circuit is not performed correctly. In this way, it becomes possible to synchronize the internal horizontal synchronization reference signal with the external horizontal synchronization reference signal at high speed.

A horizontal synchronization signal generation circuit according to a second invention includes a horizontal synchronization reference signal generation circuit that creates an internal horizontal synchronization reference signal based on an input clock signal and a reset pulse; a circuit that generates a first mask signal that defines a first dead zone and a second mask signal that defines a second dead zone that is wider than the first dead zone; a dead band switching circuit for selecting one of the signals; a reset pulse for generating a reset pulse synchronized to a predetermined edge of the internal horizontal synchronization reference signal corresponding to the predetermined edge of the internal horizontal synchronization reference signal of a given external horizontal synchronization reference signal; It is determined whether or not the predetermined edge of the external horizontal synchronization reference signal exists within the dead zone defined by the mask signal selected by the generation circuit and the dead zone switching circuit, and when it does not exist, the horizontal synchronization reference signal generation circuit The device is characterized in that it includes a reset control circuit that applies the reset pulse to the device.

The dead zone is a range in which resetting of the horizontal synchronization reference signal generation circuit is prohibited. The first dead zone is set to a width suitable for the system shown in Figure 2, that is, a slave synchronization signal generator that uses a common clock signal with the main synchronization signal generator, for example, ±1 clock pulse period as described above. Ru. Second
The dead zone of
As in the invention of 2.0, the followable range of the voltage controlled oscillator included in the PLL circuit is set to be positive.

According to the second invention, the system shown in FIG.
A dead zone switching signal is created depending on whether one of the systems shown in the figure is used. and.

When the system shown in FIG. 1 is used, a second mask signal defining a second dead zone is selected.

When the system shown in FIG. 2 is used, a first mask signal defining a first dead zone is selected. It is thus determined whether a predetermined edge of the external horizontal synchronization reference signal exists within the selected dead zone, and only if the predetermined edge does not exist, the horizontal synchronization reference signal generating circuit is reset. In this way, a horizontal synchronization signal generation circuit is realized which is applicable to both the system shown in FIG. 1 and the system shown in FIG. 2, and which can perform horizontal reset processing suitable for each system.

DESCRIPTION OF THE EMBODIMENTS FIG. 3 shows an outline of the configuration of a slave synchronization signal generator that can be used in common with the system shown in FIG. 1 and the system shown in FIG.

The slave synchronization signal generator 20 is a horizontal synchronization reference signal generation circuit 2
3. An external horizontal synchronization reference signal HD is provided from a main synchronization signal generator and includes a vertical synchronization reference signal generation circuit 24 and a circuit 25 for creating various timing or synchronization signals. and input terminals 31 and 32 of the external vertical synchronization reference signal VDO, an external low-pass filter 26 and a voltage controlled oscillator 2 that form part of the PLL circuit.
Terminals 34 and 35 for connecting 7. Input terminal 33 for the clock signal provided from the main synchronization signal generator. Input terminal 36 for dead band switching signal. It also includes terminals 37 for outputting drive signals φH1φV, sampling signals CDS, synchronization signals C, 5YNC, etc. generated by the various signal generation circuits 25.

The external horizontal synchronization reference signal HDo is input to the horizontal synchronization reference signal generation circuit 23 via the input terminal 31, and the external vertical synchronization reference signal V
Do is connected to the vertical synchronization reference signal generation circuit 2 via the input terminal 32.
4 respectively.

When this slave synchronization signal generator 20 is used in the system shown in FIG.
A low pass filter 26 and a voltage controlled oscillator 27 are connected between 4 and 35. The oscillation output of the voltage controlled oscillator 27 is input as a clock signal to the horizontal synchronization reference signal generation circuit 23 via a terminal 35. When this slave synchronization signal generator 20 is used in the system shown in FIG. 2, it is not necessary to connect the low-pass filter 26 and the voltage-controlled oscillator 27.
Instead, the clock signal given from the main synchronization signal generator is passed through the terminal 33 to the horizontal synchronization reference signal generation circuit 23.
Enter. The oscillation center frequency of the voltage controlled oscillator 27 and the frequency of the clock signal manually input via the terminal 33 given from the main synchronization signal generator do not necessarily have to be the same, but if they are different, the horizontal synchronization reference signal generation circuit 23
In order to make the frequency of the clock signal input to the system the same when used in the system of FIG. 1 and when used in the system of FIG. 2, a divide-by-1 circuit or the like may be provided. For example, if the oscillation center frequency of the voltage controlled oscillator 27 is 28 MHz,
When the frequency of the clock signal applied to the terminal 23 from the main synchronous oscillator is 14 MHz, a circuit is provided to divide the clock signal input from the voltage controlled oscillator 27 via the terminal 35 by 1/2, and converts the clock signal into a 14 MHz clock signal. The signal is applied to the horizontal synchronization reference signal generation circuit 23. These clock signals are also provided to the vertical synchronization reference signal generation circuit 24.

Also in the horizontal synchronization reference signal generation circuit 23. When used in either system, the dead band switching signal is connected to terminal 36.
Input via .

The horizontal synchronization reference signal generation circuit 23 uses the input clock signal to generate an external horizontal synchronization reference signal HD.

An internal horizontal synchronization reference signal HD1 synchronized with is generated, and the vertical synchronization reference signal generation circuit 24 uses the input clock signal to generate an external vertical synchronization reference signal vD.

An internal vertical synchronization reference signal VD1 synchronized with is created.

The frequency dividing circuit and the like included in these generation circuits 28 and 24 (included in a decoder 42 to be described later) can be shared. The internal horizontal and vertical synchronization reference signals HD and VD created and output by the generation circuits 23 and 24 are given to the various signal creation circuits 25, and these input signals H
The various signals φH2φ described above based on D and VD
V. CDS.

C, 5YNC, etc. are generated.

FIG. 4 shows an example of an external horizontal synchronization reference signal HDo and an external vertical synchronization reference signal VDo.

FIG. 5 shows a specific example of the horizontal synchronization reference signal generation circuit 23. In this figure, the same parts as those shown in FIG. 3 are given the same reference numerals. Also, Figures 6 and 7 are
3 is a time chart showing the operation of the circuit shown in the figure.

Phase comparator 41. Low pass filter 26. The voltage controlled oscillator 27 and the decoder 42 constitute a PLL circuit. The voltage controlled oscillator 27 generates a clock signal having a center frequency of an appropriate frequency (for example, 14 MHz), and its oscillation frequency is controlled by the output voltage of the phase comparator 41 applied through the low-pass filter 26. The decoder 42 includes a circuit for frequency dividing the clock signal input from the oscillator 27, a counter, a logic circuit, etc., and uses the input gate signal to generate an internal horizontal synchronization reference signal H.
Create D. The external horizontal synchronization reference signal HDo given from the main synchronization signal generator and the internal horizontal synchronization reference signal HD output from the decoder 42 are given to the phase comparator 41, and a voltage signal corresponding to the phase difference is sent to the phase comparator 41. 41. As a result, the internal horizontal synchronization reference signal HD generated from the decoder 42 by the reset process of the decoder 42, which will be described later, is synchronized with the external horizontal synchronization reference signal HDo.

If the low-pass filter 26 and the voltage-controlled oscillator 27 are not provided, the tarock signal from the main synchronization signal generator is supplied to the decoder 42 through the terminal 33, so that the decoder 42 receives the internal horizontal synchronization reference signal. H
D occurs. In this case, the internal horizontal synchronization reference signal HD generated from the decoder 42 is synchronized with the external horizontal synchronization reference signal HDo by the reset process of the decoder 42.

The reset process of the decoder 42 is a process for aligning the leaving edge (falling edge) of the internal horizontal synchronization reference signal HD generated from the decoder 42 with the leading or edge of the external horizontal synchronization reference signal HDo at an appropriate timing. The reset pulse RP is provided by an OR gate 45, which will be described later.
is applied to the decoder 42.

The decoder 42 also generates two internal horizontal synchronization reference signals H
Mask signals MSI and MS2 respectively representing dead zones 1 and 2 provided with a predetermined time width before and after the leading or edge of D are generated. Dead band 1
and 2 are for prohibiting the input of the reset pulse RP to the decoder 42.

The dead zone 1 is applied when the slave synchronization signal generator 20 is used in the system shown in FIG. 2, and has a very narrow time width as shown in FIG. 6. For example, dead zone 1 is set to have a time width of ±1 period of the clock signal centered on the leading edge of the internal horizontal synchronization reference signal.

The dead zone 2 is applied when the slave synchronization signal generator 20 is used in the system shown in FIG. 1, and has a very wide time width as shown in FIG. 7. The dead zone 2 is set to approximately the maximum width of the traceable range of the oscillation frequency of the voltage controlled oscillator 27. The followable range of the voltage controlled oscillator 27 refers to the range between the maximum oscillation frequency and the minimum oscillation frequency of the voltage controlled oscillator 27, and includes the internal horizontal synchronization reference signal HD,
The phase difference between the external horizontal synchronization reference signal HDo and the external horizontal synchronization reference signal HDo (the time difference between their leading edges) is the first limit at which the control voltage generated from the phase comparator 41 produces the maximum oscillation frequency of the voltage controlled oscillator 27. The range is such that it lies between the control voltage and a second limit control voltage that produces a minimum oscillation frequency. The dead zone 2 is, for example, about more than 10% of one period of the horizontal synchronization reference signal.

Dead zones 1 and 2 and mask signals MSI and MS2 representing them are shifted by one period of the clock signal.

Mask signals MSI and MS2 are applied to dead zone switching circuit 43. The dead zone switching circuit 43 includes two AND gates 51 and 52, and an OR gate 53 which receives the outputs of these AND gates 51 and 52 as inputs. Mask signal MSI is applied to AND gate 51, and mask signal MS2 is applied to AND gate 52. The dead band switching signal inputted through the terminal 36 is applied as is to the AND gate 51, and also to the AND gate 5.
It is inverted and given to 2. When the slave synchronization signal generator 20 is used in the system shown in FIG. 2, the dead zone switching signal is kept at H level, so the mask signal MSI passes through the switching circuit 43, and when used in the system shown in FIG. Since the dead zone switching signal is held at L level, the mask signal MS2 passes through the switching circuit 43. Dead band switching circuit 4
The mask signal selected in this way by 3 is OR
input to gate 45;

The differentiating circuit 44 generates a differentiating pulse DP serving as a reset pulse RP. This differential pulse DP is a leading edge (falling) detection pulse of the external horizontal synchronization reference signal HDo. The differentiating circuit 44 is composed of two D flip-flops 55 and 56 and an AND gate 57. A tarok signal is applied to the clock input terminals of D flip-flops 55 and 5B.

, the external horizontal synchronization reference signal HDo is applied to the data input terminal of the D flip-flop 55, and the non-inverted output of the D flip-flop 55 is applied to the data input terminal of the D flip-flop 5B. The AND gate 57 has the inverted output of the D flip-flop 55 and the D flip-flop 56.
The AND gate 57 inverts and outputs the AND logic signal of these input signals. Therefore, from the differentiating circuit 44, the external horizontal synchronization reference signal HD
When o falls (leading edge), a differential pulse DP having a pulse width of one clock signal period is generated, which falls at the next rising edge of the clock signal. This differential pulse DP is applied to an OR gate 45.

Dead zones 1 and 2 are periods in which mask signals MSI and MS2 are at H level, respectively. In contrast, the differential pulse DP is a negative pulse. Therefore, the mask signal is H
The differential pulse DP generated when the level (dead zone) is O
Do not pass through R gate 45. On the other hand, when the differential pulse DP is generated when the mask signal is at L level (outside the dead zone), this differential pulse passes through the OR gate 45 and is applied to the decoder 42 as a reset pulse RP. If necessary, a delay circuit may be provided after the OR gate 45.

The mask signals MSI and MS2 are delayed by one period of the clock signal from dead zones 1 and 2.

This is because the differential pulse DP is generated one cycle of the clock signal later than the leading edge of the external horizontal synchronization reference signal HD.

Therefore, as shown in FIGS. 6 and 7, if the leading edge of the external horizontal synchronization reference signal HDo exists within dead zone 1 or 2, the reset pulse RP
will not occur, and the reset pulse RP will be applied to the decoder 42 only when the leading edge of the external horizontal synchronization reference signal HDo is outside the dead zone 1 or 2.

In the system shown in FIG. 1, a wide dead zone 2 is selected as described above. Therefore, the internal horizontal synchronization reference signal HD1 generated from the decoder 42 and the external horizontal synchronization reference signal HD
The synchronization with o is thick (out of sync).

A reset pulse RP is applied to the decoder 42 only when the phase difference between the two signals is so large that the PLL circuit cannot follow it. As a result, the phase difference between the internal horizontal synchronization reference signal HD and the external horizontal synchronization reference signal HDo becomes small, the PLL circuit operates stably, and the synchronization between the two signals HD and HDo is quickly established.

In the system shown in FIG. 2, a narrow dead zone 1 is selected.

In the system shown in Fig. 2, the clock signal is given from the main synchronous generator to the slave synchronous generator 2o, so the very narrow dead zone 1 is Reset processing of the decoder 42 is prohibited within this range.

[Brief explanation of the drawing]

FIGS. 1 and 2 are block diagrams showing examples of systems including a main synchronization signal generator and a slave synchronization signal generator, respectively. FIG. 3 is a block diagram showing the configuration of the slave synchronization signal generator. FIG. 4 is a time chart showing external horizontal and vertical synchronization reference signals. FIG. 5 is a circuit diagram showing the configuration of a horizontal synchronization reference signal generation circuit. 6 and 7 are time charts showing the operation of the circuit shown in FIG. 5. 23...Horizontal synchronization reference generation circuit. 26...Low pass filter. 27...Voltage controlled oscillator. 41...Phase comparator. 42...Decoder. 43...Dead zone switching circuit. 44... Differential circuit. 45...OR gate. Agent for the above patents: Fuji Photo Film Co., Ltd.
Person Patent Attorney Ken Ushiku Figure 2

Claims (2)

[Claims] (1) A horizontal synchronization reference signal creation circuit that creates an internal horizontal synchronization reference signal based on an input clock signal and a reset pulse; a given external horizontal synchronization reference signal and the above output from the horizontal synchronization reference signal creation circuit; a phase comparator that compares the phases of internal horizontal synchronization reference signals and generates a voltage signal according to the phase difference; a low-pass filter that passes a low frequency component of the output voltage signal of the phase comparator; A voltage controlled oscillator whose oscillation frequency is controlled by the output voltage signal of the filter and generates a clock signal to be applied to the horizontal synchronization reference signal generation circuit. a reset pulse generation circuit that generates a reset pulse in which the phase difference between the internal horizontal synchronization reference signal and the external horizontal synchronization reference signal is synchronized with a predetermined edge of the external horizontal synchronization reference signal by the voltage controlled oscillator; Prohibiting input of the reset pulse to the horizontal synchronization reference signal generation circuit when the determination circuit determines that the phase difference is within the followable range; and when the determination circuit determines that the phase difference is outside the followable range. a reset control circuit that applies the reset pulse to the horizontal synchronization reference signal generation circuit when it is determined that horizontal synchronization signal generation circuit. (2) a horizontal synchronization reference signal generation circuit that creates an internal horizontal synchronization reference signal based on the input clock signal and reset pulse;
a circuit that generates a first mask signal that defines a dead zone and a second mask signal that defines a second dead zone that is wider than the first dead zone; a dead zone switching circuit that selects either one of the two, a reset pulse generation circuit that generates a reset pulse synchronized with a predetermined edge corresponding to the predetermined edge of the internal horizontal synchronization reference signal of a given external horizontal synchronization reference signal; and determines whether or not the predetermined edge of the external horizontal synchronization reference signal exists within the dead zone defined by the mask signal selected by the dead zone switching circuit, and when the predetermined edge of the external horizontal synchronization reference signal does not exist, resets the horizontal synchronization reference signal generation circuit.・Horizontal synchronization signal generation circuit equipped with a reset control circuit that provides pulses.