JPH04109666A - Bicmos logic circuit - Google Patents

Abstract

PURPOSE:To operate at a high speed even by a low power source voltage by charging the base of an N-P-N bipolar transistor by both an N-channel MOS logic unit and a P-channel MOSFET connected in parallel with the N-channel unit. CONSTITUTION:When N-channel MOSFETs 8, 9 for constituting a CMOS logic circuit 1 are conducted and the output of the logic circuit 1 falls, a base 5 of a second N-P-N bipolar transistor is charged by both an N-channel MOS logic unit 2 and a P-channel MOSFET 12 connected in parallel with the unit 2. Accordingly, the base potential of the transistor 5 is charged to a high level. Thus, even if a power source voltage is low, a high speed operation can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a B i CMOS logic circuit suitable for low power supply voltage operation.

BACKGROUND ART In recent years, as integrated circuits have become faster, BiCMOS circuits have come into use. - As an iCMOS circuit for boat fishing, an iCMOS logic circuit as shown in FIG. 5, for example, is known.

A conventional BiCMOS logic circuit will be described below with reference to FIG.

FIG. 5 is a circuit diagram showing a conventional two-man NAND logic BiCMOS logic circuit.

The CMOS logic circuit 21 has an input signal circuit 1. ■2 NAN
It outputs D logic, and O8FET between P channels (
Parallel circuit of 26.27 (hereinafter abbreviated as PMOS) and N-channel MO3FET (hereinafter abbreviated as NMOS) 28.2
9 series circuits are connected in series between the power supply VDD terminal and the ground terminal, PMOS 26 and NMOS 28
(7) 'y'-to! : Input the input signal Il, PMOS
The input signal I2 is input to the gates of PMOS 27 and NMOS 29, and the connection point between the drains of PMOS 26 and 27 and the drain of NMOS 28 is used as an output point.

The output point of this CMOS logic circuit 21 is connected to the base of an NPN bipolar transistor 24.

The collector of the NPN bipolar transistor 24 is connected to the power supply V. It is connected to the D terminal, and its emitter is connected to the output terminal of the output signal O. Furthermore, an NPN bipolar transistor 25 is connected between the emitter of the NPN bipolar transistor 24 and the ground terminal.

An input signal I++ is connected between the output terminal of the output signal O and the base of the NPN bipolar transistor 25. An NMOS consisting of a series circuit of 30 and 31 NMOS inputs, respectively.
A logic section 22 is connected.

Further, an NMOS 23 is connected between the base of the NPN bipolar transistor 25 and the ground terminal, and its gate is connected to the output point of the CMOS logic circuit 21.

In the KONO circuit, the NMOS logic section 22 and NMOS 23 generate an output that is in opposite phase to the output of the CMOS logic circuit 2, and
The PN bipolar transistors 24 and 25 are operated in a push-pull manner.

Next, the operation of this circuit will be explained.

Now, input signal 1. ,I. If both of them are 1, the output signal O is in the O state.

From this state, at least one of the input signals L-Iz becomes O.
, at least one of the PMOS 28 and 27 becomes conductive and at least one of the NMOS 28 and 29 becomes non-conductive, so that the output point of the CMOS logic circuit 21, that is, the NP
The base potential of the N bipolar transistor 24 is PMO
Charged by at least one of S26 and S27, the power supply V
. It rises towards the potential of D. As a result, NPN bipolar transistor 24 becomes conductive.

On the other hand, in the NMOS logic section 22, the NMOS 30,
31 becomes non-conductive. Also, NMOS2
3 is conductive. As a result, the base potential of the NPN bipolar transistor 25 falls toward the ground potential, so the NPN bipolar transistor 25 becomes non-conductive. As a result, the potential of the output signal O rises rapidly, and VD
The built-in potential (buj
lt-1n potential) reaches a potential lowered by Vp and becomes a level.

On the other hand, from the state where at least one of the input signal inputs □r I2 is O, the input signal 1. , I2 are both 1, PMO326, 27 becomes non-conductive and N
Since MOS28 and 29 are conductive, CMOS logic circuit 2
The output point 1, that is, the base potential of the NPN bipolar transistor 25 falls toward the ground potential, and the NPN bipolar transistor 24 becomes non-conductive.

On the other hand, in this case, the NMOS consisting of NMOS30.31
Since the logic part 22 is conductive and the NMOS 23 is non-conductive, the base potential of the NPN bipolar transistor 25 is equal to the input signal 1. , NMOS30 from the Lebel potential of I2
．． The voltage starts rising toward the potential lowered by the threshold voltage of 31. As a result, NPN bipolar transistor 2
5 is conductive. Then, the potential of the output signal 0 decreases toward a potential 72 minutes higher than the ground potential, and becomes 0 level. The base potential of the NPN bipolar transistor 25 increases by - degrees, but decreases as the level of the output signal O decreases, and finally becomes the same potential as the 0 level of the output signal 0.

[Problems to be Solved by the Invention] In the conventional BiCMOS logic circuit described above, when the output terminal changes from the O level to the level, the base potential of the NPN bipolar transistor 24 becomes V as described above.
. Since the voltage rises to D-VF, the NPN bipolar transistor 24 becomes sufficiently conductive, and the potential of the output terminal can be charged at high speed. However, when the output terminal changes from level 0 to level 0, the base potential of the NPN bipolar transistor 25 reaches a level lower than the level of the input signals II and I2 by the threshold voltage of the NMOS, as described above. Therefore, when the input terminal is connected to the output of another B1CMOS logic circuit, the base potential of the NPN bipolar transistor 25 is VDD-VF-VTN (however, V Tsit N M
OS 17) It only rises to L threshold voltage).

Such a decrease in the charging ability of the transistor 25 becomes more noticeable when the voltage of the power supply VDD is low. Therefore, as shown by curve A in FIG.
The average delay time Tpd of the logic circuit is the power supply V. It exhibits a characteristic that increases rapidly at about 3V.

Therefore, although this conventional BiCMOS logic circuit operates at high speed when the power supply voltage VDD is 5V, which is the conventional standard voltage, the operation speed suddenly deteriorates when the power supply voltage is about 3V. For this reason, if the power supply voltage is lowered due to the miniaturization of elements, the advantage of BICMOS logic circuits over CMOS logic circuits, which is that they can drive large load capacities at high speed, will be lost, and the next standard power supply will be At 3.3V, which is regarded as a voltage, there is a problem that the superiority with respect to CMOS cannot be maintained.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an iCMOS logic circuit that can operate at high speed even under a low power supply voltage.

Means for Solving the Problems] A BiCMOS logic circuit according to the present invention includes a CMOS logic circuit that performs a logical operation on an input signal, and a CMOS logic circuit whose collector is connected to a high potential side power supply terminal and whose emitter is connected to an output terminal. a first NPN bipolar transistor driven by the output of the logic circuit; a second NPN bipolar transistor whose collector is connected to the output terminal and whose emitter is connected to the low potential side power supply terminal; An N-channel MOS logic section connected between the base of the second NPN bipolar transistor and whose configuration and input signal are the same as the N-channel O8FET constituting the CMOS logic circuit;
a P-channel MOSFET connected in parallel with the S logic section and inputting the output of the CMOS logic circuit to its gate; and a P-channel MOSFET connected between the base of the second NPN bipolar transistor and the low potential side power supply terminal and the CMOS logic circuit. The first N-channel O8FET inputs the output of
It is characterized by having the following.

[Function] According to the present invention, when the N-channel O8FET constituting the CMOS logic circuit becomes conductive and the output of the CMOS logic circuit falls, the base of the second NPN bipolar transistor connects with the N-channel MOS logic section. , and the P-channel O8FETs connected in parallel to this are charged. Therefore, the base potential of the second NPN bipolar transistor is charged to a higher level than in the conventional circuit. Therefore, even under low power supply voltage, it is possible to operate at high speeds.

[Example code] The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a two-manpower NAND logic BiCMOS logic circuit suitable for low power supply voltage operation according to a first embodiment of the present invention.

The CMOS logic circuit 1 is a NAND of input signals It and Iz.
A parallel circuit of PMOS6 and 7 that outputs logic,
A series circuit of NMOS8 and NMOS9 is connected in series between the power supply VOO terminal and the ground terminal, and input signal 11 is input to the gates of PMOS8 and NMOS8,
Input the input signal I2 to the gates of P7 and NMOS9, and
The connection point between the drain of MOS 6.7 and the drain of NMO 58 is used as an output point.

The output point of this CMOS logic circuit 1 is connected to the base of an NPN bipolar transistor 4. The collector of the NPN bipolar transistor 4 is connected to the power supply V. It is connected to the D terminal, and its emitter is connected to the output terminal of the output signal O. Furthermore, an NPN bipolar transistor 5 is connected between the emitter of the NPN bipolar transistor 4 and the ground terminal.

Between the output terminal and the base of the NPN bipolar transistor 5, an NMOS logic g2 consisting of NMOSI0 and NMOSI11 and a PMO 312 are connected in parallel. N
MOS10 and 11 have input signals If and I2 at their gates, respectively.
is entered. Further, the gate of the PMOS 12 is connected to the base of the NPN bipolar transistor 4. Further, an NMOS 3 is connected between the base of the NPN bipolar transistor 5 and the ground terminal. The gate of this NMOS 3 is connected to the base of an NPN bipolar transistor 4.

In addition, NMOS logic section logic side 2O33 is a two-man power AN
It constitutes D logic. Therefore, the NPN bipolar transistor 4 whose base is connected to the output point of the CMOS logic circuit 1 and the NPN bipolar transistor 5 whose base is connected to the output point of the partial circuit consisting of the NMOS logic section logic horizontal 2 MOS 3 perform push-pull operation. conduct. PMOS
12 is provided to enhance the charging ability when charging the base potential of the NPN bipolar transistor 5 to the potential of van.

The operation of this circuit will be explained below with reference to FIG.

When the input signals Il and ■2 are both 1, the PMOS
Since 6 and 7 are non-conductive and NMOS 8 and 9 are conductive, C
The output point of the MO3 logic circuit 1 is at the O level, the drain of the NMOS3 is at the level, and the NPN bipolar transistors 4.5 are rendered non-conductive and conductive, respectively. Therefore, the output signal O becomes O level. From this state, input signal construction □r
When at least one of I2 changes to O, PMOS6
Since at least one of the NMOS transistors 8 and 9 is conductive and at least one of the NMOS transistors 8 and 9 is nonconductive, the output point of the CMOS logic circuit 1, that is, the base of the NPN bipolar transistor 4,
The potential of the gate of PMO312 and the gate of NM033 is from 0 level to power supply V. It rises towards the potential of D. On the other hand, at this time, the NMOS logic section has logic horizontal 2 and NMOS1
Since at least one of NPN bipolar transistors 0 and 1l(7) becomes non-conductive, the base potential of the NPN bipolar transistor 5 decreases toward the ground potential. Therefore, NPN
Bipolar transistor 4 becomes conductive, NPN bipolar transistor 5 becomes non-conductive, and the potential of the output terminal becomes N.
It rises toward V oo-V p and outputs a level.

On the other hand, input signal 11. At least one of I2 is 0
When the input signal 11=I2 both changes to 1 from the state of NPN bipolar transistor 4 and NM
o83 becomes non-conductive. On the other hand, in this case, NMOSI
Since both transistors 0 and 11 become conductive, the base potential of the NPN bipolar transistor 5 begins to rise. Also, CMO
As the potential at the output point of S logic circuit 1 decreases, NMo8
3 changes to a non-conductive state and 2MOS12 changes to a conductive state, so the base of the NPN bipolar transistor 5 is charged by both the NMOS logic part 3 and 2MOS12, and the base potential rapidly moves toward the power supply Voo-Vp. can be raised. As a result, the NPN bipolar transistor 5 becomes conductive, and the potential of the output terminal O finally decreases from the ground potential to a voltage higher than Vp, reaching the 0 level.

As explained above, in this embodiment, the input signals I,
, I2 change, the base potential of the NPN bipolar transistor can be charged to a higher potential than the conventional circuit shown in FIG. 5, so it can operate at high speed even with a low power supply voltage. is possible.

By setting the threshold voltage VTP of the 2MOS 12 to about Ov, it is also possible to increase the charging speed to the base of the NPN bipolar transistor 5 through the 2MOS 12. Even if the threshold voltage of the 2MOS12 is about OV, the leakage current when the output terminal is at the level is that the source of the PMoS12 is V
At oo-v2, since the gate is at vDD, a positive voltage equal to VF is applied between the gate and the source, so it becomes non-conductive and can be kept sufficiently small.

FIG. 2 is a graph showing the power supply voltage dependence of Tpd of the circuit of this example. As is clear from this figure, the operating power supply range of curve B showing the characteristics of this embodiment is expanded in the lower voltage direction by approximately VTN compared to curve A showing the characteristics of the conventional circuit.

FIG. 3 is a circuit diagram of a BiCMOS logic circuit according to a second embodiment of the present invention.

This embodiment differs from the first embodiment shown above in that N
The point is that the gate of Mo53 is connected not to the output point of CMOS logic circuit 1 but to the output terminal of output signal 0.

The other configurations are the same as the first embodiment shown in FIG.

In this embodiment, the loads to be driven by the CMOS logic circuit 1 are the base of the NPN bipolar transistor 4 and
Since only the gate of the MOS 12 is used, there is an advantage that the operation of the CMOS logic circuit 1 becomes faster than that of the first embodiment, and therefore the operation of the entire circuit can also become faster. Note that, as in the first embodiment, it is more effective if the threshold voltage of the 2MOS 12 is set to approximately O-V.

FIG. 4 is a circuit diagram of a BfCMOS logic circuit according to a third embodiment of the present invention.

In this embodiment) PMOS6a, 7a and NMOS
A first CMOS logic circuit 1a consisting of 8a and 9a, and P
It has a second CMOS circuit 1b consisting of MOSEib, 7b and NMOS 8b, 9b. These logic circuits 1a and lb constitute the same two-man NAND circuit.

The difference in configuration between this embodiment and the first embodiment described above is that in the first embodiment, the CMOS logic circuit 1 includes an NPN bipolar transistor 9, an NMOSIO and a PMOS
11, but in this example, the first CMO
The S logic circuit 1a is provided exclusively for driving the base of the NPN bipolar transistor 4, and the second CMOS logic circuit 1b is provided exclusively for driving the gates of the NMo83 and PMOS12. Other configurations and operations are the same as those of the first embodiment shown in FIG.

In this embodiment, the output load capacitance of the first CMOS logic circuit 1a is only the base capacitance of the NPN bipolar transistor 4, and the output load capacitance of the second CMOS logic circuit 1b is also only the gate capacitance of the NMOS 3 and 2MOS 12. Therefore, it is possible to increase the speed of the CMOS logic circuits 1a and 1b, thereby increasing the speed of the entire circuit and expanding the margin in MO3 design.

Also in this embodiment, as in the previous embodiment, the speed can be further increased by setting the threshold voltage of the PMO 312 to about Ov.

In the above embodiment, a two-man NAND circuit has been described as an example, but it goes without saying that the present invention is similarly applicable to other logic circuits including NOR systems.

[Effects of the Invention] As explained above, according to the present invention, the base of the second NPN bipolar transistor is connected to the N-channel MOS logic section and the P-channel MOSFET connected in parallel thereto.
Since charging is performed at both sides, it is possible to charge the base potential of the second NPN bipolar transistor to a higher level than in the conventional circuit. For this reason, 3.
BiCMO operates at high speed even with a power supply voltage as low as 3V
An S circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a BiCMOS logic circuit according to a first embodiment of the present invention, FIG. 2 is a graph showing the power supply voltage dependence of delay time in the same circuit, and FIG. 3 is a circuit diagram of a BiCMOS logic circuit according to a second embodiment of the present invention. FIG. 4 is a circuit diagram of a BiCMOS logic circuit according to the third embodiment of the present invention, and FIG. 5 is a circuit diagram of a conventional BiCMOS logic circuit. 1.21; CMOS logic circuit, 1a; first CMOS logic circuit, 1b; second CMOS logic circuit, 2.22; N
MOS logic section, 3, 8.8a, 8b. 9.9a, 9b, 10, 11, 23. 28-31; N-channel MOSFETz 6, 6a, 8b, L7a, 7b
, 12+ 26z 27; P channel MO3FET
, 4, 5. 24, 25; NPN bipolar transistor

Claims (3)

[Claims] (1) A CMOS logic circuit that performs a logical operation on an input signal, and a first NPN bipolar transistor whose collector is connected to a high potential side power supply terminal and whose emitter is connected to an output terminal and is driven by the output of the CMOS logic circuit. , a second NPN bipolar transistor whose collector is connected to the output terminal and whose emitter is connected to the low potential power supply terminal; and a second NPN bipolar transistor connected between the output terminal and the base of the second NPN bipolar transistor. An N-channel MOS logic section whose configuration and input signals are the same as the N-channel MOSFETs constituting the CMOS logic circuit, and the CMOS logic section connected in parallel with this N-channel MOS logic section.
P channel M that inputs the output of the MOS logic circuit to the gate
OSFET, a first NPN transistor connected between the base of the second NPN bipolar transistor and the low potential side power supply terminal, and inputting the output of the CMOS logic circuit to the base.
Bi characterized in that it has a channel MOSFET.
CMOS logic circuit. (2) A first CMOS logic circuit that performs a logical operation on an input signal, a second CMOS logic circuit that has the same configuration as the first CMOS logic circuit and performs a logical operation on the input signal, and a collector whose collector is a high potential side power supply terminal. a first NPN bipolar transistor whose emitter is connected to the output terminal and is driven by the output of the first CMOS logic circuit; whose collector is connected to the output terminal and whose emitter is connected to the low potential side power supply terminal; a second NPN bipolar transistor connected to the output terminal and the second NPN bipolar transistor;
N, which is connected between the base of the bipolar transistor and whose configuration and input signal constitute the CMOS logic circuit.
an N-channel MOS logic section that is the same as the channel MOSFET, a P-channel MOSFET that is connected in parallel with the N-channel MOS logic section and inputs the output of the second CMOS logic circuit to its gate, and the second NPN bipolar transistor. A BiCMOS logic circuit comprising: a first N-channel MOSFET connected between a base and the low potential side power supply terminal and inputting the output of the second CMOS logic circuit to its gate. (3) In place of the first N-channel MOSFET, a second N-channel MOSFET is connected between the base of the second NPN bipolar transistor and the low-potential side power supply terminal, and whose base is connected to the output terminal. BiCMOS according to claim 1 or 2, characterized in that a MOSFET is provided.
logic circuit.