JPH04107928U - Digital processing device for analog signals - Google Patents

Abstract

(57) [Summary] [Purpose] The present invention is an analog signal digital processing device that performs digital conversion of an analog signal or analog conversion of a digital signal. The purpose is to reduce the number of samples without [Configuration] Sampling clock CK _sc with a period corresponding to the absolute value of the difference between the digital data of the current sampling latched in the latch circuit 22 and the digital data of the previous sampling delayed and held in the delay circuit 27 is generated as an address and a clock. By generating the signal from the section 23, the signal is sampled in a short period when the signal changes are large, and is sampled in a long period when the signal changes little, and is written into the data memory 25.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention can be used, for example, when converting audio signals into digital format for recording and playback. The present invention relates to a digital processing device for analog signals.

0002

[Conventional technology]

Figure 7 shows a conventional digital recording circuit for audio signals. The audio signal S is first converted into a digital signal by the A/D converter 11. is latched by the latch circuit 12, and written and recorded in the data memory 13.

0003 Here, a clock for latching the digitized signal to the latch circuit 12 is used. clock pulse CK, and write instruction signal WR for the data memory 13 and its writing. All addresses are obtained by the address and clock generation section 14, This address and the sampling counter of the audio signal S by the clock generator 14 The timing is always set to a constant period regardless of fluctuations in the audio signal.

0004 Figure 8 shows a conventional playback circuit for digitized audio signals. The digital data recorded in the memory 13 is sequentially read out through the latch circuits 15a and 15b. is output, converted into an analog audio signal S by the D/A converter 16, and output. be done.

[0005] Here, the digital data latch clock for the latch circuits 15a and 15b is read instruction signal CS to the data memory 13 and its readout Both addresses are obtained by the same address and clock generation section 14 as described above. The readout of digital data by this address and clock generation unit 14 The timing is also always set to a constant cycle regardless of fluctuations in the digital data.

FIG. 9 shows a conventional sampling state of the audio signal S. In the figure, P is the sampling point of the audio signal S, and conventionally, as shown by range A, the amount of change in the audio signal S is The sampling periods t ₁ and t ₂ are set to a constant frequency 1/f _sc , both when the variation is large and when the variation is small as shown in range B.

[0007]

[Problem that the idea aims to solve]

However, with the above-mentioned conventional digital processing device, for example, the digitized sample Even when there is no change in the audio signal S, there is always a constant Since all samples are sampled at regular intervals, the number of samples is very large and cannot be recorded in advance. There are drawbacks such as the need for a data memory 13 with a large storage capacity.

[0008] The present invention was developed in view of the above-mentioned problems. Reduce the number of samples without sampling at regular intervals The purpose is to provide a digital processing device for analog signals that enables .

[0009]

[Means to solve the problem]

That is, the analog signal digital processing device according to the present invention is Something that converts analog signals to digital or converts digital signals to analog. in, data difference calculation means for calculating the difference between continuous digital data; A signal generator that generates a timing signal based on the difference between the above continuous digital data. means of living, means for inputting or outputting a digital signal based on the timing signal; , It is configured with the following.

0010

[Effect]

In other words, the larger the amount of change in the sampled data, the greater the sampling period. The smaller the amount of change in the sampled data, the shorter the sampled data becomes. By setting a long ring period, the number of samples can be kept to the minimum necessary. can.

[0011]

【Example】

An embodiment of the present invention will be described below with reference to the drawings.

0012 Figure 1 shows the configuration of a recording circuit in an analog signal digital processing device. , in the figure, 21 is an A/D converter, 22 is a latch circuit, and 23 is an address and 24 is a delay circuit, and 25 is a data memory.

[0013] The A/D converter 21 converts the audio signal S input as an analog signal into a digital signal. The digital signal from this A/D converter 21 is converted into a signal, and the digital signal from this A/D converter 21 is and the latch circuit 22 based on the clock signal CK from the clock generator 23. and the first digital signal input terminal of the address and clock generation section 23 given to child A'm.

Further, the digital signal latched by the latch circuit 22 is delayed by a delay circuit 24 based on the inverted clock signal CK from the address and clock generation section 23, and the digital signal latched by the address and clock generation section 23 is delayed by the delay circuit 24. It is written into the data memory 25 in response to the write instruction signal WR corresponding to _sc . The digital signal delayed by the delay circuit 24 is applied to the second digital signal input terminal B'm of the address and clock generation section 23.

[0015] The address and clock generation section 23 generates digital data at the current sampling time that is applied to the first digital signal input terminal A'm and digital data at the previous sampling time that is applied to the second digital signal input terminal B'm. It generates the sampling clock C K _sc for the latch circuit 22 and the delay circuit 24 at a cycle corresponding to the absolute value of the difference with the data, and also provides the write instruction signal WR and the write address to the data memory 25. In other words, When the level difference between the sampling data is large, a short-cycle sampling clock CK _sc is generated, and when the level difference between the sampling data is small, a long-cycle sampling clock CK _sc is generated.

[0016] Figure 2 shows the configuration of a reproducing circuit in an analog signal digital processing device. In the same figure, 26 is a latch circuit, 27 is a delay circuit, and 28 is a D/A converter. It is 28.

The latch circuit 26 latches the digital data of the audio signal S read out from the data memory 25 based on the sampling clock CK _sc from the address and clock generator 23 . The digital data is applied to the first digital signal input terminal A'm of the address and clock generation section 23, and is delayed by the delay circuit 27 based on the address and the inverted clock signal CK from the clock generation section 23. The signal is converted into an analog signal through the A converter 28.

[0018] The digital data delayed by the delay circuit 27 is sent to the address and the second digital signal input terminal B'm of the clock generating section 23.

The address and clock generation section 23 has a configuration similar to that of the recording circuit shown in FIG. The read sampling clock CK _{sc for the latch circuit 26 and the delay circuit 27 is generated at a period corresponding to the absolute value of the difference from the digital data at the time of previous read given to the signal input terminal B'm, and the read sampling clock CK sc} is generated for the data memory 25. In other words, when the level difference of the digital data to be read is large, a short-cycle read sampling clock CK _sc is generated; If it is small, a long period read sampling clock CK _sc is generated.

That is, the digital data recorded in the data memory 25 is read out in response to the read sampling clock CK _sc having the same period as that at the time of sampling recording, and is restored as the same analog audio signal S as before sampling.

FIG. 3 shows the internal configuration of the address and clock generation section 23 in the recording circuit and reproduction circuit. For example, in the recording circuit, the first digital signal input terminal A'm and the second digital signal input terminal B' The 8-bit digital signals applied to m at the current and previous sampling times are latched by latch circuits 31a and 31b, respectively, in accordance with the sampling clock CK _sc .

[0022] Digital data latched in one latch circuit 31a at the time of current sampling and the digital data at the previous sampling time latched in the other latch circuit 31b. The data is given to the comparator 32 and compared to see which one is larger. If the previous data B is larger than the previous data B, a signal “1” is output; If the previous data B is smaller than A, a signal "0" is output.

[0023] Also, the current data latched in one of the latch circuits 31a and the other The previous data latched in the latch circuit 31b is each bit A0 to A7. , B0 to B7 through one terminal of the exclusive OR gate EOR to the adder 3. 3a, 33b.

[0024] Here, the exclusive values corresponding to each bit A0 to A7 of the current data are The output signal from the comparator 32 is given to the other terminal of the agate EOR, and , an exclusive OR gate corresponding to each bit B0 to B7 of the previous data above. The inverted output signal from the comparator 32 is applied to the other terminal of EOR.

[0025] In other words, the adders 33a and 33b contain the digital data from the previous sampling. 8-bit data corresponding to the absolute value of the difference between the digital data and the digital data at the time of current sampling. The data S0 to S7 are obtained, and the difference data S4 corresponding to the upper 4 bits is ~S7 are each inverted through an inverter INV and are connected to 8 parallel AND gates AN It is given to one terminal of the odd gate in D. This 8 parallel AND gate AND One terminal of each even-numbered gate in the adder 34 has addition output data S0 ~S3 is given.

[0026] On the other hand, the output data from the above 8 parallel AND gates is 2 gates each. The clock signal from the clock generator 35 is selected via the OR gate OR. is latched into the data terminals D0 to D3 of the latch circuit 36 based on the pulse CK1. Ru. Then, the 4-bit data from the output terminals O0 to O3 in this latch circuit 36 is The data is applied to the NOR gate NOR, and the addend is applied to the adder 34. It is given as calculation data A0 to A3.

[0027] Here, the output data from the NOR gate NOR is the above 8 parallel AND gate AN is applied to each other terminal of the odd-numbered gate in D, and is passed through the inverter INV. is inverted and applied to each other terminal of the even gate in the 8 parallel AND gates. It will be done. Further, as the addition reference data B0 to B3 for the adder 34, "0111" is given to each.

[0028] In other words, in the 8 parallel AND gates, the output data of the NOR gate NOR is “1”. ”, the difference data S4 to S7 from the adder 33b are transferred to the latch circuit 3. 6, and when the output data from the NOR gate is “0”, It supplies the addition output data S0 to S3 from the adder 34 to the latch circuit 36. When the output data of the NOR gate NOR is “1”, it is latched to the latch circuit 36. The checked difference data S4 to S7 are obtained when the output data of the NOR gate NOR is “0”. In some cases, it is counted down sequentially through an adder 34.

Then, when the 4-bit data latched in the latch circuit 36 becomes "000 0", that is, when the output data of the NOR gate becomes "1", the clock pulse from the clock generator 35 CK1 is outputted as a sampling clock _CKsc through an AND gate AND1, and a clock pulse CK2 is applied to an address counter 37 through an AND gate AND2, thereby outputting a write address.

FIG. 4 is a timing chart showing the operating states of each part of the circuit associated with the data write operation of the recording circuit. First, in the initial state, the 4-bit data of the latch circuit 36 in the address and clock generation section 23 is "0000". ”, and the output data of the NOR gate NOR is “1”, so the clock panel CK1 from the clock generator 35 is output as is as the sampling clock _CKsc .

Then, the latch circuit 22 latches the first digital data D1 from the A/D converter 21 resulting from the first sampling, and the first digital data D1 latched in the latch circuit 22 is , is applied to the delay circuit 24 in synchronization with the fall of the sampling clock CK _sc from the address and clock generation section 23 .

[0032] Then, the next sampling clock CK is output from the address and clock generation section 23. _sc is given, the latch circuit 22 receives the second digital signal associated with the second sampling. The file data D2 is latched and is also delayed and held in the delay circuit 24. The first digital data D1 is written into the data memory 25.

[0033] At this time, the second digital signal input terminal B'm of the address and clock generation section 23 The above first digital data D1 is given as the previous sampling data, and In addition, the second digital data D2 is currently supported at the first digital signal input terminal A'm. The corresponding latch circuits 31b and 31a are given as sampling data. This allows the first digital signal to be latched from the adders 33a and 33b. Corresponds to the absolute value of the difference between the digital data D1 and the second digital data D2 |D1 −D2 | The difference data S4 to S7 are obtained, and the inverted data is sent to the 8-parallel AND gate A. It is applied to the latch circuit 36 through the odd numbered gates at ND.

Then, the output data from the NOR gate NOR is inverted to "0", and the differential data S4 to S7 given to the latch circuit 36 are sequentially down-counted through the adder 34, and the rising edge of the sampling clock CK _sc In synchronization with the fall, the second digital data D2 latched in the latch circuit 22 is applied to the delay circuit 24.

When the latch data of the latch circuit 36 that is counted down through the adder 34 becomes "0000", the output data of the NOR gate NOR is inverted to "1", and in response to the clock pulse CK1 from the clock generator 35, the output data of the NOR gate NOR is inverted to "1". The next sampling clock CK _sc is output.

[0036] Then, the latch circuit 22 receives the signal from the A/D converter 21 for the third sampling. The accompanying third digital data D3 is latched and is also delayed by the delay circuit 24. The deferred second digital data D2 is written into the data memory 25.

[0037] At this time, the second digital signal input terminal B'm of the address and clock generation section 23 The second digital data D2 from the delay circuit 24 is the same as the previous sampling data. In addition, the first digital signal input terminal A'm is provided with the latch circuit described above. The third digital data D3 from path 22 is given as sampling data this time. , are latched by the corresponding latch circuits 31b and 31a, respectively. Then, the second digital data D2 and the third digital data are outputted from the adders 33a and 33b. The difference data S4 to S7 corresponding to the absolute value of the difference with the data D3 |D2 −D3 | The inverted data is passed through the odd gates in the 8 parallel AND gates. The signal is applied to the latch circuit 36.

Then, in synchronization with the fall of the sampling clock _CKsc , the third digital data D3 latched in the latch circuit 22 is applied to the delay circuit 24, and then the output data from the NOR gate NOR becomes "0". '', and the differential data S4 to S7 given to the latch circuit 36 are sequentially down-counted through the adder 34.

When the latch data of the latch circuit 36, which is down-counted through the adder 34, becomes “0000”, the output data of the NOR gate NOR is inverted to “1”, and in response to the clock pulse CK1 from the clock generator 35, the next A sampling clock CK _sc is output.

[0040] Then, the latch circuit 22 receives the signal from the A/D converter 21 for the fourth sampling. The accompanying fourth digital data D4 is latched and is also delayed by the delay circuit 24. The deferred third digital data D3 is written into the data memory 25.

[0041] At this time, the second digital signal input terminal B'm of the address and clock generation section 23 The third digital data D3 from the delay circuit 24 is the same as the previous sampling data. In addition, the first digital signal input terminal A'm is provided with the latch circuit described above. The fourth digital data D4 from path 22 is given as sampling data this time. , are latched by the corresponding latch circuits 31b and 31a, respectively. Then, the third digital data D3 and the fourth digital data are output from the adders 33a and 33b. The difference data S4 to S7 corresponding to the absolute value of the difference with the data D4 |D3 −D4 | The inverted data is passed through the odd gates in the 8 parallel AND gates. The signal is applied to the latch circuit 36.

Then, in synchronization with the fall of the sampling clock _CKsc , the fourth digital data D4 latched in the latch circuit 22 is given to the delay circuit 24, and then the output data from the NOR gate NOR becomes "0". '', and the differential data S4 to S7 given to the latch circuit 36 are sequentially down-counted through the adder 34.

When the latch data of the latch circuit 36 that is down-counted through the adder 34 becomes “0000”, the output data of the NOR gate NOR is inverted to “1”, and the next clock pulse CK1 from the clock generator 35 is output. A sampling clock CK _sc is output.

[0044] Then, the latch circuit 22 receives the signal from the A/D converter 21 at the fifth sampling. The accompanying fifth digital data D5 is latched and is also delayed by the delay circuit 24. The deferred fourth digital data D4 is written into the data memory 25.

FIG. 5 shows the sampling state of the audio signal S in the recording circuit. That is, in the recording circuit, the sampling clock CK _sc with a period corresponding to the change in the sampling data is input by the address and clock generation unit 23. Since the digital conversion data of the audio signal S that is generated and latched sampled is recorded in the data memory 25, as shown in range A, a short sampling period _t1 is set in a state where the signal changes are large to achieve high resolution. In addition, as shown in range B, when there are few signal changes, a long sampling period _t2 can be set to eliminate unnecessary sampling processing, and sampling processing can be performed by setting the necessary resolution when necessary. can be done.

On the other hand, in the reproducing circuit shown in FIG. 2, even when reproducing digital data recorded in the data memory 25, the currently read digital data latched in the latch circuit 26 and the digital data delayed and held in the delay circuit 27 are Since the read sampling clock CK _sc with a period corresponding to the absolute value of the difference from the previously read digital data is set by the address and clock generator 23 similar to the above, the digital data recorded in the data memory 25 is The data is read out at the same timing as the writing sampling time, and is reproduced through the D/A converter 28.

Therefore, according to the analog signal digital processing device having the above configuration, the larger the amount of change in the audio signal S, the shorter the period of the sampling clock CK _sc is set, and the smaller the amount of change in the audio signal S. Indeed, by setting the period of the sampling clock CK _sc to be long, the number of digitized samples can be suppressed to the necessary minimum.

[0048] In addition, in the above embodiment, as shown in FIGS. 1 and 2, the digital signal of the analog signal is Although the recording circuit and playback circuit in the file processing device were configured separately, they can be integrated into an integrated circuit. It may be configured as follows.

[0049] FIG. 6 shows a recording/reproducing circuit in an analog signal digital processing device. In digital data recording mode, gates G1 and G2 must be set to on. A recording circuit similar to that shown in FIG. 1 above is obtained, and the digital data playback mode is In this case, by setting gates G3 and G4 on, the same playback as in FIG. A circuit will be obtained.

[0050]

[Effect of the idea]

As described above, according to the present invention, Something that converts analog signals to digital or converts digital signals to analog. in, data difference calculation means for calculating the difference between continuous digital data; A signal generator that generates a timing signal based on the difference between the above continuous digital data. means of living, means for inputting or outputting a digital signal based on the timing signal; , For example, it is possible to maintain a constant frequency between large and small signal changes. This makes it possible to reduce the number of samples without sampling at each period.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a recording circuit in an analog signal digital processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a reproduction circuit in an analog signal digital processing device according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing the internal configuration of an address and clock generation section in the recording circuit and reproduction circuit.

FIG. 4 is a timing chart showing the operating state of each part of the circuit associated with the data write operation of the recording circuit.

FIG. 5 is a diagram showing the sampling state of the audio signal S in the recording circuit.

FIG. 6 is a block diagram showing the configuration of a recording/reproducing circuit in the analog signal digital processing device.

FIG. 7 is a block diagram showing the configuration of a conventional digital recording circuit for audio signals.

FIG. 8 is a block diagram showing the configuration of a conventional reproduction circuit for digitized audio signals.

FIG. 9 is a diagram showing the sampling state of the audio signal S in the conventional digital recording circuit.

[Explanation of symbols]

21... A/D conversion section, 22, 26, 31a, 31b, 3
6...Latch circuit, 23...Address and clock generation section,
24, 27...Delay circuit, 25...Data memory, 28
...D/A conversion section, 32...Comparison section, 33a, 33b, 34
...adder, 35...clock generator, 37...address counter.

Claims (1)

[Scope of utility model registration request] Claim 1. An analog signal digital processing device that performs digital conversion of an analog signal or analog conversion of a digital signal, comprising: data difference calculation means for calculating a difference between consecutive digital data; 1. A digital processing device for analog signals, comprising: signal generating means for generating a timing signal; and means for inputting or outputting a digital signal based on the timing signal.