JPH04107864A - Power semiconductor device - Google Patents

Abstract

PURPOSE:To remove the malfunction by a parasitic thyristor such as an IGBT while making it simple voltage control similar to the IGBT by forming n-emitter layers alternately between p-base layers so as to form main current paths, and forming gate electrodes through gate insulating films at the surfaces between other p-base layers so as to control the depletion layers of the main current paths. CONSTITUTION:When a gate electrode 8 is biased to positive for a electrode 6, an n-type inversion layer is formed at the surface region of a second p-base layer 4. Hereby, a diode is formed by the course of a p-emitter layer 2 an n-base layer - an n-type inversion layer - an n-emitter layer 5, and a main current can be let flow along this course. When this current begins to flow, the main current comes to flow also to the diode consisting of the p-base layer - 2 the n-base layer 1 - the n-emitter layer 5 right below the n-emitter layer 5. And when the gate electrode 8 is biased to zero or negative for the cathode electrode 6, the n-type inversion layer vanishes, and the holes injected from the p-emitter layer 2 to the n-base layer are pulled out through the first p-base layer 3, and a depletion layer is formed again in the n-base layer, and it returns to the voltage checking condition.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention relates to an insulated gate type static induction thyristor (IG-S).
l thyristor) and insulated gate static induction transistor (
The present invention relates to power semiconductor devices such as IG-SIT).

B9 Summary of the Invention The present invention provides a P emitter layer on one main surface of an N base layer.
In a power semiconductor device in which a strip-shaped P base layer is provided on the main surface on the opposite side, an N emitter layer is formed every other P base layer to form a main current path, and a main current path is formed between the other P base layers. This structure uses a structure in which a gate electrode is formed through a gate insulating film to control the depletion layer of the main current path, thereby eliminating malfunctions caused by parasitic thyristors like in IGBTs while providing simple voltage control similar to IGBTs.

C3 Conventional technology In recent years, in the field of power semiconductors, improvements in the efficiency of applied equipment,
From the perspective of reducing noise, there is an increasing demand for devices that can handle higher frequencies. As is well known, electrostatic induction semiconductor devices such as SIT and Sl thyristors are
It has been recognized to have superior high frequency characteristics compared to other power devices, and has been used as the main switch element of high frequency inverters.

As another semiconductor device with excellent high frequency characteristics, vertical M
The drain layer of the O8-FET is changed from the n-type semiconductor layer to the P-type semiconductor layer, and holes are actively injected from this P-type semiconductor layer to reduce the on-resistance of the high-speed MOS-FET. gated bipolar transistor (IGB)
T) is widely used in the current capacity range of 15 to 400 A. As an example of this element, JP-A-56-150870
It is disclosed in the publication No.

D0 Problems to be Solved by the Invention Sl thyristors are attracting attention as devices that exhibit excellent performance in the field of high frequency applications among power semiconductor devices, but the peak value of the current drawn from the gate at turn-off is equal to the main current. Since they are almost the same (turn-off gain=1), there is a problem that the gate circuit becomes complicated and large-scale.

On the other hand, since IGBT is a voltage-controlled device,
This has the advantage that the control circuit is simpler than current control type devices such as Sl thyristors. However, I.G.
Since the BT element has a parasitic thyristor consisting of a P emitter, an n base, a P base, and an n emitter, if a large current is passed between the P emitter and the n emitter, the parasitic thyristor section will fire, causing the gate to fail. There was a problem in that it was impossible to shut off the main current (latch-up phenomenon).

An object of the present invention is to provide a power semiconductor device that eliminates malfunctions caused by parasitic thyristors like IGBTs while providing simple voltage control similar to IGBTs.

20 Means for Solving the Problems In order to achieve the above object, the present invention forms a P emitter layer of a P type semiconductor on one main surface of an n base layer of an n type semiconductor, and forms a P emitter layer of a P type semiconductor on the side opposite to the main surface. In a power semiconductor device in which a P base layer of a P type semiconductor is formed in a strip shape on the main surface of the P base layer, an n emitter layer is formed every other layer between adjacent layers, and the n emitter layer and one of the P base layers is short-circuited with a cathode electrode, a gate insulating film is formed on the surface of the n base layer sandwiched between the p base layers on which the n emitter layer is not formed, and at least the above p base layer is formed on the gate insulating film. It is characterized by a structure in which a gate electrode is formed directly over the other P base layer.

F8 action An n emitter layer is formed every other layer between the P base layers formed in a strip shape, and the depletion layer of the P base layer sandwiching this n emitter layer is controlled by voltage from an insulated gate to control the main current. conduct.

G. Example FIG. 1 is an element structure diagram showing an embodiment of the present invention.

A P emitter layer 2 is formed on one main surface of the n-base layer 1, and a plurality of strip-shaped P base layers 3 and 4 are formed on the other main surface. First P base layer 3 and second P base layer 4
are adjacent to each other, a wide side (width a) and a narrow side (width b) are formed alternately, and the width a of the wide side is 2XWd.
The narrower width is smaller than 2.times.Wd. Here, Wd is the width of the depletion layer formed by the internal electromotive force of the PN junction formed by the P base layer 3 and the N base layer 1.

An n emitter layer 5 is formed on the surface of the n base layer 1 in a region having a narrow width. This n emitter layer 5 is short-circuited with the inside of the first P base layer 3 by the cathode electrode 6, and the remaining surface portion of the first P base layer 3 and the surface of the second P base layer 4 are connected to the n emitter layer 5. The base layer 1 is covered with a gate insulating film 7. Further, a gate electrode 8 is formed directly above the second base layer 4, and an anode electrode 9 is formed on the surface of the P emitter layer 2.
is formed. 10 is a protective insulating film.

The operation of the device having the above structure will be described in detail below.

First, when no gate bias is applied, the relationship between the anode and cathode is b<2Wd, so the normal
Similar to the off-type Sl thyristor, voltage is blocked by a depletion layer extending from the P base layer 3.4 sandwiching the n emitter layer 5. Next, the gate electrode 8 is connected to the cathode electrode 6.
When biased positively, an n-type inversion layer is formed in the surface region of the second P base layer 4. As a result, a diode is formed along the path of P emitter layer 2 - n base layer 1 - n type inversion layer - n emitter layer 5, and a main current can flow along this path. When this current starts to flow, electrons are injected from the n-emitter layer 5 side into the n-base 1 region directly under the inversion layer and the n-emitter layer 5.
The main current also flows through the diode composed of the P base layer 2-n base layer 1-n emitter layer 5 directly below the emitter layer 5. Then, when the gate electrode 8 is set to zero or negative bias with respect to the cathode electrode 6, the above-mentioned n-type inversion layer disappears, and the holes injected from the P emitter layer 2 into the n base region are transferred to the first P base region. It is extracted through layer 3, and a depletion layer is again formed in the n-base region, returning to the voltage blocking state.

It is a voltage-controlled type like T, which makes it easy to control, and, like the normally φ-off type Sl thyristor, the switching operation is performed by the depletion layer formed in the n base region by the gate arranged in a strip shape. Low loss and high speed operation similar to thyristors are possible. Also, IG
Unlike a BT, the path from the P emitter layer 2 to the N base layer 1 to the N emitter layer 5 through which the main current flows has a diode structure, so there is no latch-up phenomenon caused by a parasitic thyristor like in an IGBT, and the on-voltage is lower than that in an IGBT. can be lowered.

FIG. 2 is a structural diagram showing another embodiment of the present invention. The difference between this figure and FIG. 1 is that the gate electrode 8A is connected to the first P base layer 3 and the second P base layer 4. Therefore, the device structure of this embodiment has a wide width a between the conventional IGBs. This is due to the fact that it is formed over the entire area.

In this embodiment, when a positive bias is applied to the gate electrode 8A, electrons are induced on the surface of the n-base layer 1 as well as on the second P-base layer 4, so that the interval a between the P-base layers is
It becomes possible to turn on even if it is narrower than 2XWd. That is, in this embodiment, the width a can be made narrower than that of the above-mentioned embodiment (FIG. 1), so that the area utilization rate of the substrate can be increased.

Furthermore, when a negative bias is applied to the insulated gate 8A, the surface layer of the n-base layer 1 immediately below it is inverted to the P type, so that higher voltage blocking (higher withstand voltage) can be achieved.

In the embodiments described above, the cathode electrode 6 is divided by the gate electrode protective insulating film 3, but the film thickness of the cathode electrode 6 can be increased to form an integral electrode connected to each other above the protective insulating film 3. I can do it.

In addition, in the embodiment, the P emitter layer 2 side is entirely formed of a P-type semiconductor layer, but the conventional SI thyristor or IGB
Similar to T, a structure in which a buffer layer with a higher concentration than the n base layer is provided between the n base layer 1 and the P emitter layer 2, and a shorting layer made of an n-type semiconductor in a part of the P emitter layer 2. Of course, by employing a patterned anode-emitter short circuit structure, it is possible to improve switching speed and reduce loss.

H8 Effects of the Invention As described above, according to the present invention, an n emitter layer is formed every other strip-shaped P base layer to form a main current path, and the insulation between the P base layers sandwiching this n emitter layer is Since the main current is controlled by controlling the depletion layer by gate control, the main current is controlled by voltage control, making gate control simple and easy. Also, since it does not have a parasitic thyristor like an IGBT, malfunctions due to latching phenomenon are prevented. It can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram showing one embodiment of the present invention, and FIG. 2 is a structural diagram of another embodiment. 1...n base layer, 2...emitter layer, 3.4...
- P base layer, 5... n emitter layer, 6... cathode electrode, 7... gate insulating film, 8... gate electrode,
9... Anode electrode, 10... Protective insulating film. Fig. 1 Structure diagram of the embodiment 9 Structural diagram of the anode electrode lO, protective insulating film, and other embodiments

Claims (1)

[Claims] (1) A P emitter layer of a P type semiconductor is formed on one main surface of an n base layer of an n type semiconductor, and a P base layer of a P type semiconductor is formed in a strip shape on the main surface opposite to the main surface. In the power semiconductor device, the P base layer has an n emitter layer formed between every other layer adjacent to each other, one of the n emitter layer and the P base layer is short-circuited with a cathode electrode, and the n A structure in which a gate insulating film is formed on the surface of the n-base layer sandwiched between the p-base layers on which no emitter layer is formed, and a gate electrode is formed on the gate insulating film, covering at least immediately above the other P-base layer. A power semiconductor device characterized by: