JPH04106945A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04106945A
JPH04106945A JP22483790A JP22483790A JPH04106945A JP H04106945 A JPH04106945 A JP H04106945A JP 22483790 A JP22483790 A JP 22483790A JP 22483790 A JP22483790 A JP 22483790A JP H04106945 A JPH04106945 A JP H04106945A
Authority
JP
Japan
Prior art keywords
electrode
oxide film
thin oxide
etching
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22483790A
Other languages
Japanese (ja)
Inventor
Satoshi Yoshida
聡 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP22483790A priority Critical patent/JPH04106945A/en
Publication of JPH04106945A publication Critical patent/JPH04106945A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to obtain a device with minimum characteristic variations and enhance the yield by installing an evaluation device, electrically evaluating the presence of a thin oxide film, and carrying out process control. CONSTITUTION:A first electrode 9 is formed as an evaluation device in the lower part of a semiconductor substrate 1. After the formation of a thin oxide film on the electrode 9, this oxide film is etched and processed. During etching removal of this oxide film, a thin oxide film 8, which can not be completely eliminated, is sandwiched and formed on the electrode 9 as an upper part electrode 10 whose area is smaller than that of the electrode 9. The application of this evaluation device makes it possible to detect the presence of the film 8 and accordingly carry out process control either during process or after the formation of products by applying constant voltage between the electrode 9 and the electrode 10 and measuring the current flowing between the electrode 9 and 10. This construction makes it possible to evaluate the presence of a thin oxide film, which is an etching remainder, obtain a device with minimum characteristic variations by controlling the etching process, and enhance the yield.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に係り、特に、半導体基板上に形
成された評価用素子を有する半導体装置の構造に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a semiconductor device having an evaluation element formed on a semiconductor substrate.

〔従来の技術〕[Conventional technology]

従来の半導体装置のうち特にMO3型半導体は、近年高
速化に伴い、LDD構造が多く採用されている。前記L
DD構造を有するMO3型半導体は、1つの特徴として
、ゲート電極側壁に、サイドウオールを有している。以
下に、前記サイドウオールを形成する製造工程を、第3
図(a)〜第3図(c)に基づき説明する。
Among conventional semiconductor devices, especially MO3 type semiconductors, LDD structures are often adopted as speeds have increased in recent years. Said L
One feature of the MO3 type semiconductor having the DD structure is that it has a sidewall on the sidewall of the gate electrode. Below, the manufacturing process for forming the sidewall will be explained in the third step.
This will be explained based on FIG. 3(a) to FIG. 3(c).

■第3図(a)は、MO3型半導体装置の製造工程断面
図であり、半導体基板1上に、ゲート酸化膜3、不純物
拡散層4、ゲート電極5が形成されている。なお、図中
2は素子分前膜である。
(2) FIG. 3(a) is a cross-sectional view of the manufacturing process of an MO3 type semiconductor device, in which a gate oxide film 3, an impurity diffusion layer 4, and a gate electrode 5 are formed on a semiconductor substrate 1. Note that 2 in the figure is a pre-element film.

■前記半導体基板1上に、酸化膜6を、第3図(b)の
様に形成する。
(2) An oxide film 6 is formed on the semiconductor substrate 1 as shown in FIG. 3(b).

■前記酸化膜6を、反応性イオンエツチング法により異
方性エツチングを行い、ゲート電極5の側壁に、サイド
ウオール7を形成する。
(2) The oxide film 6 is anisotropically etched using a reactive ion etching method to form a sidewall 7 on the sidewall of the gate electrode 5.

この際に、第3図(C)の様に、ゲート電極5及び不純
物拡散層4上に、前記反応性イオンエツチング条件のバ
ラツキによって、薄い酸化I!II8が残る場合がある
At this time, as shown in FIG. 3(C), due to variations in the reactive ion etching conditions, a thin oxide layer is formed on the gate electrode 5 and the impurity diffusion layer 4. II8 may remain.

しかしながら、前記の薄い酸化膜8が、次工程のイオン
打込工程の際に、イオンの透過膜となる場合、抵抗値等
がバラツク要因となる。したがって、バラツキの少ない
素子を得る為には、薄い酸化膜8の有無を管理する必要
がある。
However, when the thin oxide film 8 becomes an ion permeable film during the next ion implantation process, resistance values and the like become a factor of variation. Therefore, in order to obtain an element with little variation, it is necessary to control the presence or absence of the thin oxide film 8.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、従来の半導体装置においては、前記の薄い酸
化膜8の有無を管理する方法がなかった。
However, in conventional semiconductor devices, there was no method for controlling the presence or absence of the thin oxide film 8.

そこで、本発明は、この様な課題を解決しようとするも
ので、その目的とするところは、前記の薄い酸化#8の
有無を、電気的に評価し、工程管理を行うことにより、
特性バラツキの少ない素子を得るところにある。
Therefore, the present invention attempts to solve such problems, and its purpose is to electrically evaluate the presence or absence of the thin oxidation #8 and perform process control.
The goal is to obtain an element with less variation in characteristics.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、半導体基板上に、第1の電極と
して、導電体層を配置し、前記第1電極上に絶縁膜を形
成した後に、前記絶縁膜をエツチング処理し、さらに上
部に、第2電極として第1電極より面積の小さい導電体
層を配設した評価用素子を有し、前記評価用素子と同一
基板上にある半導体素子の工程管理を行える事を特徴と
する。
In the semiconductor device of the present invention, a conductive layer is disposed as a first electrode on a semiconductor substrate, an insulating film is formed on the first electrode, and then the insulating film is etched, and further on the upper part: The present invention is characterized in that it has an evaluation element in which a conductive layer having a smaller area than the first electrode is disposed as a second electrode, and that process control of a semiconductor element on the same substrate as the evaluation element can be performed.

〔実施例〕〔Example〕

以下本発明の実施例を、図面により詳細に説明を行う。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第1図は、本発明による評価用素子の構造断面図である
。半導体基板上1に、第1電極9を下部に形成する。前
記第1電極9上に、酸化膜を形成した後、前記酸化膜を
エツチング処理し、さらに前記酸化膜のエツチング除去
において、完全に除去されなかった薄い酸化膜8をはさ
み、上部電極として第1電極上に、前記第1電極より面
積の小さい第2電極10を形成する。
FIG. 1 is a structural sectional view of an evaluation element according to the present invention. A first electrode 9 is formed on the semiconductor substrate 1 at the bottom. After forming an oxide film on the first electrode 9, the oxide film is etched, and the thin oxide film 8 that was not completely removed during the etching removal of the oxide film is sandwiched between the thin oxide films 8 to form the upper electrode. A second electrode 10 having a smaller area than the first electrode is formed on the electrode.

前述の評価用素子を用いる事により前記の薄い酸化膜8
の有無を、前記第1電極9と第2電極10との間に一定
電圧を印加し、第1電極9と第2電極10との間を流れ
る電流を測定する事により、工程中でも製品形成後でも
管理する事ができる。
By using the above-mentioned evaluation element, the above-mentioned thin oxide film 8
By applying a constant voltage between the first electrode 9 and the second electrode 10 and measuring the current flowing between the first electrode 9 and the second electrode 10, the presence or absence of But it can be managed.

次に、本発明の評価用素子をLDD構造を有するMO3
型半導体装置に適応した場合について、第2図(a)〜
第2図(d)に基づき説明する。
Next, the evaluation element of the present invention was prepared using MO3 having an LDD structure.
When applied to a type semiconductor device, Fig. 2(a) to
This will be explained based on FIG. 2(d).

第2図(a)〜第2図(d)は、LDD構造を有するM
O3型トランジスタ12と、本発明による評価用素子1
1が同一半導体基板1上に形成されたものであり、LD
D構造の特徴の一つである、サイドウオール7を形成す
る製造工程の断面図を示したものである。
FIGS. 2(a) to 2(d) show M having an LDD structure.
O3 type transistor 12 and evaluation element 1 according to the present invention
1 is formed on the same semiconductor substrate 1, and the LD
This figure shows a cross-sectional view of the manufacturing process for forming the sidewall 7, which is one of the features of the D structure.

第2図(a)の様に、MO3型トランジスタ12は半導
体基板1上に形成された、ゲート酸化膜3、不純物拡散
層4、ゲート電極5により構成されている。なお、図中
2は素子分離膜である。前記半導体基板l上の評価用素
子11の部分に、ゲート電極5を形成する時と同様に、
多結晶シリコンを用い、素子分離膜2の上部に、下部電
極として第1電極9を形成する。
As shown in FIG. 2(a), the MO3 type transistor 12 is composed of a gate oxide film 3, an impurity diffusion layer 4, and a gate electrode 5 formed on a semiconductor substrate 1. Note that 2 in the figure is an element isolation film. In the same way as when forming the gate electrode 5 on the portion of the evaluation element 11 on the semiconductor substrate l,
A first electrode 9 is formed as a lower electrode on the top of the element isolation film 2 using polycrystalline silicon.

次に、第2図(b)の様に、高温気相成長による酸化膜
6を上部に約3000〜8000A形成する。
Next, as shown in FIG. 2(b), an oxide film 6 of approximately 3000 to 8000 Å is formed on the top by high temperature vapor phase growth.

さらに、前記酸化膜6を、反応性イオンエツチング法を
用い異方性エツチングする事により、ゲート電極5側壁
にサイドウオール7を形成する。
Further, by anisotropically etching the oxide film 6 using a reactive ion etching method, a sidewall 7 is formed on the side wall of the gate electrode 5.

ここで前記異方性エツチング量が不均一な為、酸化膜6
が薄い酸化膜8として半導体基板1上に残る場合がある
Here, since the amount of anisotropic etching is non-uniform, the oxide film 6
may remain on the semiconductor substrate 1 as a thin oxide film 8.

さらに、薄い酸化膜8上に、アルミニウム薄膜をパター
ンニングする事により、第1電極9上に、第1電極より
面積の小さな第2電極10を形成する0以上の工程によ
り、本発明の評価用素子の構造を得る事ができる。
Furthermore, by patterning a thin aluminum film on the thin oxide film 8, a second electrode 10 having a smaller area than the first electrode is formed on the first electrode 9. The structure of the element can be obtained.

前記評価用素子11を用いる事により、第1電極9と第
2電極10との間に一定電圧を印加し、第1電極9と第
2電極10との間に流れる電流を測定する事により、薄
い酸化膜8の有無が評価できる。
By using the evaluation element 11, a constant voltage is applied between the first electrode 9 and the second electrode 10, and the current flowing between the first electrode 9 and the second electrode 10 is measured. The presence or absence of the thin oxide film 8 can be evaluated.

前述の実施例は、薄い酸化膜8が、MO3型トランジス
タにおける、サイドウオール7形成時のエツチング残り
である場合について述べたが、それに代えて、酸化膜の
一部のみをドライエツチングもしくは、ウェットエツチ
ング処理を行う場合に残る酸化膜であるときの評価用素
子としても適用できる。
In the above embodiment, the thin oxide film 8 is the etching residue left after forming the sidewall 7 in an MO3 transistor. However, instead of this, only a part of the oxide film is dry-etched or wet-etched. It can also be applied as an element for evaluation when the oxide film remains after processing.

さらに、エツチング処理を行う酸化膜が、酸化膜以外の
絶縁膜である場合にも適用できる。
Furthermore, the present invention can also be applied when the oxide film to be etched is an insulating film other than an oxide film.

〔発明の効果〕〔Effect of the invention〕

以上述べた様に、上部電極と下部電極との間に薄い酸化
膜をはさんだ、本発明の評価用素子を使う事により、エ
ツチング残りである薄い酸化膜の有無を評価できる。さ
らに、前述のエツチング工程を管理する事により、特性
のバラツキが少ない半導体装置を得る事ができ、それに
よって高い歩留りの半導体装置を得る事ができる。
As described above, by using the evaluation element of the present invention in which a thin oxide film is sandwiched between the upper electrode and the lower electrode, the presence or absence of a thin oxide film remaining after etching can be evaluated. Furthermore, by controlling the etching process described above, it is possible to obtain a semiconductor device with less variation in characteristics, thereby making it possible to obtain a semiconductor device with a high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明による、評価用素子の構造断面図であ
る。 第2図(a)〜第2図(d)は、本発明の評価用素子を
、LDD構造を有するMO3撃トランジスタに適応した
一実施例の構造を示す製造断面図である。 第3図(a)〜第3[K(c)は、従来の半導体装置の
構造を示す製造断面図である。 1・・・半導体基板 2・・素子分M膜 3・・・ゲート酸化膜 4・・・不純物拡散層 5・・・ゲート電極 6・・・酸化膜 7・・・サイドウオール 8・・薄い酸化膜 9・・・第1電極 10・・・第2電極 11・・・評価用素子 12・・・MO3型トランジスタ 以  上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴木 喜三部 他1名菫1の 掌 21え
FIG. 1 is a structural sectional view of an evaluation element according to the present invention. FIGS. 2(a) to 2(d) are manufacturing cross-sectional views showing the structure of an example in which the evaluation element of the present invention is applied to an MO3 strike transistor having an LDD structure. FIGS. 3(a) to 3(c) are manufacturing cross-sectional views showing the structure of a conventional semiconductor device. 1...Semiconductor substrate 2...Element M film 3...Gate oxide film 4...Impurity diffusion layer 5...Gate electrode 6...Oxide film 7...Side wall 8...Thin oxide Membrane 9...First electrode 10...Second electrode 11...Evaluation element 12...MO3 type transistor or above Applicant: Seiko Epson Corporation Agent Patent attorney: Kizobe Suzuki and one other person Sumire 1 palm of the hand 21e

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に、第1の電極として導電体層を配置し
、前記第1電極上に、絶縁膜を形成した後に前記絶縁膜
をエッチング処理し、さらに上部に、第2電極として第
1電極より面積の小さい導電体層を配設した評価用素子
を有し、前記評価用素子と同一基板上にある半導体素子
の工程管理を行える事を特徴とする半導体装置。
A conductive layer is disposed as a first electrode on a semiconductor substrate, an insulating film is formed on the first electrode, and then the insulating film is etched, and a second electrode is formed on the semiconductor substrate from the first electrode. 1. A semiconductor device comprising an evaluation element provided with a conductive layer having a small area, and capable of performing process control of a semiconductor element on the same substrate as the evaluation element.
JP22483790A 1990-08-27 1990-08-27 Semiconductor device Pending JPH04106945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22483790A JPH04106945A (en) 1990-08-27 1990-08-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22483790A JPH04106945A (en) 1990-08-27 1990-08-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04106945A true JPH04106945A (en) 1992-04-08

Family

ID=16819956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22483790A Pending JPH04106945A (en) 1990-08-27 1990-08-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04106945A (en)

Similar Documents

Publication Publication Date Title
JPS6010773A (en) Method of forming 1-element fet-memory capacitor circuit
JPH05206451A (en) Mosfet and its manufacture
JPH07245291A (en) Method and apparatus for etching silicon substrate
JPS61222172A (en) Forming method for gate insulating film in mosfet
JPH04106945A (en) Semiconductor device
JPH04275436A (en) Soimos transistor
JPH10125864A (en) Manufacture of semiconductor device
KR100504177B1 (en) Semiconductor gas sensor and Method for manufacturing the same
JPH04226080A (en) Manufacture of thin film transistor
JPH01298758A (en) Manufacture of semiconductor device
KR970013189A (en) Device isolation method of semiconductor integrated circuit
JPH04302438A (en) Thin-film transistor
JPH02110934A (en) Formation of window for contact electrode
JPS63117468A (en) Manufacture of semiconductor device
JPH0464470B2 (en)
JPS58101456A (en) Semiconductor device
KR19980056109A (en) Gate electrode formation method of semiconductor device
JPH02278725A (en) Semiconductor device and manufacture thereof
JPH0729711A (en) Forming method of resistor
JPS6340322A (en) Manufacture of semiconductor device
JPH0918007A (en) Thin film transistor and manufacture thereof
JPS63276272A (en) Semiconductor device and manufacture thereof
JPH05110103A (en) Semiconductor device
JPS59117114A (en) Manufacture of semiconductor device
KR960002789A (en) Capacitor Manufacturing Method of Semiconductor Device