JPS63276272A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS63276272A
JPS63276272A JP11281387A JP11281387A JPS63276272A JP S63276272 A JPS63276272 A JP S63276272A JP 11281387 A JP11281387 A JP 11281387A JP 11281387 A JP11281387 A JP 11281387A JP S63276272 A JPS63276272 A JP S63276272A
Authority
JP
Japan
Prior art keywords
film
gate
oxide film
polycrystalline silicon
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11281387A
Other languages
Japanese (ja)
Inventor
Hidekazu Arima
有馬 英一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11281387A priority Critical patent/JPS63276272A/en
Publication of JPS63276272A publication Critical patent/JPS63276272A/en
Pending legal-status Critical Current

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  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To improve dielectric strength of an insulating film between first and second gate electrodes and to improve charge holding characteristics of the first gate electrode, by forming the insulating film thick on the edges or the first gate electrode. CONSTITUTION:A field oxide film 2 and a first gate oxide film 3 are formed on a silicon substrate 1 and then a first gate polycrystalline silicon film 4 is deposited thereon. A thin oxide film 5 is formed on the first polycrystalline silicon film 4 and, further, a silicon nitride film 6 is deposited thereon. An oxide film 7 is formed only on the side walls of the first gate polycrystalline silicon film by the thermal oxidation process. The silicon nitride film 6 and the thermal oxide film 5 are etched and a second gate insulating film 8 is deposited thereon. Subsequently, polycrystalline silicon, tungsten side or the like is deposited thereon for providing a second gate electrode 9.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置、特に、二重ゲート構造を持つ
不揮発性半導体記憶装置における第1の伝導層と第2の
伝導層との間にある第2ゲートの絶縁酸化膜の構造およ
び、その形成方法に関するものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, particularly a nonvolatile semiconductor memory device having a double gate structure, between a first conductive layer and a second conductive layer. The present invention relates to a structure of an insulating oxide film of a second gate and a method of forming the same.

(従来の技術) 第3図(a)、(b)、(CJ、(d)は、従来の製造
工程に従った二重ゲート構造を持つ不揮発性半導体記憶
装置の一例の各要部断面図である。図において、!はシ
リコン基板、2は、この基板!」二に形成された素子間
分離絶縁膜、3は第1ゲート酸化膜、4は、第1の伝導
層である多結晶シリコン膜(以F、第1ゲート電極とい
う)、8は第2ゲート酸化11Q、9は、第2の伝導層
である多結晶シリコン膜(以ド、第2ゲート電極という
)である。
(Prior Art) Figures 3 (a), (b), (CJ, and d) are sectional views of essential parts of an example of a nonvolatile semiconductor memory device having a double gate structure according to a conventional manufacturing process. In the figure, ! is a silicon substrate, 2 is this substrate!'' 2 is an element isolation insulating film formed on it, 3 is a first gate oxide film, and 4 is a polycrystalline silicon which is a first conductive layer. 8 is a second gate oxide 11Q, and 9 is a polycrystalline silicon film (hereinafter referred to as a second gate electrode) which is a second conductive layer.

以)”、第3図を用いて従来の製造方法を説明する。Hereinafter, the conventional manufacturing method will be explained using FIG.

まず、第3図(a)に示すように、シリコン基板1のフ
ィールド領域に、選択酸化法によりフィールド酸化膜2
を形成し、素子形成領域に熱酸化により第1ゲート酸化
[3を形成する。そして全面に多結晶シリコン1漠4を
成長させ、写真製版により第1ゲート電極を形成する。
First, as shown in FIG. 3(a), a field oxide film 2 is formed on the field region of the silicon substrate 1 by selective oxidation.
is formed, and a first gate oxide [3 is formed by thermal oxidation in the element formation region. Then, polycrystalline silicon 1 and 4 are grown over the entire surface, and a first gate electrode is formed by photolithography.

次に、第3図(b)に示すように第1ゲート電極である
多結晶シリコン膜4上に第2ゲート絶縁膜8(例えばシ
リコン酸化膜)を熱酸化法、化学的気相成長法を用いて
形成する。
Next, as shown in FIG. 3(b), a second gate insulating film 8 (for example, a silicon oxide film) is formed on the polycrystalline silicon film 4, which is the first gate electrode, by thermal oxidation or chemical vapor deposition. Form using.

ついで、第3図(c)に示すように、第2ゲート電極で
ある多結晶シリコン膜9を、第2ゲート酸化膜8上に、
化学気相成長法等により形成する。
Next, as shown in FIG. 3(c), a polycrystalline silicon film 9 serving as a second gate electrode is deposited on the second gate oxide film 8.
Formed by chemical vapor deposition or the like.

(発明が解決しようとする問題点) 従来のこの種の半導体装置の製造方法は、第3図(d)
に、(c)図の要部を拡大して示すように、多結晶シリ
コン4のエツジ上に第2ゲート酸化膜8が形成されてお
り、このエツジ上の絶縁膜の絶縁性が悪いため絶縁破壊
に至る電圧(以下、このような電圧を耐圧と呼ぶ)が低
く、第2ゲート電極9にある一定以上の電圧を印加する
と、第1ゲート電極4と第2ゲート電極9との間の絶縁
が不能となるという問題点があった。また第2ゲート電
Vi44中に電荷を溜めておくときの電荷の保持特性が
悪いという問題があった。
(Problems to be Solved by the Invention) The conventional manufacturing method for this type of semiconductor device is shown in FIG. 3(d).
As shown in the enlarged view of the main part of FIG. If the voltage leading to breakdown (hereinafter such a voltage is referred to as withstand voltage) is low and a certain voltage or higher is applied to the second gate electrode 9, the insulation between the first gate electrode 4 and the second gate electrode 9 will be reduced. There was a problem that it became impossible. Further, there is a problem in that the charge retention characteristics are poor when charges are stored in the second gate voltage Vi44.

この発明は、上記のような従来の製造方法の問題点を解
消するためになされたもので、第1ゲート電極と第2ゲ
ート電極間の絶縁膜耐圧向上と、第1ゲート電極中の電
荷の保持特性を改善することができる半導体装置と、そ
の製造方法を提供することを目的としている。
This invention was made to solve the problems of the conventional manufacturing method as described above, and it improves the withstand voltage of the insulating film between the first gate electrode and the second gate electrode, and reduces the charge in the first gate electrode. It is an object of the present invention to provide a semiconductor device that can improve retention characteristics and a method for manufacturing the same.

(問題点を解決するための手段) このため、この発明に係る半導体装置の製造方法におい
ては、第1ゲート電極である多結晶シリコンの上部を窒
化ケイ素で覆い、側壁部を酸化して、該窒化部を除去し
、第1ゲート電極である多結晶シリコンを次の第2ゲー
ト絶縁膜の厚さ以」ニエッチングした後に多結晶シリコ
ン上に第2ゲート絶縁膜を形成する工程を採用すること
により、前記目的を達成しようとするものである。
(Means for Solving the Problems) Therefore, in the method for manufacturing a semiconductor device according to the present invention, the upper part of the polycrystalline silicon that is the first gate electrode is covered with silicon nitride, the sidewall portion is oxidized, and the polycrystalline silicon is covered with silicon nitride. Adopt a step of removing the nitrided portion and etching the polycrystalline silicon serving as the first gate electrode to a thickness equal to or greater than the thickness of the next second gate insulating film, and then forming a second gate insulating film on the polycrystalline silicon. This aims to achieve the above objective.

(作用) 以上のような製造方法により形成されたこの発明に係る
半導体装置は、第1ゲート多結晶シリコンの側壁酸化膜
により、第1ゲート多結晶シリコンのエツジ部分の酸化
膜厚が厚くなって、絶縁耐圧が向上され、また、第1ゲ
ート電極中の電荷保持特性が改善される。
(Function) In the semiconductor device according to the present invention formed by the manufacturing method described above, the oxide film thickness at the edge portion of the first gate polycrystalline silicon is increased due to the sidewall oxide film of the first gate polycrystalline silicon. , the dielectric strength is improved, and the charge retention characteristics in the first gate electrode are also improved.

(実施例) 以下に、この発明を実施例に基づいて説明する。第1図
(a)、(b)、(e)および第2図(a)、(b)、
(c)に、この発明に係る不発揮性半導体記憶装置の製
造方法の一実施例の工程順に従った各要部断面図を示す
。本実施例の製造−方法に葛いては、シリコン基板i上
にフィールド酸化膜2、第1ゲート酸化膜3を形成した
のち、第1ゲート多結晶シリコン膜4を化学的気相成長
法で成長させ、ついで熱酸化法により、第1ゲート多結
晶シリコン4の上部に薄く酸化膜5を形成する。しかる
のち、その上に、化学気相成長法により窒化ケイ素1g
16を成長させる(第1図(a))。自己整合により、
第1多結晶シリコン4の上部のみが酸化WA5と窒化ケ
イ素膜6とで覆われているようにして(第1図(b))
、熱酸化法により、第1ゲート多結晶シリコンの側壁部
のみに酸化+1Q7を形成する(第1図(C))。
(Examples) The present invention will be described below based on Examples. Figure 1 (a), (b), (e) and Figure 2 (a), (b),
(c) shows a sectional view of each essential part according to the process order of an embodiment of the method for manufacturing a non-volatile semiconductor memory device according to the present invention. Regarding the manufacturing method of this embodiment, after forming a field oxide film 2 and a first gate oxide film 3 on a silicon substrate i, a first gate polycrystalline silicon film 4 is grown by chemical vapor deposition. Then, a thin oxide film 5 is formed on the first gate polycrystalline silicon 4 by thermal oxidation. After that, 1 g of silicon nitride was added on top of it by chemical vapor deposition.
16 (Fig. 1(a)). Through self-alignment,
Only the upper part of the first polycrystalline silicon 4 is covered with the oxidized WA 5 and the silicon nitride film 6 (FIG. 1(b)).
, oxidation +1Q7 is formed only on the sidewalls of the first gate polycrystalline silicon by a thermal oxidation method (FIG. 1(C)).

第2図(a)、(b)、(c)は、その後の各工程を示
す各要部断面図である。まず、第2図(a)に示すよう
に、前工程第1図(C)における窒化ケイ素膜6と熱酸
化膜5とを除去し、第1ゲート多結晶シリコン4を、次
の工程で形成する第2ゲート絶MII!8の厚さより少
し厚めにエツチングする。そして、この上に熱酸化法、
または化学気相成長法により第2ゲート絶縁膜8を成長
させ(第2図(b))、ついで、その上に、第2ゲート
電極9である多結晶シリコン、タングステンサイドなど
を形成する(第2図(C))。
FIGS. 2(a), 2(b), and 2(c) are sectional views of main parts showing subsequent steps. First, as shown in FIG. 2(a), the silicon nitride film 6 and thermal oxide film 5 in the previous step of FIG. 1(C) are removed, and the first gate polycrystalline silicon 4 is formed in the next step. The second gate Zetsu MII! Etch a little thicker than 8. Then, on top of this, thermal oxidation method,
Alternatively, the second gate insulating film 8 is grown by chemical vapor deposition (FIG. 2(b)), and then polycrystalline silicon, tungsten side, etc., which are the second gate electrode 9, are formed thereon (see FIG. 2(b)). Figure 2 (C)).

上記実施例の製造方法により形成されたこの半導体装置
の構造(第2図(C))から明らかなように、この実施
例において紘、第1ゲート多結晶シリコン4のエツジ部
上の第2ゲート絶縁膜8が、側壁酸化M7のために厚く
なっておりエッジ部分の絶縁膜の耐圧能力が向上して、
前記目的を達成することができる。
As is clear from the structure of this semiconductor device (FIG. 2(C)) formed by the manufacturing method of the above embodiment, in this embodiment, the second gate on the edge portion of the first gate polycrystalline silicon 4 is The insulating film 8 is thicker due to the sidewall oxidation M7, and the withstand voltage capability of the insulating film at the edge portion is improved.
The above objective can be achieved.

(発明の効果) 以上説明したように、この発明方法によれば、第1ゲー
ト電極のエツジ−Eの絶縁膜厚を厚くしたため、第1ゲ
ート電極と第2ゲート電極間の絶縁膜の耐圧能力が向上
し、また、第1ゲート電極の電荷の保持特性が改善され
るという効果が得られる。
(Effects of the Invention) As explained above, according to the method of the present invention, since the thickness of the insulating film of the edge E of the first gate electrode is increased, the withstand voltage capacity of the insulating film between the first gate electrode and the second gate electrode is It is possible to obtain the effect that the charge retention characteristics of the first gate electrode are improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)、(c)、第2図(a)、(b)
、(c)にこの発明による不揮発性半導体記憶装置の製
造T稈に従った各要部断面図、第3図(a)、(b)、
(c)、(d)に、従来の上記半導体装置の製造−り程
に従った各要部断面図を示す。 図中、1はシリコン基板、2はフィールド酸化膜、3は
ゲート酸化膜、4は、第1の伝導層第1ゲート電極、5
は薄い熱酸化膜、6は窒化ケイ素膜、7は熱側壁の熱酸
化膜、8は第2ゲート絶縁膜、9は第2ゲート電極であ
る。 なお、各図中、同一符号は、同一または相当構成要素を
示す。
Figure 1 (a), (b), (c), Figure 2 (a), (b)
, (c) is a sectional view of each main part according to the manufacturing process of the nonvolatile semiconductor memory device according to the present invention, and FIGS. 3(a), (b),
(c) and (d) are sectional views of the main parts of the conventional semiconductor device according to the manufacturing process. In the figure, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a first conductive layer, a first gate electrode, and 5
6 is a thin thermal oxide film, 6 is a silicon nitride film, 7 is a thermal sidewall thermal oxide film, 8 is a second gate insulating film, and 9 is a second gate electrode. Note that in each figure, the same reference numerals indicate the same or equivalent components.

Claims (2)

【特許請求の範囲】[Claims] (1)二重ゲート構造をもつ不揮発性半導体記憶装置の
製造方法において、第1の伝導層を形成したのち、熱酸
化法により薄い酸化膜を形成し、ついで、化学気相成長
法により、窒化ケイ素膜を成長させる工程と、前記第1
の伝導層を選択的にエッチングし、その側壁に熱酸化法
により薄く酸化膜を形成する工程と、前記窒化ケイ素膜
と薄い酸化膜とを除去したのち、前記第1の伝導層を、
エッチングして、その上に第2ゲート絶縁膜を形成し、
ついで第2の伝導層を形成する工程とからなることを特
徴とする半導体製造方法。
(1) In a method for manufacturing a nonvolatile semiconductor memory device with a double gate structure, after forming a first conductive layer, a thin oxide film is formed by thermal oxidation, and then nitrided by chemical vapor deposition. a step of growing a silicon film; and a step of growing a silicon film;
After selectively etching the conductive layer and forming a thin oxide film on its sidewall by thermal oxidation, and removing the silicon nitride film and the thin oxide film, the first conductive layer is removed.
etching and forming a second gate insulating film thereon;
A semiconductor manufacturing method comprising the step of: then forming a second conductive layer.
(2)二重ゲート構造をもつ不揮発性半導体記憶装置に
おいて、第1の伝導層のエッジ上の第2ゲート絶縁膜の
膜厚を、第1の伝導層表面の膜厚よりも厚く構成したこ
とを特徴とする半導体装置。
(2) In a nonvolatile semiconductor memory device with a double gate structure, the thickness of the second gate insulating film on the edge of the first conductive layer is configured to be thicker than the thickness of the surface of the first conductive layer. A semiconductor device characterized by:
JP11281387A 1987-05-07 1987-05-07 Semiconductor device and manufacture thereof Pending JPS63276272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11281387A JPS63276272A (en) 1987-05-07 1987-05-07 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11281387A JPS63276272A (en) 1987-05-07 1987-05-07 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS63276272A true JPS63276272A (en) 1988-11-14

Family

ID=14596174

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11281387A Pending JPS63276272A (en) 1987-05-07 1987-05-07 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS63276272A (en)

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