JPH0410631A - Semiconductor chip sucking jig - Google Patents
Semiconductor chip sucking jigInfo
- Publication number
- JPH0410631A JPH0410631A JP11429290A JP11429290A JPH0410631A JP H0410631 A JPH0410631 A JP H0410631A JP 11429290 A JP11429290 A JP 11429290A JP 11429290 A JP11429290 A JP 11429290A JP H0410631 A JPH0410631 A JP H0410631A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- semiconductor chips
- die bonding
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 206010008631 Cholera Diseases 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はマイクロ波半導体チップを取り扱う吸着治具
（以下コレットと呼ぶ）に関し、特にチップ吸着部の構
造を提供するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a suction jig (hereinafter referred to as a collet) for handling microwave semiconductor chips, and particularly provides a structure of a chip suction part.
第４図は従来のコレットの斜視図を示す。この構造はコ
レット（１）の先端部分に吸着すべきチップの形状にあ
わせて形成した吸着部（２）と、この吸着部（２）内に
半導体素子を真空吸着するためのバキュームホール（３
）より構成されている。FIG. 4 shows a perspective view of a conventional collet. This structure consists of a suction part (2) formed at the tip of the collet (1) according to the shape of the chip to be suctioned, and a vacuum hole (3) for vacuum suction of the semiconductor element inside this suction part (2).
).
このコレットでは半導体チップのキャリヤ或いはパッケ
ージ等への実装時に、半導体チップをバキュームホール
（３）を介して吸着部（２）で真空吸着して、１チツプ
づつの搬送、各種処理を行う。しかし、第５図（ａ）の
断面図に示す様な厚み約３０μｍ程度の極薄ＧａＡｓ基
板（９）の裏面に、接地電極とヒートシンク層を兼ねる
厚い金めつき層（１０）を形成した構造の半導体チップ
を、パッケージのダイパッド部（６）にＡｕ８ｎ半田剤
などによりダイボンドする場合には、通常Ｇａ Ａ８基
板（９）と金めつき層（１０）の熱膨張率の差により、
ダイボンド時の加熱により（１２）Ｋ示す量の反りが生
じるため、第５図（ｂ） Ｋ示す様にコレット（１）に
よりＧａＡｓ基板（９）を押圧しながら冷却することに
よりチップの反抄を抑制していた。In this collet, when a semiconductor chip is mounted on a carrier, package, etc., the semiconductor chip is vacuum-suctioned by a suction part (2) through a vacuum hole (3), and one chip is transported and various processes are carried out. However, as shown in the cross-sectional view of Figure 5(a), there is a structure in which a thick gold-plated layer (10) serving as a ground electrode and a heat sink layer is formed on the back surface of an ultra-thin GaAs substrate (9) with a thickness of about 30 μm. When die-bonding a semiconductor chip to the die pad portion (6) of the package using Au8n solder, etc., the difference in thermal expansion coefficient between the Ga A8 substrate (9) and the gold plating layer (10) usually causes
Since the heating during die bonding causes a warpage of (12)K, the chip is cooled by pressing the GaAs substrate (9) with the collet (1) as shown in FIG. It was suppressed.
従来のコレットは以上の様に構成されていたので、パッ
ケージなどに同種半導体チップを複数個数べて接着する
必要がある場合には、先に半田付けした半導体チップが
、後の半導体チップのダイボンド時に反ってしまい、ま
た、１チツプづつ扱うので作業時間が長く、更に半導体
チップ間距離にばらつきがでるなどの問題点力長あった
。Conventional collets were constructed as described above, so when it is necessary to bond multiple semiconductor chips of the same type to a package, etc., the semiconductor chips that are soldered first are used when the semiconductor chips are die-bonded later. There were many problems, such as warping, long working time as each chip was handled one at a time, and variations in the distance between semiconductor chips.
この発明は上記のような問題点を解消するためになされ
たもので、複数の半導体素子を同時に取り扱うことによ
り、ダイボンド時間を短縮し、半導体チップ間距離のば
らつきの抑制と、半導体チップ間距離の短縮及びダイポ
ンド時の熱による反りを抑制する半導体チップコレット
を得ることを目的とする。This invention was made to solve the above-mentioned problems, and by handling multiple semiconductor elements simultaneously, it shortens die bonding time, suppresses variations in the distance between semiconductor chips, and reduces the distance between semiconductor chips. The object of the present invention is to obtain a semiconductor chip collet that suppresses warping due to heat during shortening and die pounding.
この発明に係る半導体チップコレットは、半導体チップ
に対する吸着部の個数を複数とし、半導体チップに対す
る複数の吸着部を所望の半導体チップの配置形状にあわ
せて形成したものである。The semiconductor chip collet according to the present invention has a plurality of suction parts for the semiconductor chips, and the plurality of suction parts for the semiconductor chips are formed in accordance with the desired arrangement shape of the semiconductor chips.
この発明における半導体チップコレットは、半導体チッ
プに対する吸着部の個数を複数とすることにより、複数
の半導体チップを同時に取り扱いダイポンド時の熱によ
る反りを抑制し、またダイポンド時間を短縮し、さらに
半導体チップに対する複数の吸着部を所望の半導体チッ
プの配置形状にあわせて形成することにより、半導体チ
ップ間距離のばらつきを抑制し、チップ間距離を短縮す
ることができる。The semiconductor chip collet of the present invention has a plurality of suction parts for semiconductor chips, thereby handling multiple semiconductor chips at the same time and suppressing warping due to heat during die-pounding, shortening the die-pounding time, and By forming a plurality of adsorption portions in accordance with the desired arrangement shape of the semiconductor chips, it is possible to suppress variations in the distance between semiconductor chips and shorten the distance between the chips.
以下、この発明の一実施例を図に従って説明する。第１
図はこの発明の一実施例であるコレットの断面説明図を
示す。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a cross-sectional view of a collet which is an embodiment of the present invention.
図において、（１）はコレット、（２）はコレラ） （
１）の先端部に半導体チップＡ（４）と半導体チップＢ
（５）の形状に合わせ、且つパッケージのダイパッド部
（６）の半導体チップＡのダイポンド位置（７）および
、半導体チップＢのダイポンド位置（８）の配置に合わ
せ作成されたチップ吸着部である。（３）は半導体チッ
プＡ−Ｂを真空吸着する為のバキュームホールである。In the figure, (1) is Colette, (2) is Cholera) (
1) Semiconductor chip A (4) and semiconductor chip B are placed at the tip of
This is a chip adsorption section made to match the shape of (5) and the arrangement of the die pad position (7) of the semiconductor chip A and the die pound position (8) of the semiconductor chip B of the die pad section (6) of the package. (3) is a vacuum hole for vacuum suctioning the semiconductor chip A-B.
このようにした構造では２個の半導体チップＡ・Ｂを同
時に取扱うことができ、第２図に示すＧａＡ３基板（９
）裏面に約６０μｍの金めつき層（１０）が作成された
構造の半導体チップの半田付けも、このコレット（１）
によって半導体チップをダイポンド後も押えながら冷却
することＫより、半導体チップの反りを抑制することが
できる。また上記構造の半導体チップ以外の場合にも、
例えば第３図に示すバキュームホール（３）を所望の半
導体チップのダイポンド位置及び半導体チップ間距離（
１３）に合わせ作成することにより、−度に４個の半導
体チップを同時に扱い、ダイボンド時間を短縮し、且つ
半導体チップ間距離のばらつきの抑制及び半導体チップ
間距離を短縮することができる。With this structure, two semiconductor chips A and B can be handled simultaneously, and the GaA3 substrate (9
) This collet (1) can also be used to solder a semiconductor chip with a gold plating layer (10) of about 60 μm on the back side.
By cooling the semiconductor chip while pressing it even after die-pounding, it is possible to suppress warping of the semiconductor chip. Also, in cases other than semiconductor chips with the above structure,
For example, the vacuum hole (3) shown in FIG.
13), it is possible to handle four semiconductor chips at the same time, shorten the die bonding time, suppress variations in the distance between semiconductor chips, and shorten the distance between semiconductor chips.
以上のようにこの発明によれば、半導体チップに対する
吸着部の個数を複数としたので、ダイポンド時の熱によ
る反りを抑制し、また、ダイボンド時間を短縮すること
ができ、また、半導体チップに対する複数の吸着部を所
望の半導体チップの配置形状にあわせて形成することに
より、半導体チップ間距離のばらつきを抑制することが
でき、半導体チップ間の距離を短縮することができる効
果がある。As described above, according to the present invention, since the number of suction parts for the semiconductor chip is plural, it is possible to suppress warping due to heat during die bonding, shorten the die bonding time, and By forming the suction portion in accordance with the desired arrangement shape of the semiconductor chips, it is possible to suppress variations in the distance between the semiconductor chips, and there is an effect that the distance between the semiconductor chips can be shortened.
第１図はこの発明の一実施例による半導体チップコレッ
トの断面説明図、第２図は裏面に金めつき層を施こした
半導体チップを第１図のコレットでダイポンドを行った
状態の断面図、第３図はこの発明の他の実施例によるコ
レットの斜視図、第４図は従来のコレットの斜視図、第
５図（ａ） （ｂ）は第４図のコレットによる半導体チ
ップの吸着・処理状態を示す断面図である。
図において、（１）はコレラ） 、（２）はチップ吸着
部、（３）ｄバキュームホール、（４）は半導体チップ
Ａ、（５）は半導体チップＢ 、 （６）はパッケージ
のダイパッド部、（７）は半導体チップＡのダイポンド
位置、（８）は半導体チップＢのダイポンド位置、（９
） ハＧａ Ａｓ 基板、（１０）は金めつき層、（１
１）は半田層、（１３）は半導体チップ間距離を示す。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is an explanatory cross-sectional view of a semiconductor chip collet according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor chip with a gold plating layer applied to the back surface after being die-pounded using the collet shown in FIG. , FIG. 3 is a perspective view of a collet according to another embodiment of the present invention, FIG. 4 is a perspective view of a conventional collet, and FIGS. It is a sectional view showing a processing state. In the figure, (1) is cholera), (2) is the chip suction part, (3) is the d vacuum hole, (4) is the semiconductor chip A, (5) is the semiconductor chip B, (6) is the die pad part of the package, (7) is the die pound position of semiconductor chip A, (8) is the die pound position of semiconductor chip B, (9
) Ga As substrate, (10) gold plated layer, (1
1) indicates the solder layer, and (13) indicates the distance between semiconductor chips. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
導体チップに対する吸着部の個数を複数としたことを特
徴とする半導体チップ吸着治具。A semiconductor chip suction jig for suctioning and handling a semiconductor chip, characterized in that the suction jig has a plurality of suction parts for semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11429290A JPH0410631A (en) | 1990-04-27 | 1990-04-27 | Semiconductor chip sucking jig |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11429290A JPH0410631A (en) | 1990-04-27 | 1990-04-27 | Semiconductor chip sucking jig |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0410631A true JPH0410631A (en) | 1992-01-14 |
Family
ID=14634205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11429290A Pending JPH0410631A (en) | 1990-04-27 | 1990-04-27 | Semiconductor chip sucking jig |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0410631A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090223628A1 (en) * | 2008-03-07 | 2009-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing apparatus of composite substrate and manufacturing method of composite substrate with use of the manufacturing apparatus |
| JP6484370B1 (en) * | 2018-05-31 | 2019-03-13 | アサヒ・エンジニアリング株式会社 | Electronic component mounting equipment |
-
1990
- 1990-04-27 JP JP11429290A patent/JPH0410631A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090223628A1 (en) * | 2008-03-07 | 2009-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing apparatus of composite substrate and manufacturing method of composite substrate with use of the manufacturing apparatus |
| JP6484370B1 (en) * | 2018-05-31 | 2019-03-13 | アサヒ・エンジニアリング株式会社 | Electronic component mounting equipment |
| WO2019230032A1 (en) * | 2018-05-31 | 2019-12-05 | アサヒ・エンジニアリング株式会社 | Electronic component mounting device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH02271558A (en) | Semiconductor device and its manufacture | |
| US20220173022A1 (en) | Clips for semiconductor package and related methods | |
| KR100721279B1 (en) | A method of forming semiconductor chip assembly and an apparatus for forming wire bonds from circuitry on a substrate to a semiconductor chip | |
| JP2020178026A (en) | Assembly jig set and manufacturing method of semiconductor module | |
| JP3351395B2 (en) | Flip chip forming method using chip tray | |
| JP2000173952A (en) | Semiconductor device and its manufacture | |
| JPH0410631A (en) | Semiconductor chip sucking jig | |
| JP3651362B2 (en) | Manufacturing method of semiconductor device | |
| JP2004158739A (en) | Resin sealed semiconductor device and manufacturing method therefor | |
| JP3908590B2 (en) | Die bonding method | |
| JP2812313B2 (en) | Semiconductor device | |
| JPH08255803A (en) | Semiconductor module and manufacture thereof | |
| JPS62216251A (en) | High thermal conductive substrate | |
| WO2022038700A1 (en) | Substrate holder, bonding system, and bonding method | |
| JPS63138794A (en) | Die bonding for semiconductor laser element | |
| JPH11251510A (en) | Lead frame and semiconductor device using the same | |
| KR20240070860A (en) | Heat dissipation substrate package and its manufacturing method | |
| JP2001267351A (en) | Wire-bonding structure | |
| TW202314877A (en) | Substrate holder, bonding system, and bonding method capable of stably bonding semiconductor chips to individual substrates | |
| JPH08125076A (en) | Semiconductor package | |
| JPH02126647A (en) | Bonding apparatus | |
| JP2845634B2 (en) | Ceramic package | |
| JP2005209864A (en) | Semiconductor device manufacturing method, and semiconductor manufacturing apparatus | |
| JP2001308125A (en) | Mounting board and semiconductor device | |
| JP2513255B2 (en) | Semiconductor device |