JPH02126647A - Bonding apparatus - Google Patents

Abstract

PURPOSE:To restrain a warp of a chip from being caused during a heating operation and to achieve a good bonding operation by constituting the chip part of a bonding tool of a diamond or ceramic layer whose side coming into contact with a lead is divided into a plurality of parts, and whose lower layer is a super alloy. CONSTITUTION:A chip part 18 is constituted of a tungsten carbide (WC) layer 20 of about 9X16X2.5mm and a diamond layer 21 of about 9X16X0.7mm which have been arranged on the side of a brazing material 19. Coefficients of thermal expansion of Inconel constituting a shank 17, the WC layer 20 and the diamond layer 21 are as follows: 16.0X10<-6>/ deg.C for Inconel; 5.0X10<-6>/ deg.C for the WC layer; 3.0X10<-6>/ deg.C to 3.8X10<-6>/ deg.C for a sintered diamond. A comparatively large difference in thermal expansion exists between the shank 17 and the WC layer 21. Because of this difference in thermal expansion, slits 22 about 0.5mm wide ranging from the diamond layer 21 to the WC layer 20 constituting the chip part 18 are so as not to coincide with positions of leads 15 by using a wire; the chip part 18 is divided into eight parts which are nearly square.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a bonding device for connecting electrodes of a semiconductor element and leads of a TAB film carrier via bumps.

(Prior art) In recent years, electronic devices include LCD TVs, IC cards, card calculators,
As seen in radios, devices are becoming lighter, thinner, shorter, and smaller, and semiconductor chips such as LSIs built into them are becoming more dense and highly integrated. In addition, as LSIs become more highly integrated, there is a trend toward larger chips, an increase in the number of I10, and a reduction in the electrode pitch.

Incidentally, semiconductor packaging methods to meet the above requirements are being developed in the direction of thinning and high density (increasing the number of I10s, narrowing the electrode pitch, and increasing the size of chips).

Among such mounting methods, the wire bonding method has a diameter of 25 to 30 μm for each of the A chisel pole of LSI and the external wiring pattern.
Move the Au wire using a capillary and bond with heat to form A
This is a technology that connects by forming a u-alloy, and is widely used due to the spread of automated equipment and the versatility of bonding equipment. However, in the wire bonding method, it is difficult to reduce the thickness of the wire because the wire draws an arcuate loop, and furthermore, since bonding is performed using a capillary, if the electrode pitch becomes narrow, the adjacent bonded Au
Wires interfere with bonding, making it impossible to accommodate narrower pitches. Furthermore, in order to bond one bottle at a time,
There are many problems with multi-pin/LSI devices, such as the time required and failure to form a pair in case of defective bonding.

For these reasons, the wireless bonding method is attracting attention and being put into practical use. The TAB method and the flip-chip method are typically known as wireless bonding methods, but the flip-chip method is difficult to bond and also difficult to form solder bumps. On the other hand, T.A.
Method B has been adopted in card calculators, card radios, etc., has a lot of experimental data, bonding equipment has been manufactured, and it has been introduced from an early stage.

The TAB method is T ape Autoa+atcd
This is an abbreviation for B onding method, and as shown in Figure 8, a wiring pattern made of Cu is formed on a long organic film (polyimide, glass epoxy, etc.). Align the tip of the pattern lead 3 with the bump (metal protrusion) 5 formed on the top of the A chisel of the LSI 4, and
Bonding tool 6 heated to 00-500°C at a pressure of 70-100 g/bump from 0.5-2.
The tip of the Cu pattern lead 3 is pressed against the bump 5 from above for 0 seconds to bond them by thermocompression and to connect them. The conditions of heating temperature, pressurizing force, and pressurizing time at this time are appropriately selected depending on the materials of the leads and bumps, etc.

The bumps are usually made of Au and are formed by photolithography through a base metal film formed on the Af electrode by vapor deposition or sputtering. The underlying metal film is AI! A bottom layer such as Tj Cr that has adhesion to the electrode, a layer such as Ni that has a barrier effect between Au/AJ, and Pt to increase the adhesion of Au plating.
It consists of an Au layer or the like.

The Cu lead on the film carrier is typically 0.
Approximately 4 μm of Sn plating is applied to the LSI AI.
! The Au bumps on the electrodes are bonded by thermocompression bonding using a bonding tool to create an Au-Sn alloy.

Conventionally, the bonding tool of the bonding device is
As shown in FIG. 9, a tip portion consisting of a cemented carbide layer 8 and a diamond layer (or ceramic layer) 9, which have been integrated in advance in a recessed portion of the tip surface of the main body portion (shank) 7, is inserted into the tip portion. It has a structure in which it is joined and fixed via a brazing material IO such as Ag so that it is located on the shank 7 side. In addition,
The chip portion has a shape corresponding to the size of the LSI chip, and known examples include Syndite from DeBeers and Compax from GE.

In bonding the Cu lead of the film carrier and the bump of the LSI using the bonding tool described above, the LS
The number of pins of I is about 100 bins, and the chip size is 110m.
If the size is about X1O, the tool shown in Fig. 10 (
A tool having a chip portion as shown in A) is used, and when bonding is performed using the chip portion of this tool 6, the Cu lead of the film carrier and the bump of the LSI can be bonded well. This is shown in Figure (B) after bonding.
This is clear from the fact that --like impressions (shaded areas) appear on the diamond layer 9 of the chip portion corresponding to the bumps of the LSI chip, as shown in FIG. However, as LSIs become more highly integrated in recent years, bonding failures may occur, especially when the chip size of memory, gate arrays, etc. increases to 15 m or more on a side. This is L
Since the size of the tip at the tip of the bonding tool increases in accordance with the SI chip size, when the tool is heated to a high temperature, the heat between the shank 7 and the cemented carbide layer 8 forming the tip shown in FIG. 9 described above increases. This is because a large concave warpage occurs in the tip portion due to the difference in expansion and the difference in thermal expansion between the diamond layer 9 and the cemented carbide layer 8 that constitute the tip portion.

That is, when the bonding tool 6 with a large chip part is used to bond the Cu leads of the film carrier and the bumps of the LSI as shown in FIG. Strong pressure is applied to each corner of the chip, and sufficient pressure cannot be applied to the bumps on the outer periphery of the chip between the corners, resulting in poor bonding. This is the same figure (B) after bonding.
), this is clear from the fact that indentations (shaded areas) appear only at the corner portions of the diamond layer 9 of the tip portion. If bonding is performed at a higher pressure to eliminate such bonding defects, other problems such as damage to the LSI chip, deformation of the leads, or edge touching of the leads occur, leading to a decrease in yield.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned conventional problems. It is an object of the present invention to provide a bonding device that can achieve good bonding by suppressing the occurrence of warping of the chip portion.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a method in which a bump exists between an aluminum electrode of a semiconductor element and a lead of a TAB film carrier in which a wiring pattern is formed on an organic resin film. In this bonding device, the electrode and the lead are connected via a bump by thermocompression bonding with a tip portion at the tip of the bonding tool in a state in which the tip portion of the bonding tool is bonded to a diamond or ceramic layer and a cemented carbide layer in contact with the lead. The bonding device is characterized in that the diamond or ceramic layer is divided into a plurality of layers by providing one or more slits in at least the diamond or ceramic layer.

The main body (shank) of the bonding tool is made of, for example, Inconel, molybdenum, or the like.

Regarding the depth of the slit, it is desirable to set it in consideration of the difference in thermal expansion between the shank and the cemented carbide layer, from the viewpoint of suppressing the occurrence of warping of the tip portion during heating. In other words, if the difference in thermal expansion between the shank and cemented carbide is similar,
A slit is provided in the diamond or ceramic layer on the upper layer side of the chip part to divide only this layer. However, even in this case, slits may be provided throughout the cemented carbide. On the other hand, if the difference in thermal expansion between the shank and the cemented carbide is large, the chip portion is divided by providing a slit across the entire chip, that is, from the diamond or ceramic layer to the cemented carbide layer. Note that the divided tip portions are fixed to the tip of the shank using a brazing material such as Ag.

Regarding the position of the slit, it is necessary to ensure that it does not coincide with the position of the lead of the film carrier to be bonded.

It is desirable that the chip portions divided by providing the slits be as close to square as possible and symmetrical both left and right and front and back.

It is desirable that the slit be formed using a wire or the like after the tip portion is fixed to the shank, for example.

(Function) According to the present invention, the tip portion of the bonding tool is composed of a diamond or ceramic layer on the side in contact with the lead and a lower cemented carbide layer, and at least one or more slits are formed in the diamond or ceramic layer. By providing a structure with multiple divisions, LSI
Even if the size of the chip portion increases in accordance with the increase in the size of the chip, it is possible to suppress the occurrence of concave warping of the chip portion during heating. As a result, when bonding the Cu leads of the film carrier with the bumps of a large LSI using the tip part of the bonding tool, it is possible to apply uniform and uniform pressure to the bumps of the LSI, so that the Cu leads of all the film carriers are bonded. Leads and bumps of a large LSI can be bonded well.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

Example 1 FIG. 1 is a partial cross-sectional view showing the arrangement of the LSI chip, film carrier, and bonding tool before bonding in Example 1, and FIG.
A plan view of the SI chip, Figure i3 (A) is a cross-sectional view of the main part of the bonding tool, and Figure CB) is a rear view showing the chip part in Figure (A). 11 in the figure is a memory IC chip as an LSI chip with 28 pins and a chip size of about 9IIIX1 [iM]. AI of this IC chip 11
An Au bump 12 with a thickness of 20 μm is formed on the electrode with a base metal of Au/Pt/TI interposed therebetween. Said IC
A film carrier 13 is disposed above the chip 11, and the tips of Sn-plated Cu leads 15 extending into the openings 14 of the carrier 13 are aligned with each bump 12 of the chip 11. . A bonding tool 1 is provided above the opening 14 of the film carrier 13.
B is placed. This bonding tool 1B is
A shank 17 made of Inconel is provided, and a tip portion 18 is fixed to four parts of the tip surface of the shank 17 via an Ag brazing material 19. This chip portion 18 is connected to the brazing material 1
Approximately 9 ru x 16m x 2.5 placed on 9 side
It consists of a tungsten carbide (WC) layer 20 of rttx and a diamond IW 21 of about 9 m x IBau x O, 7B. Note that the shank 17
The thermal expansion coefficients of Inconel, WC layer 20 and diamond layer 21 that constitute Inconel 1B, OX 10-
6/"C1W C,5,OX 10-6/'C1 sintered diamond; 3.OX 10-6/"C:~3.
8 x 10-6/'C, shank 17 and WC
There is a relatively large differential thermal expansion between the layers 21. Because of this difference in thermal expansion, a wire is used to extend the width of the chip portion 18 from the diamond layer 21 to the WC layer 20 to a width of approximately 0.
A slit 22 of 511ffi is formed so as not to coincide with the position of the lead 15, and the chip portion 18 is divided into eight parts so as to have a shape close to a square.

Using the bonding tool 16 described above, bonding was performed between the bumps 12 of the IC chip 11 and the leads 15 of the film carrier 13 under conditions of a tool temperature of 500° C., a pressing force of 809/bump, and a time of 1 second.

As a result, a strong bond was obtained in which the tensile strength of all the pins was 309/bump or more, and the failure mode was all lead breakage. When we examined the indentations on each divided part of the tip part 18 of the tool 16 at this time, the indentations were clearly visible, and the indentations were observed on all corners and sides of each divided part. It was confirmed that the occurrence of warpage was significantly reduced.

Example 2 FIG. 4 is a plan view showing the arrangement of the LSI chip and film carrier used in Example 2, FIG. 5 (A) is a sectional view of the main part of the bonding tool, and FIG. Diagram (A
) is a rear view showing the chip portion of the device. 11' in the figure is
It is a memory IC chip as an LSI chip with a chip size of approximately 6 MX 10 m and 29 pins with A chisel pole pads concentrated on two opposing sides. This IC chip 11' is for wire bonding and has no bumps formed thereon, leaving the A pad exposed as it is. A film carrier 13' is arranged above the IC chip tt'. Au bumps (not shown) are attached to the tips of the Sn-plated Cu leads 15 extending into the openings 14 of the carrier 13', and these bumps match the It' pads of the chip 11'. It is supposed to be done. Above the 13° opening 14 of the film carrier, there is a
) A bonding tool 16'' shown in FIG. This bonding tool 16' includes a shank 17 made of molybdenum, and a tip portion 18° is fixed to a concave portion on the tip surface of the shank 17 via an Ag brazing material 19. This chip portion 1g' is arranged on the side of the brazing material 19.
1 tungsten carbide (WC) layer 20 and 8 rt
It is composed of ua X 10111 X O, 7B (7) sintered diamond layer 21. The coefficient of thermal expansion of molybdenum, the WC layer 2o, and the diamond layer 21 constituting the shank 17 is molybdenum; 5.4 x 1
0-6/'C1WC; 5. OX 10-6/”C1
Sintered diamond; 3. OxlO-6/'C~3.1
i xlO-6/'C Te, shank 17 and WC layer 2
There is a relatively large difference in thermal expansion between the WC layer 20 and the diamond layer 21. Due to this difference in thermal expansion, a slit 22 with a width of about 0.3M is formed only in the diamond layer 21 constituting the tip portion 18 using a wire.
is formed so as not to coincide with the position of the lead 15,
The diamond layer 21 at the tip portion 18° is divided into two parts so as to have a shape close to a square.

'' Using a series of bonding tools 16', tool temperature: 470°C, pressing force: 10 g/bump for the first stage, 2
IC chip 11 under conditions of stage 90g/bump, time: 1st stage 3 seconds, 2nd stage 1 second, stage temperature: 150°C.
Bonding was carried out between the pad A of 11' and the bump (not shown) attached to the glue 15 of the film carrier 13'. As a result, the tensile strength of all pins is 25g
A bond stronger than /bump was obtained, and the failure mode was all lead breakage. At this time, when examining the impressions at each division of the tip portion 18'' of the tool 1B', we found that
The indentation was clearly visible, and the indentation was observed at all corners and all the way through each divided portion, and it was confirmed that the occurrence of warpage in the tip portion 18' had been significantly reduced.

Embodiment 3 FIG. 6 is a plan view showing the arrangement of the LSI chip and film carrier used in Embodiment 3, FIG. It is a back view which shows the chip part of the same figure (A). 11'' in the figure is a gate array chip as an LSI chip with 3oo bins, an electrode pitch of 100.czm, and a chip size of about 15m x 15m.In the center of the four sides of this chip 11'',
A wide part is formed with a pitch of 0.7 wax.

Moreover, on the AI electrode of the chip 11'', Au/Pt/
Au bumps (not shown) with a thickness of 20 μm are formed through the TI base metal. A film carrier 13'' is disposed above the chip 112, and a Sn-plated Cu film carrier 13'' extends into the opening 14 of the carrier 13''.
The tip of the bonding tool 15 is adapted to match each bump of the chip 11''.A bonding tool 18'' shown in FIG. 7(A) is disposed above the opening 14 of the film carrier 13#. has been done. This bonding tool 16'' includes a shank 17 made of Inconel, and a tip portion 8'' is fixed to a recessed portion of the tip surface of the shank 17 via an Ag brazing material 19. This chip portion 18'' is approximately 9 ru
I! l1lX 2.5 plates of tungsten carbide (W
C) Layer 20 and approximately 9 rm x 18m x O, 7rt
Constructed from RX Diamond Ji21. Then, using a wire, a slit 22 having a width of about 0.5B is formed from the diamond layer 21 to the WC layer 20 constituting the chip portion 18'' so as not to coincide with the position of the lead 15. The portion 18 is divided into four parts so as to have a shape close to a square.

Using the bonding tool 16 described above, the bumps of the gate array chip 11'' and the leads 15 of the film carrier 13'' are bonded under the following conditions: tool temperature: 500° C., pressure: 709/bump, time: 0.5 seconds. I did it. As a result, all the tensile strengths of all the bottles were at lead breakage. At this time, when we examined the indentations on each divided part of the tip part 18'' of the tool 18'', the indentations were clearly visible, and the indentations were observed at all corners and all the way through each divided part. It was confirmed that the occurrence of warpage was significantly reduced.

[Effects of the Invention] As detailed above, according to the present invention, at least the upper layer containing diamond or ceramics constituting the tip portion attached to the tip of the shank is divided by providing one or more slits. By providing this bonding tool, even if the size of the chip portion increases in response to the large size of the LSI chip, it is possible to suppress the occurrence of warping of the chip portion during heating, and furthermore, it is possible to suppress the occurrence of warping of the chip portion during heating, and furthermore, it is possible to suppress the occurrence of warping of the chip portion during heating. A bonding device that can achieve extremely good bonding can be provided.

[Brief explanation of drawings]

Figure 1 shows the LSI chip before bonding of Example 1.
FIG. 2 is a partial cross-sectional view showing the arrangement of the film carrier and bonding tool.
FIG. 3(A) is a plan view of the I chip, FIG. 3(A) is a cross-sectional view of the main part of the bonding tool, FIG. 3(B) is a rear view showing the chip part of FIG. 3(A), and FIG. 5th plan view showing the arrangement of the LSI chip and film carrier used;
Figure (A) is a sectional view of the main parts of the bonding tool, and Figure (B) is a sectional view of the main parts of the bonding tool.
) is a rear view showing the chip part in FIG. 6(A), FIG. 6 is a plan view showing the arrangement of the LSI chip and film carrier used in Example 3, and FIG. 7(A) is a rear view showing the chip part in FIG. FIG. 8 is a partial sectional view showing the arrangement of the LSI chip, film carrier, and bonding tool before bonding; FIG. 9 is a rear view showing the chip part in FIG. The figure is a cross-sectional view of the main part of the bonding tool shown in Fig. 8, Fig. 9 (A) is a front view of a bonding tool used for conventional small LSI chips, and Fig. 9 (B) is a cross-sectional view of the bonding tool shown in Fig. 8 (A). 4(A) is a front view of a bonding tool used for conventional large LSI chips, and FIG. FIG. 3 is a plan view showing an indentation on the chip portion after bonding with a tool. 11, 11° 11”...LSI chip, 13.1
3° 13”...Film carrier, 15...C
u Lead, 113.1B'16"...Bonding tool, 17...Shank, 18.18°, 18"
...Chip portion, 20...WC layer, 21...Diamond layer, 22...Slit. Applicant's representative Patent attorney Takehiko Suzue (A) (B) Silk (A) (B) (A) (A) (A) (B) Diagram (B)

Claims (1)

[Claims] With a bump present between the aluminum electrode of the semiconductor element and the lead of the TAB film carrier in which a wiring pattern is formed on the organic resin film, the electrode and the lead are bonded by thermocompression using the tip at the tip of the bonding tool. 2. A bonding device for connecting a bonding tool to a bonding tool, wherein the tip portion of the bonding tool has a diamond or ceramic layer divided into a plurality of parts on the side in contact with the lead, and a lower layer made of cemented carbide.