JP2822506B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a soldering step of pins provided in a PGA package, wherein a pad for soldering pins and a solder dam are provided by a thin film forming technique, and a brazing material is used. A semiconductor device having a package in which a semiconductor chip is mounted on the front side of a substrate and a plurality of pads are provided on each of a plurality of pads on the back side of the substrate. In the manufacturing method, a pad connected to each of the plurality of via holes is provided on the back side of the substrate by a thin film forming technique, and a solder resist made of a vitreous material is formed on the entire surface of the substrate provided with the pad. The film is provided by a thin film forming technique, and the solder resist film is formed so that the peripheral portion of the pad is covered with the solder resist film and the central portion is exposed. Sorudadamu is provided to be etched, the pin to the pads are soldered by brazing material, the Sorudadamu is removed, the periphery of the pad and the brazing material and the pin constituting the package so as to be covered with the plating film.

[Industrial applications]

The present invention relates to a method for soldering pins provided in a PGA package on which a semiconductor chip is mounted, among semiconductor devices.

In recent years, with the increase in the density of semiconductor devices, the number of terminals derived from one semiconductor device has been steadily increasing as per Lent's law, and there are several hundred to several thousand terminals.

A silicon wafer that has completed a wafer process is generally finished into a semiconductor device through an inspection process from an assembly process called a post-process.

In the assembling process, the wafer is first scribed and divided into chips, and mounting (die bonding), bonding, sealing, marking, and the like are performed.

Here, in the case of a small chip having a relatively low degree of integration, many chips are mounted on a frame-shaped terminal called a lead frame, wire-bonded, and then sealed with a resin.

However, in the case of highly integrated LSIs and super LSIs, the number of lead terminals derived from one chip is increased by orders of magnitude, and it is extremely difficult to connect by wire bonding.

Therefore, many lead terminals derived from the chip are
It is an important issue how to efficiently and externally lead out the semiconductor device, which also affects the cost of the semiconductor device itself.

[Conventional technology]

In the bonding step of taking out terminals from the semiconductor chip, if the number of terminals increases, wire bonding becomes unwieldy and a so-called wireless system without wires is used.

The wireless method includes a flip chip method in which a chip provided with bumps is face-down and fixed directly to a substrate,
A beam lead method in which a chip provided with a beam-shaped lead is face-down and fixed directly to a substrate, and a bump provided on the chip is attached to a lead piece provided on a long tape-shaped carrier with a perforation (perforation). A well-fixed tape carrier system is well known.

Among them, the tape carrier method is a method developed for the purpose of automatic embedding, and TAB (tab, Tape Au
Also called tomated bonding.

 Hereinafter, a TAB connection will be described as an example.

This TAB connection consists of inner lead bonding (hereinafter abbreviated as ILB) that connects the TAB lead provided on the tape carrier and the bump provided on the chip, and the TAB lead provided on the tape carrier on a package etc. And an outer lead bonding (hereinafter abbreviated as OLB) for connecting to a terminal called a lead pattern.

Then, after the OLB is completed, a part of the tape carrier is sealed together while holding the TAB lead, or is removed before the OLB.

However, in any case, first, the ILB is performed, and then the OLB is performed.Therefore, the tape carrier is interposed between the ILB and the OLB to relay the connection between the chip and the package on which the chip is mounted. It can be said that it is a member that does.

The TAB lead fixed to the bump provided on the chip in the ILB process is connected to an object to be connected in the next OLB process, and one chip is mounted thereon. There is a member called a package mounted on a board or the like, a member called a substrate used when a plurality of chips are mounted (hereinafter, collectively referred to as a package).

The number of lead terminals (bumps) derived from the chip is increasing with the increase in the density and integration of the elements provided on the chip. Naturally, the lead terminals and the ILB are formed. In addition, the TAB lead in the relay where the package and OLB are made is becoming thinner and more numerous.

Along with this, wiring patterns such as lead patterns provided on packages have exceeded the limits of patterning technology using conventional thick film forming technology, and so-called thin film forming technology using thin film forming technology that allows finer pattern configuration. Multilayer patterning techniques are being used.

On the other hand, the package structure is a so-called PGA (PGA) in which a lead pattern for mounting a chip is wired on the front side and metal pins are arranged in a grid on the back side.
in Grid Array) has been increasingly used.

This PGA is suitable for mounting a chip with a high degree of integration and a large number of terminals. A pin as thin as a hair, for example, having a thickness of 0.2 mm, a pitch of 0.6 mm, and a number of 500, becomes a terminal when this PGA is mounted on a printed board or the like.

 FIG. 5 is a perspective view of an example of a PGA package.

In FIG. 1, a package 1 is made of plastic or the like, but is generally composed of a substrate 2 made of ceramic such as Al ₂ O ₃ or AlN. When the mounted chip has a large number of lead terminals such as an LSI, for example, the wiring pattern 4 is provided on the front side of the substrate 2 and sometimes multilayer wiring is performed.

On the top layer, if you fall down, dozens of leads connected to OLB and hundreds of lead patterns if there are many
10 is provided so as to surround the periphery of the substrate 2.

Although not shown here, a metallized sealing portion 14 is provided around the outer periphery of the substrate 2 to braze the cap if necessary. The sealing portion 14 is made of, for example, NiCr / Au if it is folded down, and is formed together in the step of providing the wiring pattern 4.

Further, on the back side of the substrate 2, several tens to hundreds of pins 7 are provided when the number is large.

 FIG. 6 is a partially enlarged perspective view of the back side of FIG.

In the figure, the substrate 2 of the package 1 is provided with several tens to several hundreds of via holes 5 in a lattice shape when the number is large.

The via hole 5 is, for example, a hole having a diameter of 0.1 mm and is filled with, for example, a W-based heat-resistant conductive paste or the like.

Pads 6 for soldering the pins 7 are respectively provided in the openings on the back side of the via holes 5.
It is connected to and provided.

Therefore, when the number of the pads 6 is large from several tens to several hundreds, the pads 6 are arranged in a grid like the via holes 5.

Conventionally, the pad 6 is formed of a thick film or a thin film.

For thick films, for example, by screen printing
For example, it is formed of a W-based or Mo-based paste, and if it is a thin film, a metal pad is formed by vapor deposition or sputtering.

In this case, a so-called sputtered layer, for example, in which NiCr is first coated to form a base, and a thin Au film is coated thereon
It is formed of NiCr / Au thin film.

On the pad 6 thus formed, a metal pin 7 made of, for example, permalloy (trademark of Fe / Ni alloy) is fixed.

When the pad 6 is formed of a thick film, the pin 7 is fixed by brazing using, for example, silver brazing.

On the other hand, when the pad 6 is formed of a thin film, a so-called hard solder having a melting temperature of 800 ° C. or more, such as silver solder, is difficult to apply. For example, a soft solder having a low melting temperature such as PbSn is used. It has been done by so-called soldering.

FIG. 7 is a sectional view showing the structure of a conventional method of providing pins.

In the figure, 2 is a substrate, 5 is a via hole, 6 is a pad, 7
Is pin, 8 is brazing material, 81 is silver brazing material, 10 is Ni / A
u plating film.

The substrate 2 is provided with tens to hundreds of via holes 5 in a lattice shape.

For example, a W-based paste is buried in the via hole 5 to establish electrical continuity with the wiring pattern on the front side of the substrate 2. A pad 6 is provided so as to be connected to the via hole 5.

The pad 6 is formed, for example, by screen-printing a W-based paste.

If the paste embedded in the via hole 5 and the paste forming the pad 6 are the same, both pastes are fired together.

A pin 7 made of, for example, permalloy is soldered to the pad 6 by a silver solder 81. This brazing is for example 850
Performed in an oven at ℃.

After that, for example, Ni plating is applied to the base, and a Ni / Au plating film 10 coated with Au is provided thereon.
Is completed.

FIG. 8 is a cross-sectional view of another conventional example of a method of providing pins.

The numbers in the figure are the same as those in FIG. 7, and 9 is a solder dam.

In the brazing of the silver brazing material 81, for example, an inorganic flux of ammonium chloride or the like is used so that the silver brazing material 81 flows well and the root portion of the pin is well wet and covered. However, on the back surface of the substrate 2, not only the pads 6 are arranged in a grid pattern, but also a wiring pattern is provided on the back surface depending on the type of package.

Therefore, except for the pad 6, the exposed surface where the brazing material 8 flows and is not desired to be adhered is covered with a weir for stopping the flow of the brazing material before soldering, that is, a so-called solder dam 9. .

The solder dam 9 needs to withstand the soldering temperature of the pin 7 and is a so-called glass dam using a glass paste, which is patterned by screen printing and then fired.

Thereafter, a plating film 10 is provided. Since the solder dam 9 is firmly fixed to the substrate 2, plating can be performed as it is.

That is, the pad 6 is surrounded by the solder dam 9 and the pin 7
Is soldered using a silver solder 81 to provide a Ni / Au plating film 10.

 Thus, the step of providing the pins 7 on the substrate 2 is completed.

As described above, when the degree of integration of the semiconductor chip mounted on the PGA package is not so large, and therefore the number of leads to be derived is several tens, pads are formed using a thick film forming technique, and pins are formed on the pads. A so-called glass dam formed by soldering or using a thick film glass paste for a solder dam can be used.

However, when the degree of integration of the semiconductor chip to be mounted is increased and the number of leads to be led out is hundreds, the number of pads is increased, the shape is reduced, and the density is increased. Providing pads by membrane,
Making a solder dam is out of hand.
Then, it is shifting to a thin film.

[Problems to be solved by the invention]

In providing the pins on the PGA package, it was necessary to use a hard brazing material having a high melting temperature such as silver brazing for the subsequent assembly process.

Otherwise, it is necessary to change the specifications of various processes to provide wiring patterns on the PGA, bond chips, seal with caps, and provide heat sinks and radiating fins to complete semiconductor devices. Disappears.

However, the conventional PGA package was provided using a thick film regardless of whether it was a pad or a solder dam, so there was no inconvenience.

However, the number of pins provided on the PGA package has increased, and both the pads and the solder dams have exceeded the limit that can be formed using a thick film as in the past, and have to be formed with a thin film.

However, when providing the pins in the PGA package, if the process of forming a thick film is replaced with the process of forming a thin film, a fatal obstacle occurs.

In other words, when soldering is performed without providing a solder dam and the brazing material spreads to the periphery of the pad, stress concentrates on the periphery of the pad, causing micro cracks in the package substrate, and eventually the pad peels off with the substrate. There was a problem that would.

In addition, since the solder dam provided by the thin film has less tight adhesion to the substrate than the thick film, when performing plating,
There has been a problem that the plating solution peels off or the plating solution intrudes into a gap between the substrate and causes a trouble later.

An object of the present invention is to provide a method in which a pad for soldering a pin and a solder dam provided on a PGA package constituting a semiconductor device are provided by a thin film forming technique, and the soldering of pins can be performed by a hard solder material such as silver solder. It is an object.

[Means for solving the problem]

The above-mentioned problem is solved by a method of manufacturing a semiconductor device having a package in which a semiconductor chip is mounted on a surface of a substrate and a pin is erected on each of a plurality of pads on the back side of the substrate. A pad connected to each of the plurality of via holes is provided on the back surface of the substrate by a thin film forming technique. A solder resist film made of a vitreous material is formed on the entire surface of the substrate provided with the pad by the thin film forming technique. A solder dam is provided by photo-etching the solder resist film so that a peripheral portion of the pad is covered with the solder resist film and a central portion is exposed, and a pin is brazed to the pad with a brazing material. The solder dam is removed, and a peripheral portion of the pad, a brazing material, and a pin are covered with a plating film. It is solved by the method for manufacturing a semiconductor device comprising a di.

(Operation)

As described above, the number of pins implanted in a PGA package is also increasing, and the number of pads to which the pins are soldered and the fine dimensions are limited by the conventional thick film forming technology. In contrast to getting out of hand, in the present invention, this is formed by a thin film forming technique.

That is, in the present invention, a so-called Au thin film is coated on a NiCr base, for example, so that conduction can be obtained in via holes provided in a lattice on the package substrate.
NiCr / Au thin film pads are provided by thin films.

Then, when brazing pins to this pad,
A heat-resistant vitreous material such as SiO ₂ is used as a solder resist film for the brazing material, and a so-called solder dam that covers portions where the brazing material does not want to flow is provided using thin film forming technology and photo etching technology. ing.

When installing this solder dam, since it is not firmly baked on the substrate like a thick film and does not have strong adhesion strength, stress is applied especially to the peripheral edge of the pad, and a fine crack is formed in the substrate, and eventually In order to prevent the entire substrate from being peeled off, the entire surface is covered with a solder resist film and then etched.

By this etching, only the central portion of the pad to which the pin is soldered is exposed, and the peripheral portion is covered with the solder resist film.

According to the solder dam formed in this way, even if a brazing material such as a silver brazing material having a high processing temperature and a large distortion is used,
Since the brazing material does not flow to the periphery of the pad covered by the solder dam, stress is not concentrated on the periphery of the pad.

As a result, it is possible to prevent the substrate from cracking at the periphery of the pad.

Furthermore, the solder dam formed by this thin film
Since the adhesion to the substrate is not as good as that of a thick solder dam, the pins are peeled off by etching after the pins are soldered to the pads.

Thereafter, the pad, the brazing material and the pin are covered by Ni / Au plating or the like.

Thus, the pins can be brazed using the same brazing material as in the case of the conventional thick film pad.

〔Example〕

FIG. 1 is an explanatory view of an embodiment of the present invention, FIG. 2 is a manufacturing process diagram by a partially enlarged sectional view of FIG. 1, FIG. 3 is a perspective view of an example of a semiconductor device according to the present invention, and FIG. FIG. 3 is a partially enlarged sectional view of FIG. 3.

In FIG. 1, when the package 1 is viewed from the back side of the substrate 2, pins 7 are erected on pads 6 arranged in a grid at a pitch of at most 1 mm.

The substrate 2 is made of, for example, a ceramic such as Al ₂ O ₃ or AlN, and has a thickness of, for example, 0.6 mmφ.

Then, a thin film of NiCr or Cu is provided on the substrate 2 by, for example, sputtering so that conduction with the via hole 5 can be obtained as a base film for gluing, for example, and then a thin film of Au or Ni is formed thereon. The two layers are stacked to form a pad, and the pad 6 is formed by photoetching.

The shape of the pad 6 is generally circular, and 500
When a large number of such pads are provided, the size of the pad 6 is 1 mmφ or less, such as 0.5 mmφ or 0.7 mmφ.

 The pins 7 are soldered to the pads 6 one by one.

This pin 7 is made of, for example, Ni-plated permalloy.
Made of Ni-plated BeCu, Ni-plated W, etc. And when the number becomes 500, for example, 0.1 mmφ
Or 0.2mmφ. In addition, the length of the pin 7 is, for example, 1.0 mm or 0.15 mmφ, and is often shaped into a nail head (a nail head) so that it can be stably brazed to the pad 6.

FIG. 2 shows a step of brazing a pin according to the present invention.

FIG. 3A shows a step of forming the pad 6, in which a thin film of Au is provided on a NiCr thin film as a base by sputtering.

Next, in FIG. 2B, the substrate 2 provided with the pads 6 is formed.
Is provided with a solder resist film 91 on the entire back side. The solder resist film 91 is required to withstand a brazing material for use in contact for to catch pin 7 carried out in the next step, SiO ₂
By a film forming method such as evaporation or sputtering. Further, to lower the viscosity by adding a solvent to the thick film paste whose main component is SiO _2,
For example, a thin film may be applied using a spin coater.

In the next figure (C), a solder dam 9 is formed by etching the solder resist film 91.

The solder dam 9 has a central part 62 of the pad 6 exposed to solder the pin 7 and a peripheral part 61 of the pad 6.
A hole is dug in the inner race than the diameter of the pad 6 so that the solder dam 9 is covered.

Since the etching performed to form the solder dam 9 uses the SiO ₂ -based solder resist film 91, it is formed by photo-etching using a hydrofluoric acid-based etching material.

Next, in FIG. 3D, the pin 7 is put up on the central portion 62 of the pad 6 and brazing is performed.

For the brazing of the pin 7, for example, an inorganic flux of ammonium chloride or the like is used in order to allow the brazing material 8 to well pass over the nail head of the pin 7. Then, silver brazing is used for the brazing material 8, for example, 850 ° C.
In a furnace.

When the soldering of the pin 7 is completed, the solder dam 9
Is removed, and a cross-sectional configuration as shown in FIG.

Since the brazing material 8 is not coated on the peripheral portion 61 of the pad 6, a structure is not applied in which the pad 6 is wound around the peripheral portion 61 and peeled off.

Finally, plating is applied to the exposed peripheral portion 61 of the pad 6, the brazing material 8 and the pins 7, and the plating is covered with the plating film 10.

In this plating, conduction can be obtained from the front side of the substrate 2 (not shown) through the via hole 5.
Electroplating can be selectively applied only to 61, brazing material 8 and pins 7.

The configuration of this electroplated plating film 10 is such that Ni
It has a two-layer structure in which plating is performed and Au plating is performed thereon.

Thus, the pad 6 is provided on the back side of the substrate 2 by using the thin film forming technique, the peripheral edge 61 is covered with the solder dam 9 so as not to apply the peeling stress, and the pin 7 is formed by using a hard solder such as silver solder. Is proved to be sufficiently resistant to brazing.

3 and 4, a wiring pattern 4 is provided on the front side opposite to the back side of the substrate 2 on which the pads 6 are provided. With this wiring pattern 4, the pattern arrangement of the via holes 5 rising to the front side from the pins 7 arranged in a grid on the back side of the substrate 2 is rearranged so as to be connectable to the chip 3.

The wiring pattern 4 can be formed by a thick film forming technique if the wiring density is low. However, recently, the wiring density has been increased, the line width has been reduced, and multilayer wiring has become necessary. It is made by making full use of multilayer wiring technology.

Taking the case where the chip 3 is connected by TAB as an example, the end of the wiring pattern 4 is formed so as to surround several hundreds of lead patterns 41 around the substrate 2 when the number is large. The lead pattern 41 is, for example, a thin film of Au or Al, Au
It is composed of a plating layer of Ag or Ag, or a thick film of Au-Pd or the like.

At the same time as the patterning of the wiring pattern 4, a sealing portion 14 is provided around the substrate 2. The sealing portion 14 is a metallized layer of, for example, NiCr.

 Thus, a PGA type package 1 is completed.

To complete a semiconductor device using this package 1, first, a chip 3 is mounted on the package 1. From the chip 3, for example, an Au-plated TAB lead 31 is led out corresponding to the lead pattern 41 provided on the substrate 2. The lead pattern 41 and the TAB lead 31 are bonded by thermocompression at the crimping portion 13.

This bonding is generally performed when the temperature of the substrate 2 is 250 to 4
The temperature is set at 00 ° C., which is much lower than the melting temperature of the silver solder of the brazing material of the pins 7 provided on the back side of the substrate 2. When the number is large, for example, so-called gang bonding in which all leads are connected collectively is performed using a pressure bonding head at 320 ° C.

Thus, the TAB lead 31 derived from the chip 3 becomes
From lead pattern 41 to wiring pattern 4, via hole 5
And is connected to the pin 7 and goes out.

Next, in order to protect the chip 3 from the outside atmosphere, the cap 11 is sealed and sealed.

For this sealing, first, the periphery of the package 1 and the chip 3
In the sealing part 14 provided in advance by metallizing on the back of
For example, a frame-shaped cap 11 made of Kovar (trademark of FeNiCo alloy) is sealed, and the chip 3 is completely sealed. A space formed between the substrate 2, the chip 3, and the cap 11 is filled with, for example, a nitrogen gas.

If this sealing is performed using, for example, PbSn 7-3 solder, the processing temperature is 280 ° C.

Further, it is efficient that the sealing portion 14 provided on the substrate 2 is formed by, for example, forming a NiCr thin film at the same time as forming the wiring pattern 4 at the same time.

Next, a heat sink 12 is mounted on the chip 3 in order to efficiently extract the heat generated from the chip 3 to the outside.

The heat sink 12 includes, for example, a single metal such as Mo, Cu, and Al, a ceramic such as AlN and SiC, AlSi and Cu.
When an alloy such as W is used and is made of ceramic, the crown portion 15 of the heat sink 12 is also metallized with, for example, NiCr / Au.

The heat sink 12 is located on the back side of the chip 3.
For example, it is mounted so as to cover the cap portion 11 and the cap portion 11 metallized with NiCr / Au or the like. This heat sink
For example, if 12 cappings are performed using PbSn 5-5 solder, the processing temperature can be 265 ° C.

Further, when it is necessary to improve the heat radiation, a heat radiation fin made of a metal having good thermal conductivity such as Al or Cu is provided on the heat sink 12, though not shown.

The substrate 2 of the package 1 according to the present invention includes Si
Ceramics such as C and Al ₆ Si ₂ O ₁₆ (mullite) can be used, and a CuW alloy can be used for the heat sink 12.

Further, not only the material but also various shapes and dimensions can be modified.

〔The invention's effect〕

As described above, a chip is mounted with an increase in the number of leads required for a highly integrated semiconductor chip.
Increasingly more pins are provided on PGA packages, and it becomes increasingly difficult to form pads using conventional thick film forming techniques and braze the pins to them.

On the other hand, when a hard solder such as silver solder is used for a thin-film pad, there has conventionally been a 10% failure in which the pad peels off and the pin falls off.

However, according to the present invention, when this pad is formed by a thin film forming technique, and the periphery of the pad is covered with a solder dam made of a vitreous material, and the pin is soldered with silver,
There is no obstacle for the separation of the pad and the accompanying falling off of the pin, which can greatly contribute to the improvement of the manufacturing process and the yield of the semiconductor device.

[Brief description of the drawings]

 FIG. 1 is an explanatory view of an embodiment of the present invention, FIG. 2 is a manufacturing process diagram based on a partially enlarged sectional view of FIG. 1, FIG. 3 is a perspective view of an example of a semiconductor device according to the present invention, and FIG. 3 is a partially enlarged sectional view of FIG. 3, FIG. 5 is a perspective view of an example of a PGA package, FIG. 6 is a partially enlarged perspective view of the back side of FIG. 5, and FIG. FIG. 8 is a cross-sectional view of another conventional example of a method of providing pins. In the figure, 1 is a package, 2 is a substrate, 3 is a chip, 4 is a wiring pattern, 5 is a via hole, 6 is a pad, 61 is a peripheral portion, 62 is a central portion, 7 is a pin, 8 is a brazing material, and 9 is a brazing material. Solder dam 91 is a solder resist film.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 23/12 H01L 23/50

Claims (1)

(57) [Claims] 1. A semiconductor chip (3) is mounted on the front side of a substrate (2), and pins (7) are planted on each of a plurality of pads (6) on the back side of the substrate (2). In the method for manufacturing a semiconductor device having the package (1), a pad (6) connected to each of the plurality of via holes (5) is formed on the back side of the substrate (2) by a thin film forming technique. A solder resist film (91) made of a vitreous material is provided on the entire surface of the substrate (2) on which the pad (6) is provided by a thin film forming technique, and a peripheral portion (61) of the pad (6) is provided. The solder resist film (91) is photo-etched to provide a solder dam (9) so that the central part (62) is exposed while the solder resist film (91) is covered with the solder resist film (91). The pin (7) becomes the brazing material (8) The solder dam (9) is removed, the peripheral portion (61) of the pad (6) is covered with the brazing material (8) and the pin (7) by a plating film (10), A method of manufacturing a semiconductor device, comprising a package (1) comprising: