JPH03139870A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To utterly remove the deformation or snapping of a pin so as to improve process and yield rate by making a wiring pattern on the front side of a board, and the brazing a metallic pin to the pad connected to the wiring pattern, on the reverse side using brazing material of AuGe. CONSTITUTION:Pads 6, which correspond to several tens to several hundreds of via holes 5 and are arranged in lattice shape, are provided on a board 12. Wiring patterns 4 are provided on the front side of the board 2 by film multilayer patterning, and metallic pins 7 consisting of permalloy, or the like are soldered to the pads 6 on the reverse side using AuGe brazing material 8. The brazing material 8 is of a pellet shape, and is put between the pad 6 and the pin 7. After finish of brazing, current are applied to the pad 6, the pin 7, and the AuGe brazing material 8 used for brazing through the via hole 5, whereby, for example, electric plating of Au is applied.

Description

[Detailed Description of the Invention] [Summary] This relates to a method of manufacturing a semiconductor device, and particularly relates to a brazing material used in soldering a bottle to a PGA substrate. In addition, the conventional specifications can be applied to the processing temperature of the post-soldering process.After forming the wiring pattern on the front side of the package substrate on which the semiconductor chip is mounted, A metal pin is soldered to each of a plurality of pads connected to the wiring pattern via via holes on the back side of the substrate using an AuGe brazing material.

[Industrial application field]

The present invention relates to a method for manufacturing a ceramic package on which a semiconductor chip is mounted, particularly among semiconductor devices.

In recent years, with the increase in the density of semiconductor devices, the number of terminals led out from one semiconductor device has also increased, ranging from several hundred terminals to thousands of terminals.

A silicon wafer that has undergone a wafer process is generally completed into a semiconductor device through an assembly process called a post-process and an inspection process.

In the assembly process, the wafer is first scribed and divided into chips, which are then subjected to mounting (guinea bonding), bonding, sealing, marking, and the like.

For small chips with relatively low integration density,
Many of them are mounted on a frame-shaped terminal called a lead frame, wire-bonded, and then sealed with resin.

However, when it comes to highly integrated LSI and VLSI,
The number of lead terminals derived from a single chip increases by an order of magnitude, making it difficult to connect them using wire bonding. Therefore, for example, TAB (Tape Au
Bonding to the package has come to be carried out by a method called tomated bonding.

This TAB-connected package is an element component that efficiently connects a large number of lead terminals led out from the chip and maintains high reliability. Therefore, how to configure this package is an important issue that also affects the cost of the semiconductor device itself.

[Conventional technology] The bonding process for extracting terminals from semiconductor chips is
When the number of terminals increases, wire bonding becomes unmanageable, and wireless methods that do not use wires are often used.

Wireless methods include the flip-chip method, in which a chip with bumps is placed face down and fixed directly to the board, the beam lead method, in which a chip with beam-shaped leads is placed face down and fixed directly on the board, and the chip with perforations. ) A tape carrier method is well known in which bumps provided on a chip are fixed to lead pieces provided on a long tape-shaped carrier.

Among these, the tape carrier method is a method developed for the purpose of automatic installation.
It is also called ``e.Automated Bonding''.

The TAB connection will be described below as an example.

This TAB connection is the TAB connection provided on the tape carrier.
Inner lead bonding (hereinafter abbreviated as ILB) connects the leads and bumps provided on the chip, and the TA731J-de provided on the tape carrier is connected to terminals called lead patterns provided on the package etc. It is divided into two processes: outer lead bonding (hereinafter abbreviated as OLB).

Then, a part of the tape carrier may be sealed together with the TAB lead after OLB is completed, or may be removed before 0LBO.

However, in any case, after the ILB is performed, the OL
Since B is performed, the tape carrier has ILB and OLB
It can be said that it is a member that intervenes between the chip and the package in which it is mounted.

Then, one chip is mounted on the object to which the TAB lead fixed to the bump provided on the chip in the TLB process is connected in the next OLB process, and it is connected to another object, for example, There are members called packages that are mounted on printed boards and the like, and members called substrates that are used when multiple chips are mounted (hereinafter collectively referred to as packages).

With the increasing density and integration of elements provided on chips, the number of lead terminals (bumps) led out from the chip is increasing, and as a matter of course, the number of lead terminals (bumps) leading out from the chip is increasing, and as a matter of course, the lead terminals and ILBs are connected to each other and packaged. Intermediate TAB leads used for OLB are also becoming thinner and thinner, and the number of leads is also increasing.

Along with this, wiring patterns such as lead patterns provided on packages in which chips are mounted have exceeded the limits of patterning technology that uses conventional thick film technology, and are now using thin film technology that can create more detailed patterns. , so-called thin film multilayer patterning has come to be used.

On the other hand, the structure of the package is so-called "P", in which the lead pattern on which the chip is mounted is wired in multiple layers on the front side, and metal bottles are arranged in a grid pattern on the back side.
It has a configuration called GA (Pin Grid Array).

This PGA is suitable for mounting chips with high density and a large number of terminals.For example, the thickness is 0.2 mmφ and the pitch is 0.
．． The hair-thin pins, 6 mm in length and 500 in number, serve as terminals when this PGA is mounted on a printed board or the like.

FIG. 6 is a perspective view of an example of a PGA.

In the figure, a package 1 is made of a substrate 2 made of ceramic such as AA20ff or AIN, although it may be made of plastic or the like. When the chip to be mounted has a large number of lead-out terminals, such as an LSI, a wiring pattern 4 is provided on the front side of the substrate 2 using, for example, a thin film forming technique, and sometimes multilayer wiring is formed.

Then, on the top layer, there are provided lead patterns 10 of several tens to hundreds in number, which are connected to the leads by an OLB, for example.

Further, around the substrate 2, a metalized capping portion 17 is provided for soldering a cap (not shown). This crown attachment part 17 is made of, for example, NiCr/A.
U, etc., and are made together in the process of providing the wiring pattern 4.

Further, on the back side of the substrate 2, there are provided pins 7 ranging from several tens to several hundreds in number.

FIG. 7 is a partially enlarged perspective view of the back side of FIG. 6.

In the figure, a substrate 2 of a package 1 is provided with several tens to hundreds of via holes 5 in a grid pattern. This via hole 5 is, for example, 100 μmφ.
The holes are filled with, for example, a W-based conductive paste with excellent heat resistance, so that conduction can be established through the front and back surfaces of the substrate 2.

Pads 6 for soldering pins 7 are provided in the openings on the back side of the via holes 5 to be connected to the via holes 5, respectively.

The pads 6 arranged in a lattice pattern corresponding to the dozens to hundreds of via holes 5 each have a
A pin 7 made of metal such as Permalloy (trademark of Fe-Ni alloy) is soldered with a brazing material 81 such as silver solder.

Therefore, this pad 6 is made of, for example, a W-based paste so as to withstand the processing temperature of the brazing material 81 when the pin 7 is soldered.

On the other hand, each pin 7 soldered to the pad 6 is connected to the wiring pattern 4 on the front side through a via hole 5 penetrating the substrate 2. Since this via hole 5 also requires heat resistance, it is filled with, for example, a W-based paste.

Here, brazing materials such as silver solder with a melting point of 450°C or higher are hard solders, and AuSn or Pb with a melting point of 450°C or lower are
5n is a soft solder, commonly called solder. Therefore, in the case of the conventional package l, the via holes 5 and pads 6 are first provided with a high sintering temperature paste such as W-based paste, and the pads 6 are pinned with a hard soldering material such as silver solder. 7 is a soldered configuration. In any case, the firing temperature is high, for example 700 degrees, so in the conventional semiconductor device assembly process, the via holes 5 and pads 6 are formed using thick film paste, and the pads 6 are made of hard soldering material. The process of soldering the pin 7 is performed first.

In this way, the huge number of terminals led out from the semiconductor chip are bonded to the lead pattern provided on the front side of the package via multiple TAB leads corresponding to the number of terminals, and then passed through the via hole to the back side of the package. It is designed to be rotated around and taken out to the outside via a pin.

By the way, in a semiconductor device in which a chip is mounted on a PGA, in addition to soldering the pins to the PGA package,
There are things like thermocompression bonding to bond the chip to the package, and soldering of the cap to protect the chip from the outside air.
Alternatively, a heat sink or heat dissipating fins may be soldered to dissipate heat from the chip.

FIG. 8 shows a cross-sectional view of the configuration of an example of a PGA Jihad type semiconductor device.

In the same figure, ■ is the package, 2 is the substrate of package 1, 3 is the chip, 7 is the pin, 11 is the cap, 12 is the heat sink, 13 is the heat dissipation fin, and 3 is the TA.
This is an example of a typical configuration connected via a BIJ-doard 14.

The joints to be soldered, thermocompressed, or glued in the second step are: ■ The soldering part 15 that connects the pad 6 and the pin 7 provided on the back side of the board 2, ■ The soldering part 15 that is led out from the chip 3. TAB lead 14 and base Fi2
A crimping part 16 that thermocompresses the lead pattern 10 provided on the front side of the metallized base Ifi2; ■ A sealing part 17 that seals the cap 11 to the front side of the metallized base Ifi2; (1) An adhesive part 19 for soldering or bonding the heat sink 12 and the radiation fins 13 together.

The processing temperature for these soldering, thermocompression bonding, and bonding must be low enough to be used in later stages of the assembly process for finishing the semiconductor device. Furthermore, when the wiring pattern 4 provided on the substrate 2 has a thin film structure and multilayer wiring is performed using thin film multilayer technology, an organic insulating material such as polyimide is used for the insulating layer. The heat resistance of the materials that make up these packages must also be considered.

FIG. 5 is an assembly process diagram of a conventional manufacturing method.

In the same figure, the method of constructing the package is carried out in consideration of the processing temperature conditions of the respective joints corresponding to the numbers ① to ② above.

That is, in the first step, pins are soldered to the back side of the board.

Next, a wiring pattern such as a lead pattern is provided on the front side of the substrate, for example, a thin film patterning process is performed, and then the processes after thermocompression bonding of the chip are performed.

When soldering the pins, a silver solder with a high melting temperature of around 700° C. is used as the soldering material. Also,
A so-called solder dam, which is a so-called enclosure provided to prevent the brazing filler metal from flowing into an unnecessary area, is made of a material having heat resistance that can withstand the melting temperature of the brazing filler metal, such as Sin.

Therefore, in the conventional assembly process in which the pins are soldered first, problems related to processing temperature do not occur in the other bonding processes (1) to (4) or in the process of forming thin film multilayer wiring.

However, as mentioned above, the pins provided on the backside of PGAs tend to become thinner and thinner, and using a substrate to which these pins are already soldered makes it difficult to perform thin-film patterning work, especially in multi-layer, which is a complicated process. When patterning a structure, pins often become bent or broken.

Another method is to solder the pins with, for example, Au
This method uses a soft brazing filler metal with a low melting temperature, such as n.

In this case, the pins can be soldered after the thin film buttering process is completed, but since the melting temperature of the brazing filler metal is low, the processing temperature in each joining process of Choices are severely restricted.

[Problem to be solved by the invention]

As described above, in the conventional semiconductor device assembly process, pins are first provided on the back side of the package substrate in the first step. Silver solder, which has a high melting temperature, was used to solder these pins. Therefore, there is no problem with various heat treatments performed in post-processes after soldering the pins, which is convenient.

However, when patterning a thin film for TAB connection on a board to which pins are soldered, it is extremely difficult to do so without damaging the thin and large number of pins, and they may become bent. There was a problem with it breaking.

In the method of brazing the pins after the thin film buttering process using a soft brazing material with a low melting temperature,
Processing temperatures in other steps are subject to significant restrictions. As a result, there was a problem in that the brazing material and processing temperature conditions were not compatible with each other.

In the manufacturing process of a semiconductor device, the present invention performs soldering of pins after wiring a thin film pattern provided on a substrate of a package on which a chip is mounted. The purpose is to provide a manufacturing method that can be applied to conventional specifications.

[Means to solve the problem]

The problem described above is that after a wiring pattern is formed on the front side of a substrate of a package on which a semiconductor chip is mounted, a plurality of pads connected to the wiring pattern through via holes on the back side of the substrate are formed. This problem is solved by a method of manufacturing a semiconductor device in which metal pins are soldered using an AuGe brazing material.

[For production]

As described above, in the present invention, after the wiring pattern is formed, the pins are soldered using AuGe brazing material.

In other words, in the present invention, the brazing material used to braze the pins after forming the wiring pattern should be at a low temperature that does not affect the wiring pattern, especially a multilayer thin film pattern (below 400°C, which is the heat-resistant temperature of polyimide used as an interlayer insulating film). It is a brazing material that can be soldered at a low temperature of 330°C, which is the sealing temperature of sealing brazing materials such as AuSn and Pb5n that are conventionally used for soldering caps and heat sinks. It is a brazing material that can be soldered at a higher temperature.

Among brazing materials that satisfy such brazing conditions, particularly when using AuGe having a melting temperature of 356° C., superior brazing can be achieved compared to other brazing materials.

Furthermore, since the melting temperature of the AuGe brazing material of the present invention is lower than the heat resistance temperature of polyimide, polyimide can be used not only as an insulating film between the eyebrows of wiring patterns, but also as a solder dam to prevent unnecessary flow of the brazing material. can.

Furthermore, if the pins and pads provided on the substrate for soldering the pins are plated with Au in advance, strong soldering with good wettability can be achieved without using flux for soldering.

[Example] Figure 1 is a perspective view of the main parts explaining the present invention, Figure 2 is an assembly process diagram of the manufacturing method of the present invention, Figure 3 is an explanatory diagram of the first embodiment of the present invention, FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

In FIG. 1, the substrate 2 of the package 1 is, for example, an AI
It is N ceramic. Then, dozens to hundreds of via holes 5 are provided in a grid pattern, penetrating the front and back sides of the substrate 2.

This via hole 5 is, for example, a hole of 100 μmφ and W
A conductive paste such as a base material, a Mo-based material, an Ag-based material, a Cu-based material, or the like is embedded to penetrate the front and back surfaces of the substrate 2 to establish electrical conduction. Since the via hole 5 is small, a vacuum suction method or the like is used for filling the conductive paste.

On the other hand, in the opening on the back side of the via hole 5, a pad 6 having a diameter of 500 μm, for example, is provided in connection with the via hole 5 in order to solder the pin 7 thereto. After filling the via hole 5 with a conductive paste, the pad 6 is patterned by, for example, screen printing using the same conductive paste used to fill the via hole 5, and is sintered together with the via hole 5.

In this way, the substrate 2 is provided with pads 6 arranged in a lattice pattern corresponding to dozens to hundreds of via holes 5.

The substrate 2 provided with the via hole 5 and the pad 6 has a second
As shown in the assembly process according to the present invention in the figure, first, the wiring pattern 4 is formed. A feature of the manufacturing method of the present invention is that this wiring pattern 4 forming step is performed first.

The wiring pattern 4 is formed on the front side of the substrate 2, but when the number of via holes 5 is small and complicated multilayer wiring is not required, patterning can be performed using a thick film technique with a simple process.

However, when the number of terminals led out from the chip 3 is large, such as several hundred, and the number of via holes 5 is also necessarily large, the wiring pattern 4 is formed by thin film multilayer patterning technology.

Thin film multilayer patterning uses, for example, a spin-coated polyimide film as an interlayer insulating film, and NiCr/NiCr/
This is carried out using a thin film such as Au as a conductor film. Also,
At the same time as the wiring pattern 4 is formed, a pattern (sealing portion 17) for sealing the cap 11 around the substrate 2 may also be formed. Then, the front side of the substrate 2 is
If the conductive paste protrudes like a ridge from the opening of the via hole 5, it is polished once before patterning.

As described above, in the manufacturing method of the present invention, first, the wiring pattern 4 is formed on the front side of the substrate 2 by thin film multilayer patterning, and then the pins 7 are formed on the back side of the substrate 2.
It is characterized by the use of solder welding.

That is, a metal pin 7 made of permalloy or the like and having a diameter of 150 μm and a length of 1 mm, for example, is soldered to the pad 6 on the back side of the substrate 2 on which the wiring pattern 4 has been formed using an AuGe brazing material 8.

Example = 1 In Fig. 3, the pin 7 is made of par 7Cl and has a diameter L50 amφ and a length 1 or 2 mm, and is shaped into a nail head (nail head) shape of 300 μmφ.

Figure (A) shows the relationship between the pad 6, pin 7, and AuGe brazing material 8 before sintering.

The AuGe brazing material 8 has a thickness of 150 μm and a diameter of 450 μm.
It is formed into a pellet of μmφ and held between a pad 6 and a pin 7. Generally, the pads 6 arranged in a lattice pattern have a narrow pitch of, for example, 1++un, so this clamping operation is performed by supporting the pins 7 all at once, or by supporting the pins 7 all at once, or by A jig is used to automatically place the brazing filler metal 8 on the pad 6.

Then, it is placed in a hydrogen furnace with a reducing atmosphere set at a temperature of 380° C. and heated for 30 minutes, and when the AuGe brazing material 8 is sufficiently melted, it is taken out and returned to room temperature, thereby completing (1) brazing.

As shown in the same figure (B), after sintering, the AuGe brazing material 8
In order to ensure that the flux reaches the top of the nail head of the pin 7, an inorganic flux such as ammonium chloride is used.

After soldering of the pin 7 is completed, conduction is established between the pad 6, the pin 7, and the AuG brazing material 8 used for soldering through the via hole 5, and electroplating of, for example, Au is performed.

Example: 2 In FIG. 4, pad 6 and pin 7 are plated with Au in advance.

On the nail head part of pin 7 processed in the same manner as in Example 1,
First, apply rosin-based organic flux.
Pre-brazing is carried out by immersing it in a bath of AuGe brazing material 8 which is molten at 70°C.

After that, apply rosin flux to pad 6 and pin 7.
While applying a pre-pressure so that the pad 6 is pressed down, it is placed in a hydrogen furnace with an internal temperature of 365° C. and heated for 30 minutes, and when the AuGe brazing material 8 is sufficiently melted, it is taken out. In this way, the soldering of pin 7 is completed.

Example: 3 In FIG. 1, a polyimide coating film with a thickness of 4.5 μm is applied using a spin coater on the back side of the package l on which the Au-plated pad 6 is provided, and the coating film is applied to the pad 6. It was etched using hydrazine to expose the face and was made into solder dam 9.

The solder dam 9 covers and dams the area where the solder metal does not want to flow.

As in Example 2, apply rosin flux to pad 6. Further, AuC; e brazing material 8 is pre-brazed to the pin 7 which has been previously plated with Au. While applying preload so that the pin 7 presses down the pad 6, the furnace temperature is increased to 365°C.
The Au
When the Ge brazing filler metal 8 is sufficiently melted, it is taken out. After cooling in this way, the brazing process is completed.

If, for example, Au plating is to be performed on the pad 6, pin 7, and AuGe brazing material 8 after soldering, the polyimide coating forming the solder dam 9 is peeled off using, for example, hydrazine. Sometimes.

Comparative Example: Brazing was performed in the same manner as in Example 1 using AuSi brazing material. The melting temperature of AuSi brazing material is the eutectic temperature 363
°CT: Since it is close to AuGe brazing material 8, the temperature conditions are suitable.

This AuSi brazing material has a thickness of 150 μm and a diameter of 45 μm.
When the AuSi brazing material was made into a pellet shape with a diameter of 0 μm and sandwiched between the pad 6 and the pin 7, and soldered according to the same specifications as in Example 1, the AuSi brazing material had poor wettability. It cannot be applied to soldering of very fine parts such as the pin 7.

In Examples 1, 2, and 3, the wiring pattern 4 of the thin film multilayer already provided on the substrate 2 is not disturbed in any way.
Pin 7 can be soldered.

Further, in general, it is difficult to completely clean soldering flux, and if it remains, it may cause problems such as corrosion, so it is preferable not to use it. Therefore, since the AuGe brazing material 8 has good wettability, if the pads 6 and pins 7 have been previously plated with Au, flux for the soldering layer may not be used.

Further, in the third embodiment, since it is possible to use a polyimide coating film for the solder dam 9, it is possible to cover the portions where the solder material is not desired to flow through an extremely simple process.

Furthermore, the wiring pattern 4 is difficult with the base Fi2 with pin 7.
Since the forming process is not performed, but is performed in a process prior to soldering, problems such as deformation and breakage of the pin 7, which occur in about 10% of cases in conventional processes, are completely eliminated. In this way, package 1 is completed.

Taking the assembly process shown in FIG. 2 and the configuration shown in FIG. be done. Then, the chip 3 is subjected to (1) TAB connection by thermocompression bonding at the compression bonding portion 16 composed of the lead pattern IO provided on the package l by forming the wiring pattern 4 and the T A B +J-dead 14 .

In this (1) thermocompression bonding, a 320° C. pressure bonding head is used to connect all the leads at once, ie, so-called gigantic bonding.

Next, a frame-shaped cap 11 made of, for example, Kovar (trademark of FeNiCo alloy) is attached to the sealing part 17 provided around the substrate 2 using 7-3 Pb5n solder.
■ Crown at a temperature of °C.

This sealing part 17 may be formed by metallizing NiCr/Au at the same time as, for example, forming the wiring pattern 4, which is more efficient than forming a thick film in a separate process.

Next, the heat sink 12 is made of, for example, an Aj2Si alloy, and the bonding surface is metalized with NiCr/Au. This heat sink 12, the back surface of the chip 3 metalized with NiCr/Au, and the cap 11 are each attached to the cap attachment portion 1B at a temperature of 265° C. using Pb5n 5-5 solder.

Finally, place the heat dissipation fin I3 made of, for example, Af on the heat sink 12 using an epoxy thermosetting adhesive.
■Cure and adhere at a temperature of 0°C.

In this way, the wiring pattern 4 is first formed on the front side of the substrate 2 of the package l, and then the pins 7 are soldered to the back side of the substrate 2 using the AuGe brazing material 8, which is the reverse process of the conventional process. We were able to fabricate a semiconductor device using a new manufacturing method that allows conventional processes to be applied to subsequent steps.

Note that the substrate 2 of the package 1 in the present invention includes A1
203, Alh S 120rb (mullite), etc. can also be used, the heat sink 12 can be made of CuW alloy, etc., and the heat sink 13 can be made of C.
U, etc. can also be used, and various modifications can be made not only to the materials constituting them but also to their shapes and dimensions.

Also, pin 7 is attached to package 1 using AuGe brazing material 8.
■Assembling processes other than soldering include ■thermo-compression bonding, ■crown bonding,
It is sufficient that the processing temperature is lower in the order of (1) crowning and (2) adhesion, and various modifications are possible.

Furthermore, (1) adhesion between the heat sink 12 and the radiation fins I3 can be performed in advance by soldering or adhesion at a higher processing temperature than (2) crown bonding.

[Effects of the Invention] As described above, according to the pin brazing method using AuGe brazing material according to the present invention, it is possible to solder a pin using AuGe brazing material, which does not affect the wiring pattern provided on the front side of the PGA board, for example, using polyimide. Since soldering can be performed at a temperature lower than the heat-resistant temperature of 400°C, the wiring pattern can be formed before soldering the pins.

On the other hand, soldering of caps, heat sinks, etc. can be performed at a temperature higher than 330° C., which is the sealing temperature of conventionally used sealing brazing materials such as AuSn and Pb5n.

Therefore, there will be no deformation or breakage of the pins, which was inevitable during the assembly process to form the wiring pattern on the front side of the PGA board, which has an increasingly increasing number and thinner pins on the back side. .

In this manner, the present invention can greatly contribute to improving the manufacturing process and yield of semiconductor devices.

[Brief explanation of the drawing]

Figure 1 is a perspective view of the main parts explaining the present invention, Figure 2 is an assembly process diagram of the manufacturing method of the present invention, Figure 3 is an explanatory diagram of the first embodiment of the present invention, and Figure 4 is the main part of the book. 5 is an assembly process diagram of a conventional manufacturing method. FIG. 6 is a perspective view of an example of PGA. FIG. 7 is a partially enlarged perspective view of FIG. 6. 2 is a cross-sectional view of the structure of an example of a PGA-mounted semiconductor device. In the figure, ■ is a package, 2 is a substrate, 3 is a chip, 4 is a wiring pattern, 5 is a via hole, 6 is a pad, 7 is a pin,
8 is an AuGe brazing material, and 9 is a solder dam. 18 children 9 shaku theory θ Hijiro Seiden Oo oblique nekiki 1
Notes (Elliptical engineering) Invention 1; 7-filament manufacturing method/) Guidance and construction notes No. 2
Old (A) Sintering @ (E3) #g reconnaissance 4 and Sun Moon O Houki-I Fu 9F Ji 421 Theory B Moon Melon] No.
3 Kuchijusaya Sun Moon 2nd/) r loquat 1 word is aF4 PCrA/)
-JlnJjPF view map book C Grandma's work 1 return/') made by Idan Tate Nio in the evening on the right side 15 Partially enlarged back side of Figure 16 7 l

Claims (1)

[Claims] The substrate of the package (1) on which the semiconductor chip is mounted (
After forming a wiring pattern (4) on the front side of the substrate (2), a plurality of pads (4) connected to the wiring pattern (4) through via holes (5) on the back side of the substrate (2)
6), attach the metal pin (7) to the AuGe brazing material (8).
1. A method of manufacturing a semiconductor device, characterized in that soldering is performed using a method of manufacturing a semiconductor device.