JPH08255803A - Semiconductor module and manufacture thereof - Google Patents

Semiconductor module and manufacture thereof

Info

Publication number
JPH08255803A
JPH08255803A JP7056930A JP5693095A JPH08255803A JP H08255803 A JPH08255803 A JP H08255803A JP 7056930 A JP7056930 A JP 7056930A JP 5693095 A JP5693095 A JP 5693095A JP H08255803 A JPH08255803 A JP H08255803A
Authority
JP
Japan
Prior art keywords
chip
semiconductor chip
module substrate
semiconductor
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7056930A
Other languages
Japanese (ja)
Inventor
Hajime Kato
肇 河東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7056930A priority Critical patent/JPH08255803A/en
Publication of JPH08255803A publication Critical patent/JPH08255803A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To provide a manufacturing method of a semiconductor module on which the repair work for chip replacement can be performed easily. CONSTITUTION: First, a semiconductor chip 3 is tacked by vacuum sucking force to the aperture part 1a of a module substrate 1, and the semiconductor chip 3 and the conductor pattern of the module substrate 1 are connected by a wire 4 in the above-mentioned state. Then,the semiconductor chip 3 is permanently fixed to the module substrate 1 by resin-sealing on the wire connection side of the semiconductor chip 4.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、モジュール基板上に半
導体チップを実装してなる半導体モジュール及びその製
造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module having a semiconductor chip mounted on a module substrate and a method for manufacturing the same.

【0002】[0002]

【従来の技術】半導体モジュールの実装形態の中には、
ウエハから個片に分割された半導体チップ(ベアチッ
プ)を直に基板上に実装するダイレクトボンディングと
呼ばれるタイプがある。従来、この種の半導体モジュー
ルを製造するにあたっては、図4に示すように、基板1
上のボンディングパッド(不図示)にダイボンド剤2を
介して半導体チップ3を接合する。次に、モジュール基
板1上に形成された導体パターン(不図示)と半導体チ
ップ3とを金線等のワイヤ4にて接続し、その後、チッ
プコート樹脂5によって半導体チップ3を封止する。
2. Description of the Related Art Among the mounting forms of semiconductor modules,
There is a type called direct bonding in which a semiconductor chip (bare chip) divided into individual pieces from a wafer is directly mounted on a substrate. Conventionally, when manufacturing a semiconductor module of this type, as shown in FIG.
The semiconductor chip 3 is bonded to the upper bonding pad (not shown) via the die bonding agent 2. Next, the conductor pattern (not shown) formed on the module substrate 1 and the semiconductor chip 3 are connected by the wire 4 such as a gold wire, and then the semiconductor chip 3 is sealed with the chip coat resin 5.

【0003】[0003]

【発明が解決しようとする課題】しかしながら上記従来
の製造方法においては、モジュール基板1にダイボンド
剤2で半導体チップ3を固定したのち、モジュール基板
1の導体パターンと半導体チップ3とをワイヤ4にて接
続するため、以下のような不都合があった。すなわち、
マルチチップモジュール等の如きモジュール基板1上に
複数個の半導体チップ3を実装する場合では、1個の不
良チップによってモジュール全体が不良となるため、ワ
イヤボンディング後の特性測定で不良チップが検出され
た場合、不良チップを良品チップに交換するための補修
作業が行われることがある。こうした補修作業では、既
にダイボンド剤2によって固定された不良チップをモジ
ュール基板1から強引に引き剥がすことになるため、作
業中に誤ってモジュール基板1や他の半導体チップ3を
傷つけるなどの二次不良を引き起こす虞れがあった。ま
た、不良チップの引き剥がしは勿論のこと、チップ剥離
後のボンディングパッド部を平坦化するためモジュール
基板1に残ったダイボンド剤2を除去しなければなら
ず、一連の補修作業がきわめて煩雑なものとなってい
た。
However, in the above conventional manufacturing method, the semiconductor chip 3 is fixed to the module substrate 1 by the die bonding agent 2, and then the conductor pattern of the module substrate 1 and the semiconductor chip 3 are connected by the wire 4. Because of the connection, there were the following inconveniences. That is,
When a plurality of semiconductor chips 3 are mounted on the module substrate 1 such as a multi-chip module, one defective chip causes the entire module to be defective. Therefore, defective chips are detected by the characteristic measurement after wire bonding. In this case, repair work may be performed to replace the defective chip with a good chip. In such repair work, since the defective chip already fixed by the die bond agent 2 is forcibly peeled off from the module substrate 1, a secondary defect such as scratching the module substrate 1 or another semiconductor chip 3 by mistake during the work. There was a risk of causing. In addition to peeling off the defective chip, the die bonding agent 2 remaining on the module substrate 1 must be removed in order to flatten the bonding pad portion after the chip is peeled off, and a series of repair work is extremely complicated. It was.

【0004】本発明は、上記問題を解決するためになさ
れたもので、その目的とするところは、主としてチップ
交換のための補修作業を簡易に行うことができる半導体
モジュールの製造方法を提供することにある。
The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor module, which can easily carry out repair work mainly for chip replacement. It is in.

【0005】[0005]

【課題を解決するための手段】本発明は、上記目的を達
成するためになされたもので、導体パターンが形成され
たモジュール基板の所定位置に半導体チップを実装して
なる半導体モジュールの製造方法であり、先ず、モジュ
ール基板の所定位置に半導体チップを真空吸着力により
仮固定した状態で半導体チップと導体パターンとをワイ
ヤにて接続する。その後、半導体チップのワイヤ接続面
側を樹脂封止してモジュール基板に半導体チップを本固
定する。
The present invention has been made to achieve the above object, and is a method for manufacturing a semiconductor module in which a semiconductor chip is mounted at a predetermined position on a module substrate on which a conductor pattern is formed. First, the semiconductor chip and the conductor pattern are connected by a wire in a state where the semiconductor chip is temporarily fixed by a vacuum suction force at a predetermined position on the module substrate. Then, the wire connection surface side of the semiconductor chip is resin-sealed to permanently fix the semiconductor chip to the module substrate.

【0006】[0006]

【作用】本発明に係わる半導体モジュールの製造方法に
おいては、モジュール基板の所定位置に真空吸着力によ
って半導体チップが仮固定され、この状態でモジュール
基板の導体パターンと半導体チップとがワイヤにて接続
される。ワイヤボンディング後には半導体チップのワイ
ヤ接続面側が樹脂封止され、これによってモジュール基
板の所定位置に半導体チップが本固定される。したがっ
て、ワイヤボンディング後の特性測定において不良チッ
プが検出された場合には、基板表面と直交する方向に不
良チップを押し出すだけでモジュール基板から不良チッ
プを取り外すことが可能となり、しかも不良チップを取
り外した後は従来の如くダイボンド剤等の取り除き作業
を要することなく、交換用の良品チップを実装すること
が可能となる。
In the method of manufacturing the semiconductor module according to the present invention, the semiconductor chip is temporarily fixed to a predetermined position of the module substrate by the vacuum suction force, and in this state, the conductor pattern of the module substrate and the semiconductor chip are connected by the wire. It After wire bonding, the wire connection surface side of the semiconductor chip is resin-sealed, whereby the semiconductor chip is permanently fixed at a predetermined position on the module substrate. Therefore, if a defective chip is detected in the characteristic measurement after wire bonding, it becomes possible to remove the defective chip from the module substrate simply by pushing out the defective chip in the direction orthogonal to the substrate surface. After that, a replacement good chip can be mounted without the need for removing the die bonding agent and the like as in the conventional case.

【0007】[0007]

【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明に係わる半導体モ
ジュールの製造方法の第1実施例を説明する図である。
本第1実施例においては、先ず図1(a)に示すよう
に、真空引き用の貫通孔6aを有する治具ボード6の上
面にモジュール基板1を載置する。その際、モジュール
基板1には、予めチップ実装位置に対応して例えばチッ
プ径よりも大きな開口部1aを設けておく。また、治具
ボード6にはモジュール基板1の位置決め手段(例え
ば、図示はしないが位置決めピン等)を設けておき、ボ
ード上面にモジュール基板1を載置したときに開口部1
aの略中央に貫通孔6aが位置するようにする。
Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram illustrating a first embodiment of a method of manufacturing a semiconductor module according to the present invention.
In the first embodiment, first, as shown in FIG. 1A, the module substrate 1 is placed on the upper surface of a jig board 6 having a through hole 6a for vacuuming. At that time, the module substrate 1 is provided with an opening 1a larger than, for example, the chip diameter in advance corresponding to the chip mounting position. Further, the jig board 6 is provided with a positioning means for the module substrate 1 (for example, a positioning pin (not shown)), and when the module substrate 1 is placed on the upper surface of the board, the opening 1
The through hole 6a is located substantially at the center of a.

【0008】次に、吸着コレット等によって移送した半
導体チップ3をモジュール基板1の開口部1aに配置す
る。これにより、治具ボード6の貫通孔6aの上端は半
導体チップ3の裏面によって閉塞される。このとき、治
具ボード6上に図中点線で示す如きチップ位置決め用の
突起6bを形成しておけば、モジュール基板1の開口部
1aに半導体チップ3を精度良く位置決めできるととも
に、開口部1aでの半導体チップ3の横ずれを確実に防
止できるといったメリットが得られる。
Next, the semiconductor chip 3 transferred by a suction collet or the like is placed in the opening 1a of the module substrate 1. As a result, the upper end of the through hole 6 a of the jig board 6 is closed by the back surface of the semiconductor chip 3. At this time, if the projection 6b for chip positioning as shown by the dotted line in the drawing is formed on the jig board 6, the semiconductor chip 3 can be accurately positioned in the opening 1a of the module substrate 1 and the opening 1a can be positioned. The advantage that the lateral displacement of the semiconductor chip 3 can be surely prevented is obtained.

【0009】続いて、治具ボード6の貫通孔6aを介し
て真空引きを行う。これにより、半導体チップ3は治具
ボード6上に吸着されるため、その真空吸着力をもって
モジュール基板1の所定位置、すなわちチップ実装位置
となる開口部1aに半導体チップ3を仮固定する。次い
で、上述の如く半導体チップ3を仮固定しつつ、図示せ
ぬワイヤボンディングツール(キャピラリ等)によって
モジュール基板1の導体パターンと半導体チップ3とを
ワイヤ4にて接続する。
Then, vacuuming is performed through the through hole 6a of the jig board 6. As a result, the semiconductor chip 3 is adsorbed on the jig board 6, so that the semiconductor chip 3 is temporarily fixed to the opening 1a at the predetermined position of the module substrate 1, that is, the chip mounting position by its vacuum adsorption force. Next, while temporarily fixing the semiconductor chip 3 as described above, the conductor pattern of the module substrate 1 and the semiconductor chip 3 are connected by the wires 4 by a wire bonding tool (capillary or the like) not shown.

【0010】その後、真空引きを止めて治具ボード6か
らモジュール基板1を取り外す。このとき、半導体チッ
プ3が多数のワイヤ4によって機械的にモジュール基板
1に接続され、しかもチップ自体がきわめて軽いことか
ら、半導体チップ3の位置はワイヤ4によって保持され
る。続いて、図1(b)に示すように、治具ボード6か
ら取り外したモジュール基板1の下面側に補助基板7を
重ね合わせて両者を密着させる。さらに、この状態でモ
ジュール基板1の上方からペースト状のチップコート剤
(例えば熱硬化性樹脂)5を滴下して、半導体チップ3
のワイヤ接続面側を樹脂封止する。その後、チップコー
ト剤5を完全に硬化させ、モジュール基板1の開口部1
aに半導体チップ3を本固定する。
After that, the vacuuming is stopped and the module substrate 1 is removed from the jig board 6. At this time, the semiconductor chip 3 is mechanically connected to the module substrate 1 by a large number of wires 4, and since the chip itself is extremely light, the position of the semiconductor chip 3 is held by the wires 4. Subsequently, as shown in FIG. 1B, the auxiliary substrate 7 is superposed on the lower surface side of the module substrate 1 detached from the jig board 6 to bring them into close contact with each other. Furthermore, in this state, a paste-like chip coating agent (for example, thermosetting resin) 5 is dropped from above the module substrate 1 to form the semiconductor chip 3
The wire connection surface side of is sealed with resin. After that, the chip coating agent 5 is completely cured, and the opening 1 of the module substrate 1 is
The semiconductor chip 3 is permanently fixed to a.

【0011】このように本第1実施例においては、モジ
ュール基板1の開口部1aに半導体チップ3を配置した
のち、治具ボード6に設けた貫通孔6aを介して真空引
きを行うことにより、半導体チップ3を真空吸着力によ
って仮固定した状態でワイヤ4の接続を行うため、ワイ
ヤボンディング後の特性測定において不良チップが検出
された場合でも、基板表面と直交する方向に不良チップ
を押し出すだけで、モジュール基板1から簡単に不良チ
ップを取り外すことができる。また、不良チップを取り
外した後は、従来の如くダイボンド剤等の取り除き作業
を要することなく、上記同様の手順をもって再びモジュ
ール基板1の所定位置、すなわちチップ実装位置となる
開口部1aに交換用の良品チップを実装することができ
る。
As described above, in the first embodiment, the semiconductor chip 3 is placed in the opening 1a of the module substrate 1 and then vacuum is drawn through the through hole 6a provided in the jig board 6, Since the wire 4 is connected while the semiconductor chip 3 is temporarily fixed by the vacuum suction force, even if a defective chip is detected in the characteristic measurement after wire bonding, the defective chip is simply pushed out in the direction orthogonal to the substrate surface. The defective chip can be easily removed from the module substrate 1. Further, after removing the defective chip, it is not necessary to remove the die-bonding agent or the like as in the conventional case, and the same procedure as described above is used again to replace the opening 1a at the predetermined position of the module substrate 1, that is, the chip mounting position. A good chip can be mounted.

【0012】ここで、上述の如くモジュール基板1に半
導体チップ3を本固定した後は、補助基板7を取り外し
て最終製品形態としてもよいが、そのまま半導体モジュ
ールの一構成部品として補助基板7を残す場合は、予め
熱伝導率の高い材料(例えば銅、アルミ、セラミックな
ど)で補助基板7を構成し、これを放熱板として半導体
チップ3のワイヤ接続面と反対側の面、つまり発熱量の
多いチップ裏面に接合しておくとより好適である。すな
わち、こうして得られるモジュール構造にあっては、そ
の製造過程において不良チップの検出に伴う補修作業が
容易になるだけでなく、モジュール動作時に半導体チッ
プ3で発生した熱が放熱板7に伝導され、そこから効率
良く外部に放散されるようになるため、モジュール全体
の放熱効果が格段に高まる。また、放熱板7にフィン構
造を採用すれば、より大きな放熱面積が得られるため、
さらなる放熱効果の向上が図られる。ちなみに、放熱板
7の接合にあたっては、個々の半導体チップ3に対して
個片の放熱板7をそれぞれ接合してもよいが、モジュー
ル基板1の全面にわたって放熱板7を接合した方が組立
工数や放熱効果の点で有利である。
Here, after the semiconductor chip 3 is permanently fixed to the module substrate 1 as described above, the auxiliary substrate 7 may be removed to form a final product, but the auxiliary substrate 7 is left as it is as one component of the semiconductor module. In this case, the auxiliary substrate 7 is previously made of a material having a high thermal conductivity (eg, copper, aluminum, ceramics, etc.), and this is used as a heat dissipation plate on the surface opposite to the wire connection surface of the semiconductor chip 3, that is, a large amount of heat is generated. It is more preferable to bond it to the back surface of the chip. That is, in the module structure thus obtained, not only the repair work accompanying the detection of the defective chip is facilitated in the manufacturing process, but also the heat generated in the semiconductor chip 3 during the module operation is conducted to the heat dissipation plate 7, Since it is efficiently dissipated to the outside, the heat dissipation effect of the entire module is significantly enhanced. If a fin structure is adopted for the heat dissipation plate 7, a larger heat dissipation area can be obtained,
The heat dissipation effect can be further improved. By the way, when the heat sink 7 is joined, the individual heat sinks 7 may be joined to the individual semiconductor chips 3, but if the heat sink 7 is joined over the entire surface of the module substrate 1, the number of assembling steps may be increased. It is advantageous in terms of heat dissipation.

【0013】図2は本発明に係わる半導体モジュールの
製造方法の第2実施例を説明する図である。本第2実施
例においては、先ず図2(a)に示すように、基板製作
段階でチップ実装位置に対応するモジュール基板1の所
定位置に平面矩形状の凹部1bを形成し、さらに凹部1
bの中央には真空引き用の通孔1cを形成しておく。そ
してチップ実装時には、吸着コレット等により移送した
半導体チップ3をモジュール基板1の凹部1bに配置す
る。このとき、図示はしないが、予め凹部1bの底面に
チップ位置決め用の突起を形成しておくか、或いはモジ
ュール基板1の凹部1bをチップ径よりも僅かに大きく
形成しておけば、モジュール基板1に対して半導体チッ
プ3を精度良く位置決めできるうえ、凹部1bでのチッ
プの横ずれも確実に防止できる。
FIG. 2 is a diagram for explaining a second embodiment of the method of manufacturing a semiconductor module according to the present invention. In the second embodiment, first, as shown in FIG. 2A, a planar rectangular recess 1b is formed at a predetermined position of the module substrate 1 corresponding to the chip mounting position at the substrate manufacturing stage, and the recess 1 is further formed.
A through hole 1c for vacuuming is formed in the center of b. At the time of chip mounting, the semiconductor chip 3 transferred by a suction collet or the like is placed in the recess 1b of the module substrate 1. At this time, although not shown, if a projection for chip positioning is formed on the bottom surface of the recess 1b in advance, or if the recess 1b of the module substrate 1 is formed slightly larger than the chip diameter, the module substrate 1 On the other hand, the semiconductor chip 3 can be accurately positioned, and lateral displacement of the chip in the recess 1b can be reliably prevented.

【0014】続いて、モジュール基板1に設けた通孔1
cを介して真空引きを行い、その真空吸着力をもって半
導体チップ3をモジュール基板1の所定位置、すなわち
チップ実装位置となる開口部1aに仮固定する。次い
で、半導体チップ3を仮固定しつつ、図示せぬワイヤボ
ンディングツール(キャピラリ等)によってモジュール
基板1の導体パターンと半導体チップ3とをワイヤ4に
て接続する。
Subsequently, the through hole 1 provided in the module substrate 1
Vacuuming is performed via c, and the semiconductor chip 3 is temporarily fixed to the opening 1a at a predetermined position of the module substrate 1, that is, a chip mounting position by the vacuum suction force. Next, while temporarily fixing the semiconductor chip 3, the conductor pattern of the module substrate 1 and the semiconductor chip 3 are connected by the wires 4 by a wire bonding tool (capillary or the like) not shown.

【0015】その後、真空引きを止めてモジュール基板
1の通孔1cをシール材8によって塞ぎ、この状態でモ
ジュール基板1の上方からペースト状のチップコート剤
5を滴下して半導体チップ3のワイヤ接続面側を樹脂封
止する。さらに、チップコート剤5を完全に硬化させ、
モジュール基板1の凹部1bに半導体チップ3を本固定
する。
After that, the vacuuming is stopped and the through hole 1c of the module substrate 1 is closed by the sealing material 8. In this state, the paste chip coating agent 5 is dropped from above the module substrate 1 to connect the semiconductor chip 3 to the wire. The surface side is resin-sealed. Further, completely cure the tip coat agent 5,
The semiconductor chip 3 is permanently fixed to the recess 1b of the module substrate 1.

【0016】このように本第2実施例においては、モジ
ュール基板1の凹部1bに半導体チップ3を配置したの
ち、基板の通孔1cを介して真空引きを行うことによ
り、半導体チップ3を真空吸着力によって仮固定した状
態でワイヤ4の接続を行うため、ワイヤボンィング後の
特性測定において不良チップが検出された場合でも、通
孔1cを介して基板表面と直交する方向に不良チップを
押し出すだけで、モジュール基板1から簡単に不良チッ
プを取り外すことができる。また、不良チップを取り外
した後は、従来の如くダイボンド剤等の取り除き作業を
要することなく、上記同様の手順をもって再びモジュー
ル基板1の所定位置、すなわちチップ実装位置となる凹
部1bに交換用の良品チップを実装することができる。
As described above, in the second embodiment, after the semiconductor chip 3 is arranged in the recess 1b of the module substrate 1, the semiconductor chip 3 is vacuum-sucked by vacuuming through the through hole 1c of the substrate. Since the wire 4 is connected in a state of being temporarily fixed by force, even if a defective chip is detected in the characteristic measurement after wire bonding, the defective chip is simply pushed out in the direction orthogonal to the substrate surface through the through hole 1c. Thus, the defective chip can be easily removed from the module substrate 1. Further, after the defective chip is removed, there is no need to remove the die-bonding agent or the like as in the conventional case, and the same procedure as described above is used again to replace the concave portion 1b at the predetermined position of the module substrate 1, that is, the chip mounting position with a good product for replacement. A chip can be mounted.

【0017】図3は本発明に係わる半導体モジュールの
製造方法の第3実施例を説明する図である。本第3実施
例においては、先に述べた第1及び第2の各実施例に比
較して、特にワイヤボンディング後に行われる樹脂封止
の方法に違いがある。
FIG. 3 is a view for explaining a third embodiment of the semiconductor module manufacturing method according to the present invention. The third embodiment differs from the above-described first and second embodiments in the method of resin encapsulation, which is performed after wire bonding.

【0018】すなわち、図3(a)に示す方法では、上
記第1実施例の如くモジュール基板1の開口部1aに半
導体チップ3を真空吸着力により仮固定した状態でモジ
ュール基板1の導体パターンと半導体チップ3とをワイ
ヤ4にて接続したのち、箱型のケース9に入れたペース
ト状のチップコート剤5にモジュール基板1を下向きに
して浸す。これにより、半導体チップ3のワイヤ接続面
側をチップコート剤5によって樹脂封止し、さらにチッ
プコート剤5を完全に硬化させてモジュール基板1の開
口部1aに半導体チップ3を本固定する。
That is, in the method shown in FIG. 3 (a), the semiconductor chip 3 is temporarily fixed to the opening 1a of the module substrate 1 by the vacuum suction force as in the first embodiment, and the conductor pattern of the module substrate 1 is formed. After connecting the semiconductor chip 3 with the wire 4, the module substrate 1 is dipped in a paste-like chip coating agent 5 placed in a box-shaped case 9 with the module substrate 1 facing downward. As a result, the wire connection surface side of the semiconductor chip 3 is resin-sealed with the chip coating agent 5, and the chip coating agent 5 is completely cured to permanently fix the semiconductor chip 3 in the opening 1 a of the module substrate 1.

【0019】また、図3(b)に示す方法では、上記第
2実施例の如くモジュール基板1の凹部1bに半導体チ
ップ3を真空吸着力により仮固定した状態でモジュール
基板1の導体パターンと半導体チップ3とをワイヤ4に
て接続したのち、箱型のケース9に入れたペースト状の
チップコート剤5にモジュール基板1を下向きにして浸
す。これにより、半導体チップ3のワイヤ接続面側をチ
ップコート剤5によって樹脂封止し、さらにチップコー
ト剤5を完全に硬化させてモジュール基板1の凹部1b
に半導体チップ3を本固定する。
Further, in the method shown in FIG. 3B, the semiconductor chip 3 is temporarily fixed to the recess 1b of the module substrate 1 by the vacuum suction force as in the second embodiment, and the conductor pattern of the module substrate 1 and the semiconductor After connecting the chip 3 and the wire 4 to each other, the module substrate 1 is dipped in a paste-like chip coating agent 5 placed in a box-shaped case 9 with the module substrate 1 facing downward. As a result, the wire connection surface side of the semiconductor chip 3 is resin-sealed with the chip coating agent 5, and the chip coating agent 5 is completely cured to form the recess 1 b
The semiconductor chip 3 is permanently fixed to.

【0020】このように本第3実施例においては、上記
第1及び第2実施例の如く樹脂封止の際に補助基板7や
シール材8等の樹脂漏れ防止手段を講じることなく、モ
ジュール基板1に実装された複数(図例では2個)の半
導体チップ3を一括して樹脂封止し、且つ所定の位置
(開口部1a、凹部1b等)に本固定することができる
ため、工程の簡略化が図られる。なお、ケース9はチッ
プコート剤5が硬化した後で取り外してもよいし、その
ままモジュール基板1に取り付けて最終製品形態として
もよい。
As described above, in the third embodiment, the module substrate is not provided with the resin leakage preventing means such as the auxiliary substrate 7 and the sealing material 8 at the time of resin sealing as in the first and second embodiments. Since a plurality (two in the illustrated example) of semiconductor chips 3 mounted on one can be collectively resin-sealed and fixed permanently at a predetermined position (opening 1a, recess 1b, etc.), Simplification is achieved. The case 9 may be removed after the chip coating agent 5 is cured, or may be directly attached to the module substrate 1 to form the final product.

【0021】[0021]

【発明の効果】以上、説明したように本発明によれば、
モジュール基板の所定位置に真空吸着力によって半導体
チップを仮固定し、この状態でモジュール基板の導体パ
ターンと半導体チップとをワイヤにて接続するととも
に、ワイヤボンディング後は半導体チップのワイヤ接続
面側を樹脂封止してモジュール基板の所定位置に半導体
チップを本固定するため、ワイヤボンディング後の特性
測定において不良チップが検出された場合であっても、
基板表面と直交する方向に不良チップを押し出すといっ
た簡単な作業でモジュール基板から不良チップを取り外
すことが可能となる。また、モジュール基板から不良チ
ップを取り外した後においても、従来の如くダイボンド
剤等を除去するなどの煩雑な作業を要することなく、交
換用の良品チップを実装することが可能となる。その結
果、チップ不良に伴うマルチチップモジュール等の補修
作業(チップ交換作業)においては、不良チップをモジ
ュール基板から取り外す際にモジュール基板や他の半導
体チップを傷つけるなどの二次不良の発生が皆無となる
ため、半導体モジュールとしてのトータル的な歩留りの
向上並びにコストの低減が図られる。さらに、上述の如
く補修作業がきわめて簡易なものとなるため、作業を標
準化して効率アップを図ることもできる。
As described above, according to the present invention,
The semiconductor chip is temporarily fixed to a predetermined position of the module substrate by a vacuum suction force, and in this state, the conductor pattern of the module substrate and the semiconductor chip are connected by a wire, and after wire bonding, the wire connection surface side of the semiconductor chip is made of resin. Even if a defective chip is detected in the characteristic measurement after wire bonding, because the semiconductor chip is sealed and the semiconductor chip is permanently fixed at a predetermined position on the module substrate,
The defective chip can be removed from the module substrate by a simple operation such as pushing out the defective chip in a direction orthogonal to the surface of the substrate. Further, even after the defective chip is removed from the module substrate, it is possible to mount a good replacement chip without the need for complicated work such as removing the die bonding agent and the like as in the conventional case. As a result, in the repair work (chip replacement work) of a multi-chip module etc. due to a chip defect, there is no secondary defect such as damage to the module substrate or other semiconductor chips when the defective chip is removed from the module substrate. Therefore, it is possible to improve the total yield as a semiconductor module and reduce the cost. Further, since the repair work is extremely simple as described above, it is possible to standardize the work and improve the efficiency.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例を説明する図である。FIG. 1 is a diagram illustrating a first embodiment of the present invention.

【図2】本発明の第2実施例を説明する図である。FIG. 2 is a diagram illustrating a second embodiment of the present invention.

【図3】本発明の第3実施例を説明する図である。FIG. 3 is a diagram illustrating a third embodiment of the present invention.

【図4】従来例を説明する図である。FIG. 4 is a diagram illustrating a conventional example.

【符号の説明】[Explanation of symbols]

1 モジュール基板 1a 開口部 3 半導体チップ 4 ワイヤ 5 チップコート剤 7 補助基板(放熱板) 1 Module Board 1a Opening 3 Semiconductor Chip 4 Wire 5 Chip Coating Agent 7 Auxiliary Board (Heat Radiating Plate)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 導体パターンが形成されたモジュール基
板の所定位置に半導体チップを実装してなる半導体モジ
ュールの製造方法において、 前記モジュール基板の所定位置に前記半導体チップを真
空吸着力により仮固定した状態で前記半導体チップと前
記導体パターンとをワイヤにて接続し、 その後、前記半導体チップのワイヤ接続面側を樹脂封止
して前記モジュール基板に前記半導体チップを本固定す
ることを特徴とする半導体モジュールの製造方法。
1. A method of manufacturing a semiconductor module in which a semiconductor chip is mounted at a predetermined position on a module substrate having a conductor pattern formed thereon, wherein the semiconductor chip is temporarily fixed at a predetermined position on the module substrate by a vacuum suction force. A semiconductor module characterized in that the semiconductor chip and the conductor pattern are connected by a wire with a wire, and then the wire connection surface side of the semiconductor chip is resin-sealed to permanently fix the semiconductor chip to the module substrate. Manufacturing method.
【請求項2】 チップ実装位置を開口してなるモジュー
ル基板と、 前記モジュール基板の開口部に配置され且つ該モジュー
ル基板の導体パターンにワイヤを介して接続された半導
体チップと、 前記開口部に配置された前記半導体チップを固定するチ
ップコート剤と、 前記半導体チップのワイヤ接続面と反対側の面に接合さ
れた放熱板とを備えたことを特徴とする半導体モジュー
ル。
2. A module substrate having an opening at a chip mounting position, a semiconductor chip arranged in the opening of the module substrate and connected to a conductor pattern of the module substrate via a wire, and arranged in the opening. A semiconductor module, comprising: a chip coating agent for fixing the formed semiconductor chip; and a heat dissipation plate bonded to a surface of the semiconductor chip opposite to a wire connection surface.
JP7056930A 1995-03-16 1995-03-16 Semiconductor module and manufacture thereof Pending JPH08255803A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7056930A JPH08255803A (en) 1995-03-16 1995-03-16 Semiconductor module and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7056930A JPH08255803A (en) 1995-03-16 1995-03-16 Semiconductor module and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH08255803A true JPH08255803A (en) 1996-10-01

Family

ID=13041236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7056930A Pending JPH08255803A (en) 1995-03-16 1995-03-16 Semiconductor module and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH08255803A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332383A (en) * 2000-03-17 2001-11-30 Seiko Epson Corp Manufacturing method of organic el display body, arrangement method of semiconductor element, manufacturing method of semiconductor device
DE10213879C1 (en) * 2002-03-27 2003-07-10 Infineon Technologies Ag Electronic component has semiconductor chips fitted into respective recesses in surface of electronic circuit board
US7232709B2 (en) 2003-12-19 2007-06-19 Nitto Denko Corporation Process for producing a semiconductor device
JP2008205195A (en) * 2007-02-20 2008-09-04 Nitto Denko Corp Method for manufacturing semiconductor device
US9153556B2 (en) 2006-09-08 2015-10-06 Nitto Denko Corporation Adhesive sheet for manufacturing semiconductor device, manufacturing method of semiconductor device using the sheet, and semiconductor device obtained by the method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001332383A (en) * 2000-03-17 2001-11-30 Seiko Epson Corp Manufacturing method of organic el display body, arrangement method of semiconductor element, manufacturing method of semiconductor device
DE10213879C1 (en) * 2002-03-27 2003-07-10 Infineon Technologies Ag Electronic component has semiconductor chips fitted into respective recesses in surface of electronic circuit board
US7232709B2 (en) 2003-12-19 2007-06-19 Nitto Denko Corporation Process for producing a semiconductor device
US9153556B2 (en) 2006-09-08 2015-10-06 Nitto Denko Corporation Adhesive sheet for manufacturing semiconductor device, manufacturing method of semiconductor device using the sheet, and semiconductor device obtained by the method
JP2008205195A (en) * 2007-02-20 2008-09-04 Nitto Denko Corp Method for manufacturing semiconductor device
JP4523611B2 (en) * 2007-02-20 2010-08-11 日東電工株式会社 Manufacturing method of semiconductor device

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