JPH04102935A - Device and method for monitoring power on sequence of recording device - Google Patents

Abstract

PURPOSE:To make it possible to discriminate defective parts at a glance by providing this monitoring device with a means having specific codes corresponding to respective chips and capable of successively displaying the specific codes in accordance with the advance of a power ON sequence, and when a certain chip is abnormal, aborting the succeeding display operation. CONSTITUTION:The monitoring device is provided with the display means 12 having the specific codes corresponding to respective chips and capable of successively displaying the specific codes in accordance with the advance of the power ON sequence and the means 12 is constituted so as to display the codes of the normal chips, and when a certain chip is abnormal, abort the succeeding display operation without displaying the code of the abnormal chip. Consequently, the monitoring device 10 capable of easily confirming whether a chip is normal or not in the power ON sequence can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to recording devices such as copying machines and printers, and in particular, it is necessary to grasp the progress status of the power-on sequence for each chip when starting up a CPU system. Related to a monitor suitable for

[Conventional technology]

Copying machines as recording devices have made remarkable progress due to advancements in image processing technology ('j) In particular, copying machines with higher image quality and colorization, as well as high speed and various editing functions, are now in demand. In order to satisfy these demands, program control is performed by a CPU system.A CPU system consists of one or more MPUs.
It is configured with multiple MPU'? : When configured, it is incorporated into one or more electric circuit boards (hereinafter not referred to as PWB) depending on the role sharing of the CPU.

In a CPU system, a start-up operation is always performed before the program is run (r (IN)). This start-up operation is called the power-on sequence. It will be verified that the chip is working properly.

On the other hand, in order to make the recording device more multifunctional and more compact, the hardware has been designed with increased PWB packaging density and LSI.

In addition, in order to cope with the increase in the number of software modules and limitations on board size due to physical space limitations within the device, the CPUs are distributed, and high-speed communication lines (L,
-NET).

By adopting such a hardware and software configuration,
If there is a change in specifications or an improvement in technology, this can be easily handled by changing only the relevant board, and it is also possible to standardize the technology.

For the above reasons, electrical hardware can be broadly divided into CRT screen display, ED/NTP, and
Sodo(E[)IT PAD>, memory card(OMO
RY CARD), etc., the user interface (UI) system, sys, image input terminal (II
T), Video/Image Processing System (VIDEO/
IPS) processing system (SYS) system and master control board (MCB), RO8,I
It consists of a master control port (MCB) system that processes OB, accessories, etc.

By the way, in the development of this type of device, P
A check is made to see if the WB operates normally. Especially P
Ensuring the normal operation of the WB is extremely important in increasing the reliability of the program's back-up process.
This has become essential whenever improving the work efficiency of subsequent processes.

A tool called a RAM monitor is used to check the operation of the PWB. After initializing the RAM, this RAM monitor sets an address, runs a program, directly reads the data in the RAM, and determines whether or not this data is correct.

In Tebagga's method, you set breakpoints at several locations, try to see if it stops at the breakpoint, and find the failure location from the breakpoints you passed. That is, if the hardware is operating correctly, it will always stop at the set breakpoint, but if it is faulty, the software will stop (WAIT) when it accesses the faulty IC.

[Problem to be solved by the invention]

Possible causes of software not running properly include poor soldering on the IC, failure of the IC itself, and defective components, but which chip is causing this, or in other words, where does it stop working after power-on? There's no way to know.

Therefore, if there is a failure in the hardware, various phenomena can be predicted, such as power-on stopping, or after entering RUN, communication is not possible, interrupt processing cannot be handled correctly, etc.

With conventional methods, it is difficult to identify whether the cause of a failure is caused by software or hardware, and even if the cause is hardware, it takes time to discover it and requires a skilled engineer. There is. Furthermore, even if the faulty PWB could be identified, it was not possible to identify which chip of the PWB was causing the problem.

Currently, defective PWBs are replaced with new ones. Furthermore, even if the cause is found in a specific chip, it will take time to investigate the cause and take countermeasures, which may affect other developments, such as software development, and there is a risk that PWB defects may delay the entire development process. There is.

Furthermore, since a defective PWB cannot be used by replacing the defective chip in a short time, it is necessary to prepare a spare, which causes problems such as cost increase and PWB inventory management.

An object of the present invention is to provide a monitor device that can confirm whether or not a chip is normal in a power-on sequence using a specific code corresponding to the chip.

Another object of the present invention is to provide a monitoring method that allows the progress of a power-on sequence to be confirmed using a communication bus.

[Means to solve the problem]

In order to achieve the above object, the present invention is a monitor device that checks the progress of a power-on sequence for each chip during startup of a CPU system installed in a recording device. has a specific code,
means for sequentially displaying the specific code as the power-on sequence progresses; the display means displays the code of the chip when the chip is normal; and the display means displays the code of the chip when the chip is abnormal. It is configured to not display any information and to stop any further display operations.

The power-on sequence monitoring method is to send step data for checking the progress of the power-on sequence onto the communication bus of the CPU system, and to determine chip failure from communication data based on the step data.

[For production]

Since the monitor display changes according to the state transition of the power-on sequence, the current power-on sequence can be understood at a glance. The failure location and defective parts can be identified from the code where the monitor display stops.

It also sends step data to L-NETJ2 to check the progress of the power-on sequence of the SYS system PWB,
SLIM monitors the progress of whether this data is received within a predetermined time.
and monitor it. If the SL'TM data is not displayed, it is determined that the chip during that period has failed because the predetermined time has not elapsed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In addition, in this embodiment, the progress of the power-on sequence of the SYS system PWB is monitored by 7 segments 1 to (SE
The case of displaying by G) will be explained. Figure 2 shows v
- An example of the arrangement of electrical components of a sys-based PWB is shown.

The v-sys system PWB1 has three connectors (J83~
5) is provided. Here, the power-on sequence will be explained using an ODDRAM monitor (hereinafter referred to as RAM monitor). A memory display board 10 as a monitor device shown in FIG. 1 is connected to the connector of this RAM monitor.

The memory display board is provided with a power-on sequence progress display section 12 composed of 7 SECs for displaying the state of the power-on sequence, and four dial switches 14 for specifying a 4-digit HEX address.

As a 7SEC display, the upper digit display section 12a indicates a division of a plurality of chips as a group, and the lower digit display section 1
2b represents the initialization and test of the chip. FIG. 3 shows an example of the correspondence between the 7SEC display and the power-on sequence status.

Next, the operation of the monitor device will be explained with reference to FIGS. 4 and 5.

When the power is turned on, the IIT remotes 1 to 73 and the IPS remote I.
IPS reset signal supplied to 74 and II
The T reset signal becomes H (HIGH), and the TPS remote 74 and IIT remote 73 are released from reset and start operating.

When it is detected that the power supply voltage has become normal, the power normal signal rises, the MCB remote 75 starts operating, establishes the control right and the U2 master right, and performs a high-speed communication network LNET test. Furthermore, the power normal signal is sent from the MCB remote 75 to the SYS remote 71 through the pot line. When a predetermined time T has elapsed after the start of operation of the MCB remote 75, the MCB
The system reset signal supplied from the remote 75 to the SYS remote 71 through the Hora I line becomes H,
Either the resets 1 to 71 of the SYS remote 71 are released and the operation starts, or in this case, the operation of the SYS remotes 1 to 71 starts after the above T time has elapsed by the 86NMI signal and the 86 reset signal inside the SYS remote 71. 200 per page
Delayed by μsec.

Note that the delay time is for crashes, instantaneous power outages, and rough 1
- This is provided to store the state of the machine in non-volatile memory when the machine stops or runs out of control due to temporary problems such as runaway software or software bugs. There is.

When SYS remote 71 starts operating, it takes about 3.8 seconds
During the period c, a core test is performed, that is, a ROM, RAM check, hardware check, etc. In the above RAM test, the IPS reset I signal and the IIT reset signal are set to H, and the IPS remote 74 and l [IT remote 1 to 73
restart the operation and perform each core test.

By the way, SYS, IIT, and IPS must be synchronized with the power-on sequence, so SYS remote 1
~71 under his own supervision, with the start of the core test
The S reset signal and IIT reset signal are set to L (Low).
), IPS remote 74 and IIT remote 73
Reset.

When the core test is completed, the SYS remote 71
C Perform a self-test. This CCCCCC Ruf test,
This is done by sending predetermined data to the L-NET, receiving it itself, and confirming that the received data is the same as the transmitted data. Please note that when performing the CCC self-test, please ensure that the self-test times do not overlap.
Time is allocated to C.

In other words, in L-NET, sys remote 71,
Each node such as the MCB remote 75 transmits data when it wants to transmit data, and if a data collision occurs, it retransmits after a predetermined period of time. This is because the SYS remote 71 transmits data when it wants to transmit data. This is because when performing a self-test l-, if another node employs L-NET, a data collision may occur and the self-test cannot be performed. Therefore, SYS remote 71
When starts the CCC self-test, the LNET test of the MCB remote 75 has finished. During this period, DLY is the SYS Etit Data Path Test (E
Waiting for completion of TA Bus TEST) to DIT D. The communication test conducted during this period (T1) is
This is a test of a 9600bps serial communication network,
Predetermined data is transmitted and received in a predetermined sequence.

When the communication test ends, for example after T3 has passed, sy
L-NE between s remote 71 and MC'B remote 75
Perform T communication test. That is, it requests the self-test results from the MCB remote 71 and sends the results to the SYS remote 71.
In response to the request, the MCB remote I-75 issues the results of the tests it has conducted so far as a self-test.

Upon receiving the self-test result, the MCB remote 75 issues a token pass to the SYS remote 71. The token pass is a card used to exchange U ■ master rights,
By passing the token pass to SYS remote 71,
The UI master authority is transferred from the MCB remote 75 to the SYS remote 71 each time. This is the power-on sequence. During this power-on sequence, the U1 remotes 1 to 70 display messages such as "Please wait for a while" and perform various tests such as a core test and a communication test.

In the above power-on sequence, if there is no response to the self-test result request, or if there is an abnormality in the self-test result, the MCB remote 75 will make the machine dead, activate the UI control right, and display the UI.
It controls the remote 70 and displays that an abnormality has occurred. This is stage 1 of Machine Dead.

FIG. 6 shows the state transition and transition conditions of the power-on sequence, and this condition is to pass through openings ① to ① not shown in FIG. 5(a). For example, MCB is SYS
Upon releasing the reset, the state of the power-on sequence transitions from A to B. First, 8254 counter 1 to 1
After setting a 0-second timer and performing a power-on self-test of the system, it is determined that 10 seconds have passed by the 10-second count interrupt of 8254 counter 1. In this example, the maximum time required to complete the power-on self-test is 8900.
m s , interrupt test (・Since the time until completion is specified as 1000 m s, if the transition from B to C does not occur even after 1000 m s has elapsed, it is determined that 8254 and 8259 are malfunctioning.Similarly, 8254.825 also when the power-on sequence does not transition from C to E.
9 or defective.

FIG. 7 is a chart showing the RAM monitor display during the power-on sequence of the SYS system PWB. FIG. 5(1)) shows a part of the power-on sequence and RAM monitor display.

In the figure, when the SYS system is powered on and set by two signals 86HMI and 86RESET, a power-on sequence is started.

First, set the interrupt vector according to the interrupt factor (
step]00). r F Fj is displayed on the RAM monitor from the reset of the sys system until the end of the initialization of 8255 of the peripheral LSIs. Then RAM
Initialize 8255, which performs processing to display on the monitor, and if it is normal, it will display [00] (step 101). Next, initialize 8259, which handles interrupts, and if it is normal, it will display "00". ]” is displayed (step 102). Similarly, 8254, which processes the timer count, is initialized and the process moves to the memory test 1~.

8259 test checks whether an interrupt corresponding to an interrupt factor that occurs outside the SYS system is generated.This interrupt test includes scan end and start interrupts, There are four interrupts: image loading start and end interrupts.

Here, the interrupt NASS1~ circuit inside the SYS system PWB is used to check whether an interrupt corresponding to the interrupt factor occurs within a predetermined time period from start to end.

The test for the 8254 is to check whether the timer count is 1 scale or not, and whether it is operating correctly or not, and whether the monitor display stops at 25H, 33H, and 42H corresponding to each time Tl, T2, and T3 created inside the 8254. Check. Note that "I(" is HEX code 1~).

For example, if the 8259 is out of order, no ACK will be returned even if accessed, so the monitor display will stop at "01".

Also, if the 8254 is malfunctioning, the functions from 9 to 9 will not work properly, so the monitor display will be 25H, 3.
It stops at either 3H or 42H.

In the memory test, the ROM is first tested by calling up software data that is not stored in the ROM. Figure 8 is ROM test I, Figure 9 is RAM test, Figure 10 is Gi N V lvI test l-(7) 7
0-char-1. is shown.

These memory tests 1 to 1 are READ/WRITE tests to check whether the memory can be accessed correctly.

The test results are displayed whether each memory is pass or fail after the test is completed.

Thereafter, communication and header (11EΔDER) data are initialized, and CCC self-tests 1 to 1 are performed.

CCC self-test is self-death 1~state ROM/R
Perform AM Test I. If the self-diagnosis is normal, the system automatically transitions to the HALT state. In the case of an abnormality, the self-death 1~ state remains.

The execution procedure of this test will be explained in Enableful FjFo Turnaround 1~Test 1~. FIG. 11 shows the flow of test I. In this test, we will execute an efficient FIFO turn run (class 4 command).CC
Wait 1ms to read the C status register. Then C
Read the CC status register and check whether this test is executable or not. ” If test 1 is repeated 500 times and still fails, it is determined that the FIFO is malfunctioning.

In this way, since the monitor display changes according to the state transition of the power-on sequence, the current power-on sequence can be determined at first glance.

In terms of the relationship between monitor display and failure location, it can be broadly divided into 7th
As shown in the figure, the A stage has a peripheral LSI, the B stage has a memory, the C stage has a CCC chip, and the D stage has an 825
4 failure can be determined.

According to this embodiment, it is possible to identify the failure location and defective parts from the monitor display or the stopped code during the power-on sequence, so the next test is performed every time this defective part is replaced. I have something to do. Therefore, in a PWB prototype test, a fatal defect can be easily discovered, and its cause can be investigated and countermeasures can be taken quickly.

Next, other embodiments of the present invention will be described.

Step data for checking the progress of the power-on sequence of the SYS system PWB is sent onto the L-NET (see FIG. 5), and communication data based on this step data is monitored. FIG. 13 shows a test example in which the progress of whether data sent out on the L-NET is received at predetermined times 30H, 40H, 50H, 51H, . . . is monitored using the SLIM.

In the figure, if no SLIM data is displayed from the SYS reset to the start of the edit data bus test (power ON to 30H), it is determined that the 8254 is malfunctioning because TI (10 sec) has not elapsed. Then 30H
~40H SLIM data r 2DXX30XX
~2DXX40XX If J is not displayed, T2(ls
ec) Since there is no progress, it is determined that 8254 is out of order in the same manner as above. Also, if there is no SLIM data displayed from the start of 10m5Loop preparation to the start of 10m5Loop, there will be no interruption in real time, so 8.
259 is determined to be out of order. To confirm this, trace the power-on sequence step data from power-on using SLIM. All power-on sequence step data is retransmitted six times. The reason for this is that the sys system CCC is normally communicating during 5OURCE I
When data with D=SYS, DESTNATION ID=SYS is received, it is judged as incorrect data and ACK is sent.
It is a lick that does not give out.

〔Effect of the invention〕

As described above, according to the present invention, defective parts can be identified at a glance by the code display on the RAM monitor, so that defective parts can be replaced during trial production. In addition, the power-on sequence can be tested simply by connecting the monitor to the RAM monitor connector provided on the PWB, making it easy to identify PWB failures and their components. This makes it possible to reduce development man-hours.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of the display section and address designation section of the memory display board of the monitor device, Figure 2 is a layout diagram of the SYS system PWB IC and RAM monitor connector, and Figure 3 is the state of the power-on sequence. Figure 4 is a diagram explaining the relationship between the displays, Figure 4 is a diagram showing the hardware architecture, Figure 5 (a) is a diagram explaining the sequence from the power-on state to the standby state, and Figure 5 (b) is a diagram explaining the sequence from the power-on state to the standby state. Figure 5(a) is a diagram explaining the power-on sequence and part of the monitor display; Figure 6 is a diagram explaining the state transition of the system monitor power-on sequence and its conditions; Figure 7 is the power-on sequence. Figure 8 is a flowchart of the ROM test, Figure 9 is the RA
FIG. 10 is a flowchart of the NVM test, FIG. 11 is a flowchart showing an example of the CCC self-test, and FIG. 12 is a diagram showing the relationship between the power-on sequence state and the SLIM data. Applicant Fuji Xerox Co., Ltd.

Claims (2)

[Claims] (1) A monitor device that checks the progress of the power-on sequence for each chip at startup of the CPU system installed in the recording device, and has a specific code corresponding to each chip, and the specific code according to the progress of the power-on sequence, and the display means displays the code of the chip when the chip is normal, and does not display the code of the chip when the chip is abnormal. , a power-on sequence monitor device for a recording device configured to stop further display operations. (2) Send step data to confirm the progress of the power-on sequence onto the communication bus of the CPU system installed in the recording device, determine a chip failure from communication data based on the step data, and check the progress of the power-on sequence. How to check.