JPH07234805A - Simultaneous debugging method of plural central processing units - Google Patents

Abstract

PURPOSE:To constitute a system which enables plural CPU boards to perform debugging operation at the same time even when the CPU boards are arranged at mutually distant places. CONSTITUTION:A process control and monitor device has programs P1 and Pm internally and plural sets of controllers 11-1n equipped with CPU boards 21-2n which operate with those programs P1-Pm, memory boards 31-3n having common memories at parts of the memories, and communication boards 51-5n which can access the common memories are connected through a communication line 7. The controller 11 is equipped with an interface board 41 which can access the common memory of the controller 11 and a terminal device 8 which is connected through this interface board 41, and optional controllers 11-1n of the process control and monitor device are debugged through operation from this terminal device 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for simultaneously debugging a plurality of central processing units of a plurality of sets of control units connected via a transmission line.

[0002]

2. Description of the Related Art A conventional debugging method for different central processing units (hereinafter, the central processing unit is abbreviated as a CPU board), particularly a CPU board when programs on different control units operate in a mutually related manner The debugging method of A. Individually, debug the controllers individually and then combine multiple sets of controllers.

B. Incorporate a trace process that includes time information in the program to be debugged. C. Debugger (eg in-circuit emulator IC
E) are prepared for the number of CPU boards to be debugged, and debugging is performed while synchronizing. Debugging was done by such methods.

[0004]

However, in the method A, when an abnormality occurs when a CPU board that finally needs to be combined is arranged at a distant place, it takes time to solve the abnormality. In the method B, the program cannot be stopped or a patch (temporary correction) cannot be performed on the way, so that the debugging efficiency is low, and in the method C, it is necessary to prepare a debugger for each method, which is costly. Regardless of the method of A to C, it is difficult to debug at the same time when the CPU boards are arranged at positions far apart from each other.

The present invention has been made in view of the above points, and an object thereof is to solve the above-mentioned problems and to easily provide a plurality of CPU boards even if the CPU boards are arranged at distant locations. Is to provide a method for simultaneous debugging.

[0006]

In order to achieve the above object, in the first invention, a central processing unit which incorporates a program and operates by the program, and a memory board having a common memory as a part of the memory are provided. In the method for simultaneous debugging of a plurality of central processing units of a process control monitoring device, a plurality of control devices each comprising a communication board capable of accessing a common memory are connected via a communication line. At least one of the control devices
The set of control devices includes an interface board that can access the common memory of the control device and a terminal device connected via the interface board, and an arbitrary control device of the process control monitoring device is operated by the terminal device. Shall be debugged.

In the second invention, the common memory of any control device of the process control monitoring device has an interface area, and the interface area includes a debug start request area, a breakpoint designating area, and a stop area. A state information area and a register storage area when stopped are provided.

[0008]

With the above structure, according to the present invention, the memory of any control device in the process control monitoring device can be accessed by an operation from the terminal device, so that the debug program not directly related to the program to be debugged can be accessed. By incorporating the above into the CPU board of the control device in advance and interfacing via a common memory, it becomes possible to access a control device far away via the transmission path, and debug becomes possible. In particular, by providing a debug start request area, a breakpoint specification area, a stop state information area, and a register storage area at the time of stop in the interface area of the common memory of any control device of the process control monitoring device, It is possible to perform synchronized debugging between different control devices.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an overall configuration diagram for explaining the concept of a process control and monitoring device according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a program on a board of a control device, and FIG. 3 is a debug operation terminal device and CPU. It is explanatory drawing which shows the flow of the command with a board. 1, in the process control monitoring device, a plurality of sets of control devices 11 to 1n are connected to the communication line 7 via communication boards 51 to 5n. Each controller 11 (12 to 1n) must have at least a CPU board 21 (22 to 2n) and a memory, respectively.
(MEM) board 31 (32 to 3n) and this memory (MEM) board
It consists of 31 (32 to 3n) and communication boards 51 (52 to 5n) that can access the common memory section. Further, in the illustrated example, the control device 11 is provided with an interface (IF) board 41 that can access the common memory unit of the memory (MEM) board 31, and this interface (IF) board 41 and a transmission line (RS232C transmission in the illustrated example). A debug terminal 8 is connected via a line 6. Further, the other control devices 12 to 1n can also be provided with interface (IF) boards 42 to 4n capable of accessing the common memory unit of the memory (MEM) boards 32 to 3n, if necessary.

In the above configuration, the CPU board 21 (22-2
n) indicates that the CPU and control memory (not shown)
It is mounted on the board 21 (22 to 2n), and this control memory contains the control calculation program and test program required by the control unit 11 (12 to 1n).
CPU board 21 (22 to 2n) and memory (MEM) board 31 (32 to
The control operation of the control device 11 (12 to 1n) is performed by the cooperative operation of 3n).

By operating the debug operation terminal 8, the controller 11 can access the memory (MEM) board 31 via the transmission line 6 and the interface (IF) board 41, and the program of the CPU board 21 can be accessed. You can debug. For the remote control devices 12 to 1n, the transmission line 6, the interface (IF) board 41, the communication board 51, the communication line 7, and the corresponding communication board (52 to
The corresponding memory (MEM) board (32 to 3n) can be accessed via 5n) and the program of the CPU board (22 to 2n) can be debugged.

FIG. 2 shows the relationship between the program on the CPU board 2n and the interface area on the memory (MEM) board 3n by taking the control device 1n as an example. In FIG. 2, in the control memory on the CPU board 2n, programs P1 to Pm in which the control unit 1n performs control calculation are debugged programs, and a debug program T1 that debugs these debugged programs P1 to Pm. This debug program T1 is installed on the memory (MEM) board 3n
Monitoring the interface area IFM above.

FIG. 3 is an explanatory diagram showing the flow of commands between the debug operation terminal device 8 and the CPU board. In FIG. 3, in the common memory of the memory (MEM) boards 31 to 3n of the control devices 11 to 1n, a debug start request area, a breakpoint specification area, a stop state information area, and a register storage area at the time of stop are provided. , And the debug program T1 of the debug operation terminal device 8 and the control device (11 to 1n) communicates with the debug operation terminal device 8 for debugging. next,
The flow of debug processing will be described. A debug start command C11 Debug is sent from the debug operation terminal device 8 and written in the interface area IFM. CPU board (21 ~
2n) monitors the interface area IFM and reads it as the debug start command C12 Debug to prepare the debug program T1. When the preparation of this debug program T1 is completed, the debug reception command R12 Debug OK is transmitted and written in the interface area IFM. The debug operation terminal device 8 knows the preparation end R11 Debug OK of the debug program T1 by reading the written state of the debug reception command R12 Debug OK in the interface area IFM. As a result, when debugging is not performed, the control device continuously executes normal control operations based on the programs P1 to Pm.

Next, when debugging is performed, the debug operation terminal device 8 writes the break address D15 to be stopped of the program to be debugged (P1 to Pm) of the control device to be debugged in the interface area IFM and debugs it. The program T1 reads as the break address D16, rewrites the instruction of the specified debugged program, and causes an interrupt.

From the debug operation terminal device 8, the debug start C17 Start is written in the interface area IFM, the debug program T1 is read as C18 Start, the debugged program is executed, and an interrupt occurs when the rewritten instruction is reached. . When this interrupt occurs, the interrupt occurrence D20 Break is set to the interface area IF.
Write to M and notify debug operation terminal 8 of D19 Break.

When the user wants to execute the debugging again, the breakpoint D15 is set again from the debug operation terminal device 8 and the debug start C17 Start command is sent, so that the program to be debugged stops at the program address previously stopped. The program runs again from to the breakpoint. When you have finished debugging, set the debug end command C13 Debug End to the interface area IF.
Write to M, debug program T1 is C14 Debug End
Read as this debug end command C14 Debug
Upon receiving End, the debug program T1 performs termination processing such as releasing the breakpoint of the program to be debugged (P1 to Pm) and finishes the debug termination processing with R14.
Send No Debug and write to the interface area IFM. The debug operation terminal device 8 is an interface area IFM.
Completion of debug end processing of R14 No Debug knows that debug has ended by reading the written status.

According to the method of the present invention, since the debugging is carried out via the interface area IFM of the memory (MEM) boards 31 to 3n of each control device, the same debug is performed for a plurality of control devices. By carrying out the procedure by the communication means using the transmission line 6, the interface (IF) board 41, the communication board 51, the communication line 7, and the corresponding communication boards (52 to 5n), the CPU boards of the plurality of control units can be simultaneously operated. You can debug the program.

[0018]

As described above, according to the configuration of the present invention, it is possible to debug the CPU boards of all the control devices on the communication line including the self control device, which are distant from each other. It is possible to perform synchronous debugging between programs on different control devices when the programs operate in a mutually related manner.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram illustrating a concept of a process control monitoring device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a program on the board of the control device.

FIG. 3 is an explanatory diagram showing a command flow between the debug operation terminal device and the CPU board.

[Explanation of symbols] 11, 12 to 1n Control device 21, 22 to 2n CPU board 31, 32 to 3n Common memory (MEM) board 41, 42 to 4n Interface (IF) board 51, 52 to 5n Communication board 6 Transmission line 7 Communication line 8 Debug operation terminal P1 to Pm Debug program T1 Debug program IFM interface area C11 to C14, C17, C18 Command R11 to R14 Response D15, D16, D19, D20 data

Claims (2)

[Claims] 1. A control device comprising a central processing unit having a built-in program and operated by the program, a memory board having a common memory as a part of the memory, and a communication board capable of accessing the common memory. In a method for simultaneously debugging a plurality of central processing units of a process control monitoring device, wherein a plurality of sets are connected via a communication line, at least one set of the control devices of the process control monitoring device is the control device. An interface board capable of accessing the common memory and a terminal device connected via the interface board, and debug any control device of the process control monitoring device by an operation from the terminal device. Simultaneous debugging method for a plurality of central processing units characterized by. 2. The simultaneous debugging method according to claim 1, wherein a common memory of any control device of the process control monitoring device has an interface area, and the interface area has a debug start request area and a break. A simultaneous debugging method for a plurality of central processing units, comprising: a point designation area, a stop state information area, and a register storage area at the time of stop.