JPH04101427A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a highly reliable semiconductor device which does not allow contamination to be concentrated on a local part of elements without conducting a high-temperature heat treatment by providing a barrier layer to prevent the passage of heavy metal inside a semiconductor substrate. CONSTITUTION:The surface of a substrate 11 is oxidized in steam at 1100 deg.C to form an oxide film 12. Then, a silicon nitride film 13 is deposited on the oxide film 12 and then a silicon oxide film 141 is deposited on the silicon nitride film 13. This substrate 11 is joined to another substrate 15 which is oxidized for the surface only. The joined body is oxidized in steam at 1100 deg.C to have a good adhesion. After that, the joined body is exposed to a nitrogen atmosphere to adhere the substrates 11 and 15 firmly through oxide films 12, 141 and 142 and a nitride film 13. Next, the substrate 11 is ground from the side opposite to the substrate 15. After the distortion caused by grinding is eliminated by etching, the surface of the substrate 15 is polished again. Then, the device is subjected to the LSI process including element separation at 1000 deg.C or below to make a CMOS.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device formed by a contamination removal method of a completely new concept in place of the gettering technique for contaminants, and a method for manufacturing the same.

(Conventional technology) Even with the progress in the development of ultra-clean technologies such as cleaning the VLSI manufacturing environment, cleaning the materials used, and reducing contamination from manufacturing equipment, it is still difficult to complete the VLSI manufacturing process, which spans several hundred steps, with the necessary cleanliness. It can be said that it is difficult to manage. Contamination has continued to occur with a statistically certain probability. This is because while advances in ultra-clean technology have improved the control limits of cleanliness, miniaturization of devices means that even a small amount of contamination can adversely affect the aforementioned device characteristics. For this reason, some kind of gettering method has become an indispensable process for super-I and SI manufacturing.

Conventionally, this gettering technology includes: 1. After diffusing phosphorus from the backside of the wafer in the final process of T and SI, heat treatment is performed at 900 to 1000°C in an oxidizing atmosphere to getter heavy metal contamination into the phosphorus diffusion layer, and low-temperature heat treatment is performed before device formation. There is an intrinsic gettering rig that forms oxygen precipitation nuclei and further performs high-temperature treatment at 1,000 to 1,100° C. to continue precipitating oxygen to these nuclei and getter contaminants there. Oxidation-induced stacking fault (08F) is caused by mechanical strain (backside damage) mechanically applied to the backside of the wafer instead of this broken oxygen precipitated layer.
There is also a method of forming a trap and letting the contamination get there.

However, both methods have the following problems. One of them is gettering temperature.

For backside damage, a temperature of approximately 1000° C. or higher is required for O8F growth and sloughing. In the intrinsic gettering, the temperature at which oxygen precipitates,
A temperature of 900°C or higher is required.

It is known that in the case of a phosphorus getter, it is difficult to sufficiently diffuse phosphorus at low temperatures due to the temperature dependence of the diffusion coefficient of phosphorus. When such a high temperature heat treatment process is required,
As the miniaturization of VLSI progresses, the distance between each element becomes shorter, and the depth of pn junctions such as FET sources and drains becomes shallower, making it easier to form junctions with phosphorus, arsenic, boron, etc., and control threshold voltages. It is necessary to suppress diffusion of localized doped regions during high-temperature processing as much as possible.
The process temperature is required to be 900° C. or lower, 800 to 850° C., but this cannot be met. Another problem is the three-dimensional design of the device structure. Some 4MDRAMs have a three-dimensional memory cell structure compared to IMDRAMs.

Furthermore, as we progress from 16 MDRAM to 256 MDRAM, increasingly complex three-dimensional structures are required. With such a structure, it is extremely difficult to suck out (getter) the contaminated heavy metals that have gathered in areas with large co-toxic local strains with the back surface, and it is even impossible to suck them out. In other words, as the miniaturization of VLSI progresses, the process temperature decreases,
As device structures become three-dimensional (more complex), it becomes difficult to incorporate effective gettering into the process.

(Problems to be Solved by the Invention) Conventional semiconductor device manufacturing methods require a high-temperature heat treatment process to getter away contamination, which is extremely inappropriate for advancing the miniaturization of elements. There is a problem in that it is not possible to effectively getter the contamination that has gathered locally in a complicated device, and it is not possible to provide a highly reliable device.

The invention was made in view of the above problems, and the purpose is to provide a highly reliable semiconductor device that does not require high-temperature heat treatment necessary for gettering and does not have to worry about collecting contamination locally on the device. . To provide such a device,
A completely new concept is required to replace traditional gettering techniques. A further object of the present invention is to provide a method for manufacturing a semiconductor device that can easily form such a device.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, a first invention provides a semiconductor device characterized in that a barrier layer for preventing the passage of heavy metals is provided inside a semiconductor substrate. .

1. The second invention includes a step of joining a pair of semiconductor substrates via a barrier layer that prevents the passage of heavy metals, and then forming an element on the surface of one of the semiconductor substrates at a temperature lower than the barrier layer formation temperature. The present invention provides a method for manufacturing a semiconductor device characterized by comprising steps.

Furthermore, the third invention includes a step of bonding a pair of semiconductor substrates via a barrier layer that prevents passage of heavy metals, and then,
The present invention provides a method for manufacturing a semiconductor device, comprising a step of forming an element on the surface of the semiconductor substrate at a temperature of 1000° C. or lower. This temperature is preferably 800°C or lower, particularly 600°C or lower.

Furthermore, a fourth invention includes a step of ion-implanting an impurity into one surface of a semiconductor substrate having two main surfaces at a concentration exceeding the solid solubility limit in the substrate, and then implanting impurities into the other surface of the semiconductor substrate. The present invention provides a method for manufacturing a semiconductor device characterized by comprising a step of forming elements on a surface.

Furthermore, a fifth invention includes a step of diffusing impurities into one surface of a semiconductor substrate having two main surfaces, a step of depositing a semiconductor layer on the one surface, and then a step of depositing a semiconductor layer on the other surface of the semiconductor substrate. The present invention provides a method for manufacturing a semiconductor device, characterized by comprising a step of forming an element.

Most of it accumulates on the back side of the board on the opposite side. Matatame 1
There is no fear that contaminants will re-diffuse to the surface of the substrate during the heat treatment process during element formation. Therefore, there is no fear that the surface of the substrate, which is the area where the device is to be formed, is constantly exposed to heavy metal contamination, and extremely reliable devices can be easily formed.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

Embodiment 1 FIG. 1 is a sectional view showing the manufacturing process of a CMOS transistor according to a first embodiment of the present invention.

First, an N-type silicon single crystal substrate 11 having a resistivity of 10 Ω·α and a (100) surface is prepared. The resistivity of this substrate may be the same as or higher than that of the substrate 15 described later. The thickness may be the same as or thinner than the normal substrate 15, and in this example, it is 625 μm (
Figure 1(a)).

Next, the surface of the substrate 11 is oxidized to form an oxide film 12. The oxidation was carried out, for example, by thermal oxidation in steam at 1100°C. The oxide film thickness was 1 μm (FIG. 1(b)).

Smoothly, silicon nitride (f[1a) is deposited on the oxide film 12.For example, dichlorosilane and ammonia gas are flowed to deposit 5 Qnm at 800°C (Fig. 1(C)).
).

Furthermore, a silicon oxide film 14 was deposited on the silicon nitride film 13 by, for example, the CVD method. This was deposited to a thickness of 1 μm by flowing silane and oxygen gas (FIG. 1(d)).

Next, the substrate work 1 thus formed and the substrate 15 whose surface was only oxidized were bonded together. The N-type substrate 15 was oxidized in water vapor at 1100° C. to improve adhesion during the bonding process. The oxide film thickness was 0.1 μm. Substrate 11 and substrate 15 were brought into close contact with each other in a nitrogen atmosphere, and maintained at a temperature of 1100° C. for 30 minutes. As a result, the substrate 11 and the substrate 15 have an oxide film 12,
141.14□ and the nitride film 13 (FIG. 1(e)).

As shown later, the substrate 11 was removed by grinding from the side opposite to the substrate 15, leaving a thickness of 25 μm. Next, it was etched by 7 μm using a nitric acid-hydrofluoric acid mixture to remove machining distortion caused by grinding. Next, the surface of the substrate 15 is polished again and the surface flatness (LTV) is 0.6.
Finished to below μm.

The cleaning process after polishing left both the front and back surfaces sufficiently clean. The oxide film 14 is
The oxide films 14+ and 142 are bonded and integrated (FIG. 1(f)).

Then, pcMO8 was created by an LSI process such as element isolation. In order to perform element isolation, a thick field oxide film 18 of, for example, 700° C.m is selectively formed, and then a thin oxide film 19 of 10 to 20 nm, which will become a gate oxide film, is formed. Subsequently, after forming an NFI polysilicon film 20 in which phosphorus is thermally diffused into an undoped polysilicon film that will become a gate electrode, patterning is performed using a normal photolithography method. After (-17), ions are implanted in a self-aligned manner using the gate electrode 20 and the field oxide film 18 as mask materials, thereby forming the p-type layer 17 and the n-type layer 17. are formed respectively.

16 is a p-type well region that was previously formed. This allows pMO8FET and n M O5
PET source/drain regions are formed. In addition, n
When ion-implanting p-type impurities into the MO8 region, 9
Mask the MO8 area with 7 photoresist. Conversely, when ion-implanting n-type impurities into the 9MO8 region, the nMO8 region is masked with a 7-photoresist.

In addition, arsenic or the like is used as the nu impurity, and boron or boron fluoride is used as the p-type impurity (Figure 1 (g)).
.

Next, a CVD oxide film 221 is formed on the entire surface, and this oxide film 22. Open an opening in a predetermined part of the Subsequently, a second polysilicon film 21 is deposited on the entire surface, and patterning is performed using an ordinary photolithography process.

Thereafter, the entire device is covered with an insulating film 222 at 400° C.m, and contact holes (not shown) are opened.

The insulating film 222 is usually made of phosphor glass 1 such as PSG or BPSG.
(Fig. 1 (h)).

Incidentally, all the steps in which the temperature is higher than 600° C. have been completed so far.

Finally, a metallization step is performed and a wiring pattern (not shown) is formed by microfabrication, followed by heat treatment at 450° C. for 15 minutes in a nitrogen atmosphere. After that, a pansivation film (not shown) is applied to protect the entire device.
is deposited throughout.

Through the above steps, an LSI made of CMOS transistors is manufactured. Note that the manufacturing process shown here is an example, and it goes without saying that the order of the steps, the number of steps, etc. will vary depending on the device to be manufactured.

In this embodiment, by forming a layer that does not allow heavy metals to pass through the semiconductor substrate, it is possible to prevent contaminant heavy metals that have entered from the back surface from reaching the device active region near the front surface.

This is because when manufacturing a VLSI, a high-temperature process is performed with the front surface of the substrate protected with an oxide film or a nitride film, except for some openings. On the other hand, when forming openings on the front surface, the entire back surface is etched, so this back surface is often exposed during high-temperature processes, and contaminating heavy metals such as Fe and Ni enter from the back surface of the substrate. reaching the device active area near the surface. This phenomenon can occur in just a few tens of seconds. The method of this embodiment is to prevent the movement of this contaminated heavy metal midway through.

That is, the present invention does not remove contaminant heavy metals by gettering, but rather maintains the device active region clean by forming a barrier layer in the substrate in advance. As the barrier layer, as shown here, the layer 12 of Sin is used.
, 14, and an insulating layer such as the SiN layer 13, which does not allow heavy metals to pass through. The substrate surface is super L
As the SI manufacturing process progresses, oxidation and etching are repeated. Oxidation and etching are repeated on the back side as well. In order to prevent the metal blocking layer from disappearing due to etching, the heavy metal blocking layer formed on the back side must be formed in the area that goes inside the substrate from the back surface layer, rather than forming it on the back surface layer as in the case of bank side damage. Must be. As a result, heavy metal contaminants 23 are deposited within the substrate 81 . In this way, the blocking ability in all steps of the VLSI process does not deteriorate. It is possible to ensure the blocking ability in all stages of the VLSI process based on the Ugyinshōsha palm. In addition, each time the back side is oxidized and etched,
Contamination trapped in the Si layer in this area can be removed.

Example 2 Next, a second example of the present invention will be described. The difference from the previous embodiment is that the barrier layer was formed by ion implantation. In the following embodiments, the same parts as in the previous embodiments are given the same numbers, and detailed explanation thereof will be omitted. Oxygen ions were accelerated at a voltage of 1.5 M eV and a dose of 1.0 x 10 cm from the back side B of a Si substrate prepared in the same manner as in the previous example.
An ion implantation layer 23 is formed by implanting the ions (FIG. 2).

Thereafter, oxygen is collected at a high concentration by heat treatment at a desired temperature, for example, 800° C., to form a barrier layer.

Thereafter, elements are formed on the surface A of the 81 substrate through the usual steps shown in the previous embodiment.

FIG. 3 shows the oxygen concentration along the depth direction from the back surface B of the substrate. The solid line is the flow file immediately after ion implantation.
The broken line indicates the profile /l/T after heat treatment. As is clear from this figure, in order for the ion implantation layer 23 to function as a barrier layer, a stable chemical ratio of silicon oxide is required.
It is necessary that the oxygen atom concentration be at least twice that of silicon atoms, and this is achieved by collecting oxygen through heat treatment (region indicated by width t). The width t of the sweet octopus-like area needs to be at least about 100 OA to 7 ooo; preferably 200 OA to 4 ooo.

By doing so, an SI substrate having a preferable barrier layer can be prepared, and elements can be formed in the same manner as in the previous embodiment, and the same effects can be obtained. Furthermore, in addition to this effect, the manufacturing process is simplified because the barrier layer can be formed by one ion implantation.

Embodiment 3 FIG. 4 is a sectional view showing the manufacturing process of a CMOS transistor according to a third embodiment of the present invention. First, resistivity 1
An N-type silicon single crystal substrate 11 having a resistance of 0 Ω·m and a (100) surface is prepared (FIG. 4(a)).

Next, the surface of the substrate 11 is oxidized to form an oxide film 12. Oxidation was carried out in steam at 1100°C.

The oxide film thickness was 1 μm (FIG. 4(b)).

Next, the surface of the substrate 11 is protected with a photoresist 40,
Etch and remove only the oxide film on the back side (see Figure 4).
C)).

Next, phosphorus was diffused only on the back surface of the substrate 11 for 1 hour in an oxidizing atmosphere using POCIs as a source at 1100° C. to form a phosphorus diffusion layer 41. Accordingly, this phosphorus diffusion layer 41 has 5
×10/c! It becomes a high concentration layer of about I. After that, board 1
Only the phosphor glass layer (not shown) formed on the back surface of the substrate 1 is etched and removed (FIG. 4(d)).

Thereafter, a silicon layer 42 was epitaxially grown to a thickness of 10 μm at 1000° C. using dichlorcycine and hydrogen. This completes the substrate required for element formation (FIG. 4(e)).

Thereafter, 0MO8 was created by an LSI process such as element isolation. First, a p-type well region was formed by, for example, ion implantation (FIG. 4(f)).

Next, in order to perform element isolation, a thick field oxide film 18 of, for example, 700 nm is selectively formed, and then a thin oxide film 19 of 10 to 20 nm, which will become a gate oxide film, is formed. Subsequently, a male polysilicon film in which phosphorus is thermally diffused is formed on the undoped polysilicon film that will become the gate electrode, and then buttering is performed using a normal photolithography method to form the gate electrode 20. Thereafter, by using the gate electrode 20 and the field oxide film 18 as a mask material, ions are implanted in a self-aligned manner. , an n-layer 17□ is formed. As a result, pMO8 and nMO8 source/drain regions are formed. Note that when ion-implanting n-type impurities into the 0MO8 region, the 9MO8 region is masked with a photoresist.

Conversely, when ion-implanting n-type impurities into the 9MO8 region, the 0MO8 region is masked with a photoresist. Furthermore, as an n-type impurity, boron or boron fluoride is used as an arsenic pm impurity (see Fig. 4 (g)).
)).

Next, a CVD oxide film 221 is formed on the entire surface, and an opening is opened in a predetermined portion of this oxide film 22+. Subsequently, a second polysilicon film is deposited on the entire surface and patterned using a normal photolithography process to form interconnections 21. Thereafter, the entire device is covered with a 400 nm insulating film 222, and contact holes are formed. The insulating film 222 is usually made of PS.
A phosphorus glass film such as G or BPSG is used. With the above steps, all processes at temperatures above 600°C are completed (Figure 4 (
h)).

Finally, a metallization step is performed to form a wiring pattern (not shown) by microfabrication, followed by heat treatment at 450° C. for 15 minutes in a nitrogen atmosphere. After that, a batacivation film (not shown) is applied to protect the entire element.
is deposited throughout.

Through the above steps, an LSI made of CMOS transistors is manufactured. Note that the manufacturing process shown here is an example, and it goes without saying that the order of the steps, the number of steps, etc. may vary depending on the device to be manufactured.

Even in this case, in addition to producing the same effects as in the first embodiment, the following can also be said. As a barrier here, a highly concentrated phosphorus layer 41 that does not allow heavy metals to pass was used. In order for this layer to work to trap contaminated metal atoms when they pass through the high concentration phosphorus layer 41, the phosphorus concentration must be 10/l:a
More than that is required. It is also more effective to create a structure in which a high concentration of crystal defects remains in a layer containing high concentration of phosphorus.

This may be formed, for example, by utilizing the phenomenon that crystal defects such as dislocations are introduced when forming a high concentration phosphorus diffusion layer. Judging from the results of migration, this dislocation seems to have the effect of trapping contaminant metals. Furthermore, a two-layer structure consisting of a layer containing high concentration of phosphorus and a phosphorus glass layer is also effective. In addition, the phosphorus glass layer formed during phosphorus diffusion may be utilized without being removed.

Example 4 In the previous third example, the phosphorus diffusion groove glass layer was removed and epitaxial growth was performed, but in this example, the phosphorus glass layer was left in the groove manufacturing process, which is the third point. This is different from the example. In this case, after performing the steps in FIGS. 4(a) to 4(C) of the third embodiment, the phosphor glass layer 50 is left (FIG. 5(a)).

When a silicon layer 51 is subsequently grown on this layer, a single crystal epitaxial growth layer is not obtained, but a polycrystalline silicon layer is obtained. However, since 0MO8 elements are not formed in this polycrystalline layer, it does not matter whether it is single crystal or polycrystalline (FIG. 5(b)).

Furthermore, the subsequent steps are shown in FIG. 4 (f) shown in the third embodiment.
) to FIG. 4(h) are performed. In this case, the phosphorus diffusion layer and the phosphorus glass layer have the effect of blocking heavy metal contamination.

This embodiment also provides the same effects as the third embodiment.

Further, instead of this epitaxial layer, a layer formed by other film deposition methods such as sputtering may be used. Furthermore, the material of this layer is not limited to St, but a material that does not distort the conductivity type with respect to the substrate material, such as Ge or C (diamond), which is a group II raw conductor, can be used when using an 81 substrate. , SiC, etc. may also be used.

Embodiment 5 FIG. 6 is a sectional view showing a fifth embodiment of the present invention. 4(a) to 4(a) of the third embodiment.
After going through the process shown in C), the acceleration energy is 1.5 MeV.
Carbon was ion-implanted into the back surface B of the wafer at a dose of 2×10 /d to form a carbon-implanted layer 60 (see FIG. 6).

The carbon distribution at this time is as shown in Figure 7, at a depth of 20 mm.
The peak concentration in μm was 2.9 x 10''/cfl.

The solid solubility limit of carbon in silicon is 3×10/i or less, but in FIG. 7, the carbon concentration from a depth of 1.7 μm to 2.3 μm exceeds this solid solubility limit. Carbon exceeding the solid solubility limit precipitates in the LSI manufacturing process described below, resulting in a high concentration of crystal defects.

After this step, the steps shown in FIG. 4(f) to FIG. 4(h) were performed to create an LSI consisting of CMO8FET.

This embodiment also provides the same effects as the third embodiment.

Here, a layer that does not allow heavy metals to pass through has an extremely high concentration of crystal defects and is used as a barrier. In this embodiment as well, the substrate surface is repeatedly oxidized and etched as the VLSI manufacturing process progresses. Oxidation and etching are repeated on the back side as well. Therefore, in order to prevent the metal blocking layer from disappearing due to etching, the heavy metal blocking layer formed on the back side should not be formed on the back surface as in the case of bank side damage, but should be formed in the area that enters the inside of the substrate from the back surface. There must be. This makes it possible to ensure blocking capability in all steps of the VLSI process.

The ion implantation conditions in this embodiment require that crystal defects be formed at such a high density that contaminating metals cannot pass through. In order to form crystal defects at a high density, it is desirable that the concentration of the implanted ions exceeds the solid solubility limit. for example,
Carbon is 4×1017/Ca, nitrogen is 5×1
Ions are implanted to a peak concentration of 0/6A or more. Further, in the oxidation process during the LSI process, the surface of the silicon substrate becomes an oxide film and cracks. If defects exist very close to the surface, they will be incorporated into the oxide film during the oxidation process and shattered. In order to avoid this, it is better to make the depth of defects 1 μm or more.

The present invention is not limited to the above embodiments, and as a result of detailed study, it has been found that the following embodiments may be used.

■The substrate may be a semiconductor substrate, and instead of Sl, other group II raw conductors such as Ge or compound semiconductors such as 5iGe may be used.
, GaAs, etc. may also be used.

■Elements are not limited to MOS type F'ET, but MI
It may be an S type or Schottky junction type FET, and furthermore, other elements such as a bibora transistor, an MO8 type capacitor, a diode, etc. may be used instead of an FET.

■ Phosphorus was diffused to form a barrier layer, but in place of phosphorus, other conductive impurities are used, such as poron and other impurities that do not increase the soak current. Groups IV and ■ may also be used.

■A barrier layer was formed by ion-implanting oxygen or carbon, but instead of these impurity oxygen, other m, ■.

Group (2) elements such as nitrogen, boron, phosphorus, tin, Ge, inert gases such as argon, xenon, krypton, etc., or any combination of these may be used.

〔Effect of the invention〕

According to the above configuration, high-temperature heat treatment is not required for the gesoterization process, and contamination is not collected locally on the element.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the invention, FIG. 2 is a diagram showing a second embodiment of the invention, FIG. 3 is a diagram explaining a second embodiment of the invention, and FIG. 4 shows a third embodiment of the invention, FIG. 5 shows a fourth embodiment of the invention, FIG. 6 shows a fifth embodiment of the invention, and FIG. FIG. 5 is a diagram illustrating a fifth embodiment of the present invention. 11.15...Si substrate, 12.14...silicon oxide film, 13...silicon nitride film, 16...p-type well region, 17. ...n-type layer, 172...p-type layer, 1
8... Fill oxide film, 19... Gate oxide film, 2
0... Gate electrode, 21... Wiring, 22... Interlayer insulating film.

Claims (5)

[Claims] (1) A semiconductor device characterized by having a barrier layer inside a semiconductor substrate that prevents passage of heavy metals. (2) A step of joining a pair of semiconductor substrates via a barrier layer that prevents the passage of heavy metals, and a step of forming an element on the surface of one of the semiconductor substrates at a temperature lower than the barrier layer formation temperature. A method for manufacturing a semiconductor device characterized by the following. (3) A process comprising a step of bonding a pair of semiconductor substrates via a barrier layer that prevents the passage of heavy metals, and a step of forming an element on the surface of the semiconductor substrate at a temperature of 1000° C. or less. A method for manufacturing a featured semiconductor device. (4) On one side of a semiconductor substrate having two main surfaces,
A method for manufacturing a semiconductor device, comprising the steps of ion-implanting an impurity at a concentration exceeding a solid solubility limit in the substrate, and then forming an element on the other surface of the semiconductor substrate. (5) On one side of a semiconductor substrate having two main surfaces,
A method for manufacturing a semiconductor device, comprising the steps of diffusing impurities, then depositing a semiconductor layer on the one surface, and then forming an element on the other surface of the semiconductor substrate.