JPH0410040A - Memory module - Google Patents

Abstract

PURPOSE:To reduce the measuring frequency and to shorten the measuring time for the performance of a memory module by providing a test circuit on the same substrate as a memory IC to decide the coincidence or noncoincidence of the output values received from plural data output terminals connected to the memory IC. CONSTITUTION:A memory module contains a test circuit 10 on the same substrate as the memory IC 1 - 8, and the wirings which are applied to the input/ output terminals I/O1 - I/O8 are branched out and connected to the circuit 10. The output of the circuit 10 is inputted to the gate of an N type transistor 15 provided at the wiring applied to the terminal I/O 1. Thus the circuit 10 is provided on the same substrate as the memories IC 1 - 8 in order to decide whether the outputs given from plural output terminals are coincident or not with each other. As a result, it is not required to increase the number of I/O output comparators of a measuring instrument nor to repeat plural times of measurement with the switch of I/Os for measurement of the performance of the memory module. Then the performance of the memory module can be easily and quickly measured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory modules, and more particularly to a test circuit for a memory module equipped with a plurality of memory ICs.

[Prior Art] As shown in FIG. 5, a conventional memory module is one in which a plurality of memory ICs 1 to 8 are surface-mounted on a circuit board 1, and each memory IC is mounted on the edge of the board 1. ICI~
Data input/output terminals l101 to l10 connected to IC8
Functionally necessary terminals such as 8 are provided. FIG. 4 shows the circuit wiring of this memory module.

As shown, each of the memories ICI to IC8 has a data input terminal DIN and a data output terminal DOUT, and these DIN and DOLIT are commonly connected to the input/output terminal I10 of the memory module. That is, the input/output terminals I10 to I108 are connected to each memory ICI to I10, respectively.
It also serves as a data input terminal to C8 and a data terminal. Note that other functionally necessary terminals provided in the memory module (for example, address terminals AO-A9, etc.) are shared by the memories ICI to IC8.

[Problem to be solved by the invention] The conventional memory module described above has a plurality of input/output terminals l.
101 to 108 are provided. Furthermore, if the mounted memory IC is of a multi-bit type, the number of input/output terminals in the module will further increase.

For this reason, when measuring the performance of a memory module, a correspondingly large number of I10 comparators are required on the measuring device side, which not only increases the cost of preparing the device but also complicates the measurement work.

In addition, if there are few I10 comparators on the measuring device side, the I/○ must be switched each time the memory module is measured and measurements must be made multiple times, which may have the disadvantage of lengthening the measurement time. .

[Differences between the invention and the prior art] In a memory module in which a plurality of memory ICs are mounted on a substrate and has a plurality of data output terminals (data input/output terminals), the present invention can mount a test circuit on the same substrate by TTL or the like. It is determined whether the output values from all the data output terminals of the module match based on the output from this test circuit, and the performance is measured based on this result.

[Means for Solving the Problems] A memory module of the present invention includes a plurality of memory ICs mounted on a substrate and a plurality of data output terminals connected to each of these memory ICs. It is characterized by having a test circuit for determining whether the output values from the terminals match or not on the same substrate as the memory IC.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a test circuit according to an embodiment of the present invention, and FIG. 2 is a circuit wiring diagram of a memory module according to an embodiment of the present invention. Memory module is memory ICI
~A test circuit 10 is provided on the same board as IC8. This test circuit 10 has input/output terminals 1101 to l1.
The wiring to 0S is branched and connected, and test circuit 1
The output from 0 is input to the gate of an N-type transistor 15 provided in the wiring to the input/output terminal l101. To further explain the test circuit 10, wires 19a to 19h branched from the data input/output wires of the memories IC1 to IC8 on the module board are connected to the NAND gate 11 and the NOR gate 1.
2, and the output 21 of the NOR gate 12 is input to the NOT circuit 13. Empty bat on module 1
Wiring 23 from 6 and NOT circuit 13 output wiring 22 and N
The output 20 of the AND gate 11 is input to the NAND gate 14. Note that the wiring 23 and the ground are connected to a high resistance 17 in order to lower the wiring 23 to the ground potential. N-type MOS for wiring from memory ICI to input/output terminal ■/○l
) A transistor 15 is interposed, and the output 24 of the NAND gate 14 is input to the gate of the MOS transistor 15.

The above NAND gates 11, 14, NOR gate 12,
NOT circuit 13. MOS) Ranjista 15, Pat 16
, a resistor 17, and each wiring constitute a test circuit 10.

Next, the operation will be explained with reference to FIGS. 3(a) and 3(b).

First, the same data ('1
”), the output values from all memories IC1 to IC8 should match when reading.Here, as shown in FIG.
When the outputs from C1 to IC8 match, the inputs of the NAND gate 11 and the NOR gate 12 match, so the output signals 20 and 21 match. That is, N
Since the output signal 21 of the OR gate 12 is input to the NOT circuit 13, the input signals 20 and 2 of the NAND gate 14 are
2 is always inverted, so 8 of the NAND gate 14
The power 24 is always at a high level, and the MOS transistor 15 is turned on.

On the other hand, as shown in FIG. 3(b), all memory ICI
~If the outputs from IC8 do not match, signal 20
and 22 are both at a high level, and test putt 1
When a high level signal is applied to NAND gate 6 from the outside, the input signal of the NAND gate 14 is always at high level, so the NA
A low level signal is provided as the output 24 of the ND gate 14.

Therefore, since the MOS transistor 15 is turned off, the input/output terminal 110f becomes in a high impedance state. Therefore,
With the same data written to all memories ICI to IC8, you can check whether the outputs from all input/output terminals match by measuring only input/output terminal 101, that is, whether the memory module is operating normally. Can be measured.

Incidentally, in the above embodiment, a memory module is shown that is equipped with a data input/output terminal in which data input and data output are shared, but the data output terminal D0 is used without such a commonality.
The present invention can be similarly applied to a memory module including a plurality of tJTs.

[Effects of the Invention] As explained above, the present invention provides a test circuit for determining whether or not outputs from a plurality of output terminals match on the same substrate as a plurality of memory ICs, so that the memory module When measuring performance, it is possible to perform the work easily and quickly without increasing the number of I10 output comparators on the measuring instrument side and eliminating the need to repeat measurements multiple times by switching Ilo. There is.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a test circuit according to an embodiment of the present invention;
2 is a circuit wiring diagram of a memory module according to an embodiment of the present invention, FIGS. 3(a) and 3(b) are waveform diagrams explaining the operation, and FIG. 4 is a circuit wiring diagram of a conventional memory module. 5
The figure is a plan view showing its appearance. 10...Test circuit, 11...
・・・・・・NAND circuit, 12・・・・・・・・・
NOR circuit, 13...N07 circuit, 1
4・・・・・・・・・NAND circuit, 15・・・・・・
・・・Transistor, 16 ・ ・ ・ ・ ・
φ ・ 17 φ ・ ・ ・ ・ ・ l101~l108・1~8 fists...Module empty bat, high resistance, module input/output terminal, memory IC.

Claims (1)

[Claims] A plurality of memory ICs are mounted on the board, and these memory ICs are
A memory module having a plurality of data output terminals each connected to a memory IC is characterized by having a test circuit for determining whether or not output values from these data output terminals match on the same board as the memory IC. memory module.