JPH04100275A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an MOS type transistor wherein the leak current between the source and the drain is reduced, by forming an insulating film on a second conducting film formed on an insulative substrate and a conducting film of a first conductivity type, and forming a third conducting film of a first conductivity type on said insulating film. CONSTITUTION:After polysilicon 102 is sputtered on the whole surface of an insulative substrate, P-type impurities BF2<+> is ion-implanted in the whole surface. After a pattern is formed by using a positive resist layer, a pattern 103 is formed by anisotropic etching. After polysilicon is sputtered on the whole surface, a silicon oxide film 106 is formed on the whole surface by thermal oxidation. Then a polysilicon film 104 containing P-type impurities and an undoped polysilicon film 105 are formed. After a polysilicon film 107 is formed on the whole surface, and BF2<+> is ion-implanted, a gate electrode 108 is formed by anisotropic etching. As the result, the film thickness of a channel region is thin as compared with that of a source.drain region, so that a thin film transistor wherein the leak current in the source.drain region is small can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a MOS semiconductor device comprising a thin film transistor (hereinafter referred to as TPT).

[Prior Art] As semiconductor devices become smaller and more highly integrated, MoS transistors are also becoming smaller, but there is a limit to how much the two-dimensional brainer technology can reduce the cell area. This led to the idea of three-dimensional integrated circuits. This three-dimensional integrated circuit has many advantages over two-dimensional brainer technology. Particularly important from the viewpoint of application to MOS memory are high density, high integration, and low soft errors caused by alpha rays. One of these three-dimensional integrated circuits is the TFT (Thin F
ilm Transistor). This TPT
The manufacturing method will be explained using FIG. 2.

First, a polysilicon film is formed on an insulating substrate 201 by the CVD method, and then phosphorus, which is an N-type impurity, is ion-implanted over the entire surface of the wafer to form an N- impurity layer 202. (FIG. 2(a)) Next, as shown in FIG. 2(b), the N- impurity layer 202
After removing unnecessary portions by photolithography, a gate oxide film 203 is formed by thermal oxidation. Subsequently, after forming a polysilicon film by the CVD method, a gate electrode 204 is formed by photolithography as shown in FIG. 2(C). Next, using the gate electrode 204 as a mask, boron, which is a P-type impurity, is ion-implanted to form a P10 impurity layer 205 as shown in FIG.

[Problem B to be Solved by the Invention] One of the major features of SRAM is that the standby current is low enough to allow battery backup. However, as memory capacity increases, it is becoming difficult to keep the standby current low. Also, it is impossible to create a stable transistor unless there is a margin of 45 orders of magnitude against leakage current. However, MO as described in the prior art
Type 3 silicon thin film transistors have the disadvantage that the leakage current between the source and drain regions is larger than that of single crystal transistors. One way to improve this is to reduce the thickness of the polysilico film. (For example, “HighPerfo
rmance SOIMOSFET Using
Ultra-thin S.

IFil, m”: Toshiba VLSI
Research Center: 640-IED
(M87') However, in this case, the silicon film thickness of the source and drain regions is also thinned at the same time, so the resistance value of the source and drain regions becomes high and the operation speed becomes slow.

The present invention is intended to solve these problems, and its purpose is to provide an MO3 type transistor in which the leakage current between the source and drain is kept low and the resistance values of the source and train are kept low. .

Another object of the present invention is to form a gate electrode by etching back and to omit a photo process, thereby achieving stable MO.
An object of the present invention is to provide an S-type thin film transistor.

[Means for Solving the Problems] ■The method of manufacturing a semiconductor device of the present invention includes the steps of forming a first conductive type conductive film on a mismatchable substrate, and forming a pattern using the first conductive type conductive film. forming a second conductive film on the insulating substrate and the first conductive type conductive film; forming an insulating film on the second conductive film; The method is characterized by comprising a step of forming a third conductive film of the first conductivity type thereon, and a step of forming a gate electrode by etching back the third conductive film.

■The method of manufacturing a semiconductor device of the present invention includes a step of forming a first insulating film on a semiconductor substrate, a step of forming a conductive film of a first conductivity type on the first insulating film, and a step of forming a conductive film of the first conductivity type on the first insulating film. a step of forming a pattern using a conductive film, a step of forming a second conductive film on the first insulating film and the first conductive type conductive film, and a step of forming a second conductive film on the second conductive film. a step of forming an insulating film, a step of forming a third conductive film of a first conductivity type on the second insulating film, and a step of forming a gate electrode by etching back the third conductive film. It is characterized by consisting of.

[Example] Hereinafter, the present invention will be described in detail based on examples.

The first diagram is a diagram showing an embodiment of the present invention in order of steps. 10
1 is a picture-edge semiconductor substrate, 102 is a polysilicon film, 10
3, 104 is a source region and drain region made of a P-type polysilicon film in which boron is implanted as an impurity into a 102 polysilicon film (BF2'' in this example), 105 is a channel forming region, and 106 is used as a gate oxide film. A silicon oxide film, 107 is a polysilicon film, and 108 is a gate electrode formed by 107.

First, as shown in (a), polysilicon 102 is sputtered by 2000 to 3000 people over the entire surface of an insulating substrate by the CVD method. It is usually deposited by thermally decomposing monosilane gas at 620°C. An amorphous silicon film thermally decomposed at 560°C may also be used. Next, a P-type impurity, in this example, BF2'' is applied to the entire surface at an energy of 60 Kev and a dose of 4XIQ.
Implant ions with ls. Next, a pattern is formed using a positive resist layer by photolithography, and then a pattern 103 is formed by anisotropic etching as shown in FIG. Next, as shown in the figure (C), polysilicon 104 is sputtered to a thickness of 500 to 100 OA over the entire surface by CVD, and then a silicon oxide film 106 is formed over the entire surface by thermal oxidation.

At this time, boron with a large diffusion coefficient diffuses into the non-doped polysilicon, and as shown in (e) the polysilicon film 104 containing P-type impurities and the non-doped polysilicon film 1.
05 is formed. Next, as shown in figure f, a polysilicon film 107 is formed on the entire surface by the CVD method, and a B F 2" film is formed on the entire surface.
After ion implantation with an energy of 60 Kev and a dose of 4.times.10@15, anisotropic etching is performed in CF, :02=5:1 gas to form a gate electrode 108 as shown in figure g.

According to this embodiment, since the polysilicon film in the channel region is thinner than the polysilicon film in the source and drain regions, the channel region is strongly influenced by the gate electrode when ON, so that the ON current (gate voltage 5. 0V, the drain current (at a train voltage of 5.0V) increases. Furthermore, since the P-N junction surface is small in the OFF state, the leakage current flowing at the P-N junction surface can be small. As a result, the ○N/○FF ratio of the TFT according to this embodiment becomes large, and the MOS
) The driving ability of the transistor can be increased.

In addition, in this example, the gate electrode is embedded in the TFT via the gate oxide film and is formed by etching back the entire surface, so unlike the conventional gate electrode formation, a mask is not used and the photo process can be omitted. This leads to shortening of process steps, and enables the provision of high-yield, high-quality thin film transistors.

Note that although a PMOS transistor was used in this example, N
A similar effect can be obtained with a MOS transistor.

Further, although an insulating semiconductor substrate is used in this embodiment, a similar effect can be obtained by using a conductive semiconductor substrate on which a silicon oxide film is formed.

Further, in this embodiment, a polysilicon film doped with impurities was used for the gate electrode, but similar effects can be obtained by using a high melting point metal or its silicide.

[Effects of the Invention] According to the present invention, the following effects can be expected.

- In MO8-way thin film transistors, the thickness of the channel region is thinner than that of the source and drain regions, making it possible to create thin film transistors with small leakage currents and high ON current in the source and drain regions.

■Since the gate electrode is formed by etch-back without using photoresist, it is possible to produce high-yield, high-quality thin film transistors.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(g) are step-by-step sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 2(a) to 2(d) are diagrams showing a conventional method of manufacturing a semiconductor device. 101.201 Insulating semiconductor substrate 102.104, 105, 107 Polysilicon film 103.104, 205 P-type polysilicon film 106
．． 203 Silicon oxide film 108.204 Gate electrode polysilicon film or higher

Claims (2)

[Claims] (1) A step of forming a first conductive type conductive film on an insulating substrate, a step of forming a pattern using the first conductive type conductive film, and a step of forming a pattern on the insulating substrate and the first conductive type conductive film. forming a second conductive film on the second conductive film; forming an insulating film on the second conductive film; and forming a third conductive film of a first conductivity type on the insulating film; A method for manufacturing a semiconductor device, comprising the step of forming a gate electrode by etching back the third conductive film. (2) Forming a first insulating film on a semiconductor substrate, forming a first conductive type conductive film on the first insulating film, and forming a pattern using the first conductive type conductive film. a step of forming a second conductive film on the first insulating film and the first conductive type conductive film; and a step of forming a second insulating film on the second conductive film. , comprising a step of forming a third conductive film of a first conductivity type on the second insulating film, and a step of forming a gate electrode by etching back the third conductive film. A method for manufacturing a semiconductor device.