JPH0397254A - Ic lead terminal - Google Patents

Ic lead terminal

Info

Publication number
JPH0397254A
JPH0397254A JP23347089A JP23347089A JPH0397254A JP H0397254 A JPH0397254 A JP H0397254A JP 23347089 A JP23347089 A JP 23347089A JP 23347089 A JP23347089 A JP 23347089A JP H0397254 A JPH0397254 A JP H0397254A
Authority
JP
Japan
Prior art keywords
lead terminal
lead terminals
solder
sop
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23347089A
Other languages
Japanese (ja)
Inventor
Takatoshi Yasuda
安田　孝寿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23347089A priority Critical patent/JPH0397254A/en
Publication of JPH0397254A publication Critical patent/JPH0397254A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To avoid the short circuit with adjacent lead terminals by providing a groove in one part of lead terminal surface to be soldered onto a substrate. CONSTITUTION:The rear surface of lower side horizontal part 2c in contact with a substrate 3 is soldered onto the substrate 3. A groove 4 opened on the rear surface side of the lower horizontal part 2c is formed along the long direction of the horizontal part 2c. An SOP 1 is provided with multiple lead terminals 2 as shown by only one terminal 2 as an example while it is a matter of course that respective lead terminals 2 are provided with the groove 4. When the SOP 1 is mounted on the substrate 3, the respective lead terminals 2 are fixed to the substrate 3 through the intermediary of solder. At this time, any surplus solder produced in such a process can run into the grooves 4 of the respective lead terminals 2 so as not to run into any other lead terminals 2.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は．ＩＣのリード端子に関し，特にスモールアウ
トラインパッケージ（以下．ｓｏｐと称する。）ＩＣの
リード端子に関する． ［従来の技術］ 従来のＳＯＰとしては，例えば′８９三菱半導体ＩＣパ
ッケージｍ（三菱電気株式会社半導体事業部　１９８９
年２万発行）の３−６６頁に示されているものが知られ
ている．第４図は、このような従来のｓｏｐの平面図で
、（１）はｓｏｐ、（２）は、このｓｏｐのリード端子
、（３）は、Ｓ　Ｏ　Ｐ　（１）がハンダ付けされる基
板である。このＳ　Ｏ　Ｐ　（１）では、リード端子（
２）は、基板（３）にフローハンダ付け或るいはりフロ
ーハンダ付け等の手段によって接続固定されている． ［発明が解決しようとする課題］ 上述した従来のＳ　Ｏ　Ｐ　（１）では、フローハンダ
付け或るいはりフローハンダ付けによって、各リード端
子（２）を基板（３）に実装しているので，隣接するリ
ード端子（２）の間隔が非常に狭い多ピンのＳ　Ｏ　Ｐ
　（１）では、実装する際に余分なハンダが隣接するリ
ード端子（２）に流れてしまうハンダブリッジ現象が起
こる．その結果、リード端子（２）同士を短絡してしま
うので、基板実装における歩留り低下、システムの誤動
作等の問題が生じ、半導体製品の高集積化に伴なう多ピ
ン化を妨げていた． 本発明は、上記のような問題点を解決するためになされ
たもので、隣接するリード端子の間隔が非常に狭いＳＯ
Ｐをハンダを用いて実装する際に，余分なハンダが発生
しても、これによって隣接するリード端子が短絡される
ことを防止すると共に，基板実装における歩留りの向上
と半導体製品の高集積化に伴なう多ピン化ＳＯＰを得る
ことを目的とする． ［課題を解決するための手段］ 上記の問題点を解決するために、本発明は、基板上にハ
ンダを用いて実装する表面実装用のＩＣのリード端子に
おいて，基板にハンダ付けされるリード端子面の一部に
溝を設けたものである．また、リード端子に溝を設ける
代りに，リード端子における基板にハンダ付けする面に
ハンダメッキを施し，リード端子の側面にはハンダメッ
キを施していないものとすることもできる．［作用］ リード端子の一部に溝を設けたものでは、ハンダを用い
て表面実装用のＩＣを基板に実装する際に発生する余分
なハンダは，他のリード端子には流れず、リード端子の
一部に設けた溝の中に流れ、隣接するリード端子を短絡
することはない。[Detailed Description of the Invention] [Industrial Application Field] The present invention... This article relates to lead terminals of ICs, and particularly to lead terminals of small outline package (hereinafter referred to as .sop) ICs. [Prior art] As a conventional SOP, for example, '89 Mitsubishi Semiconductor IC Package M (Mitsubishi Electric Corporation Semiconductor Division 1989
The one shown on pages 3-66 of 20,000 issues published annually) is known. Figure 4 is a plan view of such a conventional SOP, where (1) is the SOP, (2) is the lead terminal of this SOP, and (3) is the board to which the SOP (1) is soldered. It is. In this S O P (1), the lead terminal (
2) is connected and fixed to the board (3) by means such as flow soldering or flow soldering. [Problems to be Solved by the Invention] In the conventional SOP (1) described above, each lead terminal (2) is mounted on the board (3) by flow soldering or flow soldering. Multi-pin S O P with very narrow spacing between adjacent lead terminals (2)
In (1), a solder bridging phenomenon occurs in which excess solder flows into the adjacent lead terminal (2) during mounting. As a result, the lead terminals (2) are shorted together, causing problems such as lower yields in board mounting and system malfunctions, which hinders the increase in the number of pins associated with higher integration of semiconductor products. The present invention was made to solve the above-mentioned problems.
Even if excess solder is generated when P is mounted using solder, this prevents adjacent lead terminals from being short-circuited, and also improves the yield of board mounting and increases the integration of semiconductor products. The purpose is to obtain an accompanying multi-pin SOP. [Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides lead terminals for surface mounting ICs that are mounted on a board using solder. A groove is provided on a part of the surface. Furthermore, instead of providing a groove in the lead terminal, the surface of the lead terminal to be soldered to the board may be solder plated, and the side surface of the lead terminal may not be plated with solder. [Function] When a groove is provided in a part of the lead terminal, excess solder generated when mounting a surface-mount IC on a board using solder does not flow to other lead terminals, and the lead terminal It flows into the groove provided in a part of the lead terminal and does not short-circuit adjacent lead terminals.

また、表面実装用ＩＣのリード端子において、基板にハ
ンダ付けする面にはハンダメッキを施し，リード端子の
側面にはハンダメッキを施していないものでは、実装す
る際に発生する余分なハンダは、リード端子の側面には
流れず、隣接するリード端子を短絡することはない． ［実施例］ 第１の実施例を第１図に示す．同図において、（１）は
ＳＯＰ，（，２）はリード端子、（３）は基板である．
リード端子（２）は、Ｓ　Ｏ　Ｐ　（１）の側面から外
方に向って水平に伸延する上側水平部（２ａ）と，この
上側水平部（２ａ）の先端部から外方に向って斜め下方
に伸延する傾斜部（２ｂ）と，この傾斜部（２ｂ）の先
端部から外方に向って伸延する下側水平部（２ｃ）とか
らなる．この下側水平部（２Ｃ）の下面が基板（３）に
接して、ハンダ付けされる．この下側水平部（２ｃ）の
下面側に開口させた溝（４）が，下側水平部（２Ｃ）の
長さ方向に沿って形成されている．なお，第１図では，
リード端子（２）を１つだけ示したが，ＳＯＰ（１）に
は多数のリード端子（２）が設けられ、これら各リード
端子（２）に，上述したように溝（４）がそれぞれ設け
られていることはいうまでもない． この実施例によれば，ＳＯＰ（１）を基板（３）に実装
する場合、各リード端子（２）はハンダを介して基板（
３）に装着される．このとき発生した余分なハンダは，
各リード端子（２）の溝（４）に流れこむため，他のリ
ード端子（２）へ流れだすことはない． ｗ４２の実施例を第２図に示す．この実施例は，第１の
実施例と同様にＳ　Ｏ　Ｐ　（１）の側面からそれぞれ
突出している各リード端子（２）において，隣核するリ
ード端子（２）の側面と対向する側面（２ｄ）にハンダ
メッキを施していないものである．無論，基板（コ）に
ハンダ付けされる面，例えば下側水平部（２Ｃ）の下面
にはハンダメッキが施されている． この実施例によれば，ＳＯＰ（１）を基板（３）に実装
する場合，第１の実施例と同様に各リード端子（２）は
ハンダを介して基板（３）に装着される．このとき発生
した余分なハンダは、他のリード端子（２）に流れず，
ハンダメッキが施されている部分のみに流れる． 上記の第１の実施例では、溝（４）は下側水平部（２Ｃ
）の長さ方向に沿って設けたが、第３図に示すように長
さ方向に直角な溝（４ａ）を設けても同様に動作する． 【発明の効果］ 以上のように，本発明によれば、リード端子に溝を設け
るか、或るいは隣接するリード端子の側面と対向する側
面にハンダメッキを施さない構或を採用しているので、
実装用ＩＣを基板に実装する際に、余分なハンダによっ
てリード端子間が短絡されることがない．従って，基板
実装における歩留りが向上し，システムの誤動作も生じ
ず、高集積化に伴なう多ピン化を図ることができる．In addition, for lead terminals of surface mount ICs, if the surface to be soldered to the board is solder-plated, but the side surface of the lead terminal is not solder-plated, excess solder generated during mounting will be removed. It does not flow to the sides of the lead terminals and does not short-circuit adjacent lead terminals. [Example] The first example is shown in Fig. 1. In the figure, (1) is the SOP, (,2) is the lead terminal, and (3) is the board.
The lead terminal (2) has an upper horizontal part (2a) that extends horizontally outward from the side surface of the S O P (1), and an upper horizontal part (2a) that extends diagonally outward from the tip of this upper horizontal part (2a). It consists of an inclined part (2b) extending downward and a lower horizontal part (2c) extending outward from the tip of this inclined part (2b). The lower surface of this lower horizontal portion (2C) is in contact with the board (3) and soldered. A groove (4) opened on the lower surface side of this lower horizontal portion (2c) is formed along the length direction of the lower horizontal portion (2C). In addition, in Figure 1,
Although only one lead terminal (2) is shown, the SOP (1) is provided with a large number of lead terminals (2), and each lead terminal (2) is provided with a groove (4) as described above. Needless to say, this has been done. According to this embodiment, when mounting the SOP (1) on the board (3), each lead terminal (2) is connected to the board (
3). The excess solder generated at this time is
Because it flows into the groove (4) of each lead terminal (2), it does not flow to other lead terminals (2). An example of w42 is shown in Figure 2. In this embodiment, similarly to the first embodiment, in each lead terminal (2) protruding from the side surface of S O P (1), the side surface (2d) opposite to the side surface of the adjacent lead terminal (2) is ) without solder plating. Of course, the surface to be soldered to the board (C), for example the bottom surface of the lower horizontal part (2C), is plated with solder. According to this embodiment, when mounting the SOP (1) on the board (3), each lead terminal (2) is attached to the board (3) via solder, as in the first embodiment. The excess solder generated at this time does not flow to other lead terminals (2),
It flows only to the parts where solder plating is applied. In the first embodiment described above, the groove (4) is in the lower horizontal part (2C
) is provided along the length direction, but the same operation can be achieved even if a groove (4a) perpendicular to the length direction is provided as shown in FIG. [Effects of the Invention] As described above, according to the present invention, a groove is provided in the lead terminal, or a structure is adopted in which no solder plating is applied to the side surface opposite to the side surface of the adjacent lead terminal. So,
When mounting an IC on a board, there is no possibility of short-circuiting between lead terminals due to excess solder. Therefore, the yield in board mounting is improved, system malfunctions do not occur, and it is possible to increase the number of pins associated with higher integration.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明によるＩＣリード端子を実施したＳＯＰ
の第１の実施例の部分省略斜視図、第２図は同第２の実
施例の部分省略斜視図、第３図は第１の実施例の変形例
を示す図、第４図は従来のリード端子を用いたＳＯＰの
都分省略平面図である。 （１）・・・・・ＳＯＰ、（２）・・・・・リード端子
、（３）・・・・・基板、（４）．　（４ａ）・・・・
溝．代　　理　　人　　　大　　岩　　増　　雄晃１　
図 第２　図Figure 1 shows an SOP that implements an IC lead terminal according to the present invention.
FIG. 2 is a partially omitted perspective view of the first embodiment, FIG. 3 is a diagram showing a modification of the first embodiment, and FIG. 4 is a conventional FIG. 2 is a partially omitted plan view of an SOP using lead terminals. (1)...SOP, (2)...Lead terminal, (3)...Board, (4). (4a)...
groove. Representative Yuaki Oiwa Masu 1
Figure 2

Claims (2)

【特許請求の範囲】[Claims] （１）基板上にハンダを用いて実装する表面実装用のＩ
Ｃのリード端子において、基板にハンダ付けされるリー
ド端子面の一部に溝を設けたことを特徴とするＩＣリー
ド端子。(1) I for surface mounting mounted on the board using solder
An IC lead terminal characterized in that, in the lead terminal of C, a groove is provided in a part of the lead terminal surface to be soldered to a board. （２）基板上にハンダを用いて実装する表面実装用のＩ
Ｃのリード端子において、基板にハンダ付けするリード
端子面にはハンダメッキを施し、リード端子の側面には
ハンダメッキを施していないことを特徴とするＩＣリー
ド端子。(2) I for surface mounting mounted on the board using solder
An IC lead terminal characterized in that the surface of the lead terminal to be soldered to the board is solder-plated, and the side surface of the lead terminal is not solder-plated.
JP23347089A 1989-09-09 1989-09-09 Ic lead terminal Pending JPH0397254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23347089A JPH0397254A (en) 1989-09-09 1989-09-09 Ic lead terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23347089A JPH0397254A (en) 1989-09-09 1989-09-09 Ic lead terminal

Publications (1)

Publication Number Publication Date
JPH0397254A true JPH0397254A (en) 1991-04-23

Family

ID=16955530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23347089A Pending JPH0397254A (en) 1989-09-09 1989-09-09 Ic lead terminal

Country Status (1)

Country Link
JP (1) JPH0397254A (en)

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