JPH0997867A - Substrate for semiconductor device - Google Patents

Substrate for semiconductor device

Info

Publication number
JPH0997867A
JPH0997867A JP25491495A JP25491495A JPH0997867A JP H0997867 A JPH0997867 A JP H0997867A JP 25491495 A JP25491495 A JP 25491495A JP 25491495 A JP25491495 A JP 25491495A JP H0997867 A JPH0997867 A JP H0997867A
Authority
JP
Japan
Prior art keywords
lead
printed wiring
wiring board
end portion
etched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25491495A
Other languages
Japanese (ja)
Inventor
Katsumasa Kawashima
克正 川嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP25491495A priority Critical patent/JPH0997867A/en
Publication of JPH0997867A publication Critical patent/JPH0997867A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405—Edge mounted components, e.g. terminals

Landscapes

  • ing And Chemical Polishing (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To flatten a part surface and a lead surface and to join them compactly by providing half etching at a lead frame and a lead edge part. SOLUTION: A half etching part 2 is formed on either surface of front and rear surfaces which oppose each other in a lead edge part 3. The half etching part 2 in the lead edge part 3 of one lead L1 is joined to such junction part as the conductor terminal part of the edge part surface of a printed wiring board P by melted solder. Also, the half etching part 2 in the lead edge part 3 of the other lead L2 is joined to such junction part as the conductor terminal part on the rear surface of the edge part of the printed wiring board P by melted solder. Lead edges 3, 3 of both leads L1 and L2 are arranged on the front and rear surfaces of the printed wiring board which do not oppose each other. The cut-out surface sides of the half etching part 2 of both leads L1 and L2 are joined to each junction part of the front surface of one edge part and the reverse surface of the other edge part out of both opposing edge parts of the printed wiring board P.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、リードフレームの
リード端部を、プリント配線板など所定部品面に形成さ
れた導電端子部などリード接合部分に接合する際に、接
合し易く且つ良好な接合強度が得られるようにした半導
体装着用基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an easy and good joining when joining a lead end portion of a lead frame to a lead joining portion such as a conductive terminal portion formed on a surface of a predetermined component such as a printed wiring board. The present invention relates to a semiconductor mounting substrate that has high strength.

【０００２】[0002]

【従来の技術】一般にリードフレームは、鉄−ニッケル
合金などの金属薄板材料を、適宜な形状にパターンエッ
チングして形成したものであり、フレーム端部にはピン
形状を有する幅０．５ｍｍ程度の複数本のリード端部が
形成されていて、各リード端部はプリント配線板など、
他の電気部品の所定位置に配置された導電端子部に接続
される。2. Description of the Related Art Generally, a lead frame is formed by pattern-etching a thin metal plate material such as iron-nickel alloy into an appropriate shape, and has a pin shape at the end of the frame with a width of about 0.5 mm. A plurality of lead ends are formed, and each lead end is a printed wiring board or the like.
It is connected to a conductive terminal portion arranged at a predetermined position of another electric component.

【０００３】図６は、従来のリードフレームＬ1 、Ｌ2
を、プリント配線板など所定部品Ｐのリード接合部にそ
のリード端部３にて接合した半導体装置用基板を示す概
要側面図であり、リード端部３とプリント配線板Ｐなど
所定部品との接合面は、リード端部３と所定部品Ｐの導
電端子部（図示せず）とによって電気的に導通状態とな
っている。FIG. 6 shows conventional lead frames L1 and L2.
FIG. 3 is a schematic side view showing a semiconductor device substrate in which a lead end portion 3 is joined to a lead joint portion of a predetermined component P such as a printed wiring board, and the lead end portion 3 is joined to a predetermined component such as the printed wiring board P. The surface is electrically connected by the lead end portion 3 and the conductive terminal portion (not shown) of the predetermined component P.

【０００４】[0004]

【発明が解決しようとする課題】前記半導体装置用基板
においては、図６に示すように、プリント配線板Ｐに接
合した各リードフレームＬ1 、Ｌ2 のそれぞれリード端
部３、３の接合面と反対側の端部とプリント配線板Ｐと
は、できる限り互いにコンパクトに同一面を保持するこ
とが望ましい。In the semiconductor device substrate, as shown in FIG. 6, the lead frames L1 and L2 joined to the printed wiring board P are opposite to the joint surfaces of the lead end portions 3 and 3, respectively. It is desirable that the side end and the printed wiring board P hold the same surface as compactly as possible.

【０００５】また、それぞれ各リード端部３の接合面の
反対側の端部は、プリント配線板Ｐ以外の他の所定部品
に対する通電や接合に使用されるため、図６に示すよう
に、なるべく一方のリードフレームＬ1 に対して他方の
リードフレームＬ2 が同一面を保持するように、他方の
リードフレームＬ2 のリード端部３をクランク状などの
所定形状に屈曲加工している。Further, since the ends of the respective lead ends 3 on the opposite side of the joint surface are used for energizing and joining other predetermined components other than the printed wiring board P, as shown in FIG. The lead end 3 of the other lead frame L2 is bent into a predetermined shape such as a crank shape so that the other lead frame L2 holds the same surface with respect to the one lead frame L1.

【０００６】しかしながら、微細なピン状の複数のリー
ド端部３の屈曲加工は、きわめて高い加工精度が要求さ
れ、また、加工中での折損などの発生を防ぐために、か
なりの熟練と労力を必要としていた。However, the bending work of the plurality of fine pin-shaped lead end portions 3 requires extremely high working accuracy and requires considerable skill and labor to prevent breakage during the working. I was trying.

【０００７】本発明の課題は、大小のリジットタイプ乃
至はフレキシブルタイプのプリント配線板、ＩＣモジュ
ールなど所定部品の導電端子部などの接合部に接合され
るリードフレームのリード端部の屈曲加工を省いて、能
率的にリードフレームを作成し、そのリードにおけるリ
ード端部をプリント配線板など所定部品に対して接合し
易くするとともに接合強度を強化することにある。An object of the present invention is to eliminate bending work of lead end portions of lead frames joined to joint portions such as conductive terminal portions of predetermined components such as large and small rigid type or flexible type printed wiring boards and IC modules. In addition, the lead frame is efficiently prepared, and the lead end portion of the lead is easily joined to a predetermined component such as a printed wiring board and the joining strength is strengthened.

【０００８】[0008]

【課題を解決するための手段】本発明の第１の発明は、
リード端部における互いに相対する表裏面のいずれか一
方面にのみハーフエッチング部が形成されているリード
と、他方面にのみハーフエッチング部が形成されている
リードとが、その一方のリードにおけるリード端部の前
記ハーフエッチング部と他方のリードにおけるリード端
部の前記ハーフエッチング部とをプリント配線板の互い
に対向しない表面と裏面に配置して、それぞれ該プリン
ト配線板の接合部に接合されていることを特徴とする半
導体用基板である。The first invention of the present invention is as follows:
A lead in which a half-etched portion is formed only on one of the front and back surfaces of the lead end portion facing each other and a lead in which a half-etched portion is formed only on the other surface are the lead ends of the one lead. The half-etched portion of the portion and the half-etched portion of the lead end portion of the other lead are disposed on the front surface and the back surface of the printed wiring board that do not face each other and are respectively joined to the joint portion of the printed wiring board. Is a substrate for a semiconductor.

【０００９】次に、第２の発明は、リード端部における
互いに相対する表裏面のいずれか一方面にのみハーフエ
ッチング部が形成されているリードと、他方面にのみハ
ーフエッチング部が形成されているリードとが、前記一
方のリードにおけるリード端部間に他方のリードにおけ
るリード端部を配置し且つ両リードの前記ハーフエッチ
ング部を互いに対向させて、プリント配線板の互いに対
向する表面と裏面の接合部に接合されていることを特徴
とする半導体用基板である。Next, a second aspect of the invention is that a lead having a half-etched portion is formed only on one of the front and back surfaces of the lead end portion facing each other, and a half-etched portion is formed only on the other surface. A lead having a lead end portion of the other lead disposed between the lead end portions of the one lead and the half-etched portions of both leads facing each other, and the front and back surfaces of the printed wiring board facing each other. The semiconductor substrate is characterized in that it is bonded to a bonding portion.

【００１０】次に、第３の発明は、長リード端部と短リ
ード端部とを備え、長リード端部における互いに相対す
る表裏面のいずれか一方面のみにハーフエッチング部が
形成されているリードが、プリント配線板の接合部に前
記長リード端部のハーフエッチング部にて接合され、且
つ該プリント配線板のその他の接合部と前記短リード端
部とを繋ぐワイヤボンディングにより導通接続されてい
ることを特徴とする半導体装置用基板である。A third aspect of the invention comprises a long lead end portion and a short lead end portion, and the half-etched portion is formed on only one of the front and back surfaces of the long lead end portion facing each other. A lead is joined to a joint portion of a printed wiring board at a half-etched portion of the long lead end portion, and conductively connected by wire bonding connecting the other joint portion of the printed wiring board and the short lead end portion. It is a substrate for a semiconductor device characterized in that

【００１１】[0011]

【発明の実施の形態】本発明の半導体装置用基板を実施
の形態に従って以下に詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device substrate of the present invention will be described in detail below according to an embodiment.

【００１２】まず、本発明の第１の発明、第２の発明、
第３の発明のそれぞれ半導体装置用基板に用いるリード
フレームについて説明すれば、図１（ａ）は、第１、第
２の発明のリードフレームＬにおけるリード端部３の部
分拡大平面図であり、鉄−ニッケル合金など金属製の薄
板材料１をパターンエッチングにより複数本のピン状に
貫設したリード端部３である。First, the first invention, the second invention of the present invention,
To explain the lead frames used for the respective semiconductor device substrates of the third invention, FIG. 1A is a partially enlarged plan view of the lead end portion 3 in the lead frame L of the first and second inventions. This is a lead end 3 in which a thin plate material 1 made of a metal such as an iron-nickel alloy is penetratingly formed into a plurality of pin shapes by pattern etching.

【００１３】図１（ｂ）は、第１、第２の発明の半導体
装置用基板に用いるリードフレームＬにおける、リード
端部３のＡ−Ａ部分拡大側断面図であり、前記リード端
部３は、プリント配線板、ＩＣモジュールなど他の電気
部品と接合される接合部であって、リードフレームの厚
さｔは、本発明においては特に限定されるものではない
が、例えば、０．１〜０．３ｍｍ程度である。FIG. 1B is an enlarged sectional view of the lead end 3 taken along the line AA of the lead frame L used for the semiconductor device substrate of the first and second inventions. Is a joint portion to be joined to other electric components such as a printed wiring board and an IC module, and the thickness t of the lead frame is not particularly limited in the present invention, but is, for example, 0.1 to 0.1. It is about 0.3 mm.

【００１４】前記リード端部３の先端部は、該リード端
部３における互いに対向する表裏両面のうちのいずれか
一方面をハーフエッチングにより平坦に切り欠くことに
より形成された厚さｔ1 のハーフエッチング部２（肉薄
部）を備えている。The tip portion of the lead end portion 3 is half-etched with a thickness t1 formed by flatly notching either one of the front and back surfaces of the lead end portion 3 facing each other by half-etching. The portion 2 (thin portion) is provided.

【００１５】次に、第３の発明の半導体装置用基板に用
いるリードフレームを実施の形態に従って以下に詳細に
説明する。Next, the lead frame used for the semiconductor device substrate of the third invention will be described in detail below according to the embodiments.

【００１６】図２（ａ）は、第３の発明の半導体装置用
基板に用いるリードフレームＬにおけるリード端部３の
部分拡大平面図であり、鉄−ニッケル合金など金属製の
薄板材料１をパターンエッチングにより複数本のピン状
に貫設したリード端部３である。FIG. 2A is a partially enlarged plan view of the lead end portion 3 of the lead frame L used for the semiconductor device substrate of the third invention, in which a metal thin plate material 1 such as an iron-nickel alloy is patterned. The lead end portion 3 is formed by penetrating a plurality of pins by etching.

【００１７】図２（ｂ）は、第３の発明の半導体装置用
基板に用いるリードフレームＬにおけるリード端部３の
Ａ−Ａ部分拡大側断面図であり、前記リード端部３は、
プリント配線板と接合される接合部であって、リードフ
レームの厚さｔは、本発明においては特に限定されるも
のではないが、例えば、０．１〜０．３ｍｍ程度であ
る。FIG. 2B is an enlarged sectional view of the lead end portion 3 of the lead frame L used for the semiconductor device substrate of the third invention, taken along the line AA.
The thickness t of the lead frame, which is a joint portion to be joined to the printed wiring board, is not particularly limited in the present invention, but is, for example, about 0.1 to 0.3 mm.

【００１８】図２（ａ）〜（ｂ）に示すように、前記リ
ード端部３は、長リード端部３ａと短リード端部３ｂと
を備え、長リード端部３ａの先端部における互いに相対
する表裏両面のうちのいずれか一方面のみをハーフエッ
チングにより平坦に切り欠くことにより形成された厚さ
ｔ1 のハーフエッチング部２を備え、長リード端部３ａ
は、短リード端部３ｂよりも、おおよそハーフエッチン
グ部２の長さ分だけ長くなっている。As shown in FIGS. 2 (a) and 2 (b), the lead end portion 3 has a long lead end portion 3a and a short lead end portion 3b. The long lead end portion 3a is provided with the half-etched portion 2 having a thickness t1 formed by flatly notching only one of the front and back surfaces.
Is longer than the short lead end portion 3b by about the length of the half-etched portion 2.

【００１９】次に第１の発明は、半導体装置用基板であ
って、その発明の実施の形態を図面に従って以下に詳細
に説明する。Next, a first invention is a semiconductor device substrate, and an embodiment of the invention will be described below in detail with reference to the drawings.

【００２０】図３（ａ）は、第１の発明の半導体装置用
基板の全体平面図、図３（ｂ）は、そのＡ−Ａ側断面図
である。FIG. 3 (a) is an overall plan view of the semiconductor device substrate of the first invention, and FIG. 3 (b) is an AA side sectional view thereof.

【００２１】第１の発明の半導体装置用基板は、リード
端部３における互いに相対する表裏面のいずれか一方面
にのみハーフエッチング部２が形成されているリードＬ
1 と他方面にのみハーフエッチング部２が形成されてい
るリードＬ2 とが、プリント配線板Ｐの端部に互いに対
向しないように接合されているものである。なお、前記
リードＬ1 、Ｌ2 を有するリードフレームは、前述した
リードフレーム（図１（ａ）〜（ｂ）参照）を使用する
ことができる。In the semiconductor device substrate of the first invention, the lead L having the half-etched portion 2 formed on only one of the front and back surfaces of the lead end portion 3 facing each other.
1 and the lead L2 having the half-etched portion 2 formed only on the other surface are joined to the end portion of the printed wiring board P so as not to face each other. As the lead frame having the leads L1 and L2, the lead frame described above (see FIGS. 1A and 1B) can be used.

【００２２】一方のリードＬ1 のリード端部３における
ハーフエッチング部２は、前記プリント配線板Ｐの端部
表面の導電端子部などの接合部に溶融ハンダ（端子部上
にバンピングしたハンダ）にて接合され、また、他方の
リードＬ2 のリード端部３における前記ハーフエッチン
グ部２は、前記プリント配線板Ｐの端部裏面の導電端子
部などの接合部に溶融ハンダ（端子部上にバンピングし
たハンダ）にて接合されている。The half-etched portion 2 at the lead end portion 3 of the one lead L1 is melted (solder bumped on the terminal portion) to a joint portion such as a conductive terminal portion on the end surface of the printed wiring board P. The half-etched portion 2 at the lead end portion 3 of the other lead L2 is melted to a joint portion such as a conductive terminal portion on the rear surface of the end portion of the printed wiring board P (solder bumped on the terminal portion). ) Are joined together.

【００２３】前記両方のリードＬ1 、Ｌ2 のそれぞれリ
ード端部３、３は、互いに対向しないプリント配線板の
表面と裏面に配置され、例えば、図３（ａ）に示すよう
にプリント配線板Ｐの対向する両端部のうちの一端部の
表面と他端部の裏面のそれぞれ接合部に、両リードＬ1
、Ｌ2 の前記ハーフエッチング部２の切欠面側が互い
に対向するようにして接合されている構成体である。The lead ends 3 and 3 of the both leads L1 and L2 are arranged on the front surface and the back surface of the printed wiring board which do not face each other. For example, as shown in FIG. The leads L1 are attached to the joints on the front surface of one end and the back surface of the other end of the opposite ends.
, L2, the half-etched portions 2 of the half-etched portion 2 are joined so that their cutout surfaces face each other.

【００２４】次に、第２の発明の半導体装置用基板を、
実施の形態に従って以下に詳細に説明する。Next, the semiconductor device substrate of the second invention is
A detailed description will be given below according to the embodiment.

【００２５】図４（ａ）は、第２の発明の半導体装置用
基板の全体平面図、図４（ｂ）は、そのＡ−Ａ側断面図
である。FIG. 4 (a) is an overall plan view of the semiconductor device substrate of the second invention, and FIG. 4 (b) is an AA side sectional view thereof.

【００２６】第２の発明の半導体装置用基板は、図３
（ａ）〜（ｂ）に示した第３の発明と同様にリード端部
３における互いに相対する表裏面のいずれか一方面にの
みハーフエッチング部２が形成されているリードＬ1
と、他方面にのみハーフエッチング部２が形成されてい
るリードＬ2 とが、プリント配線板Ｐの端部に接合され
ているものである。なお、前記リードＬ1 、Ｌ2 を有す
るリードフレームは、前述のリードフレームＬ（図１
（ａ）〜（ｂ）参照）を２枚用意して、それを使用する
ことができる。The semiconductor device substrate of the second invention is shown in FIG.
Lead L1 in which half-etched portion 2 is formed on only one of the front and back surfaces of lead end portion 3 facing each other as in the third invention shown in FIGS.
And the lead L2 having the half-etched portion 2 formed only on the other surface are joined to the end portion of the printed wiring board P. The lead frame having the leads L1 and L2 is the lead frame L (see FIG.
Two sheets (see (a) and (b)) can be prepared and used.

【００２７】一方のリードＬ1 のリード端部３における
ハーフエッチング部２は、前記プリント配線板Ｐの端部
表面の導電端子部などの接合部に溶融ハンダ（端子部上
にバンピングしたハンダ）にて接合され、また、他方の
リードＬ2 のリード端部３における前記ハーフエッチン
グ部２は、前記プリント配線板Ｐの端部裏面の導電端子
部などの接合部に溶融ハンダ（端子部上にバンピングし
たハンダ）にて接合されている。The half-etched portion 2 at the lead end portion 3 of the one lead L1 is melted by soldering (solder bumped on the terminal portion) to a joint portion such as a conductive terminal portion on the end surface of the printed wiring board P. The half-etched portion 2 at the lead end portion 3 of the other lead L2 is melted to a joint portion such as a conductive terminal portion on the rear surface of the end portion of the printed wiring board P (solder bumped on the terminal portion). ) Are joined together.

【００２８】前記両方のリードＬ1 、Ｌ2 のそれぞれリ
ード端部３、３は、互いに対向するプリント配線板の表
面と裏面に、両リードの前記ハーフエッチング部２の切
欠面側を互いに対向させて配置され、例えば、図４
（ａ）に示すように、前記一方のリードＬ1 のリード端
部３、３間に、他方のリードＬ2 のリード端部３を配置
して、両リードＬ1 、Ｌ2 のそれぞれリード端部３、３
は、プリント配線板Ｐの同一端部の互いに対向する表面
と裏面のそれぞれ接合部に接合されている半導体装置用
基板である。The lead ends 3 and 3 of the both leads L1 and L2 are arranged on the front and back surfaces of the printed wiring board facing each other, with the notched surface sides of the half-etched portions 2 of both leads facing each other. For example, FIG.
As shown in (a), the lead end 3 of the other lead L2 is arranged between the lead end portions 3 and 3 of the one lead L1 so that the lead end portions 3 and 3 of the both leads L1 and L2 are respectively disposed.
Is a substrate for a semiconductor device, which is bonded to a bonding portion of each of a front surface and a back surface of the same end portion of the printed wiring board P facing each other.

【００２９】次に、第３の発明の半導体装置用基板を、
実施の形態に従って以下に詳細に説明する。Next, the semiconductor device substrate of the third invention is
A detailed description will be given below according to the embodiment.

【００３０】図５（ａ）は、第３の発明の半導体装置用
基板の全体平面図、図５（ｂ）は、そのＡ−Ａ側断面図
である。FIG. 5 (a) is an overall plan view of the semiconductor device substrate of the third invention, and FIG. 5 (b) is a sectional view taken along line AA of FIG.

【００３１】図５（ａ）に示す第３の発明の半導体装置
用基板は、リード端部３における互いに相対する表裏面
のいずれか一方面にのみハーフエッチング部２が形成さ
れている一方のリードＬ1 が、プリント配線板Ｐの端部
に接合され、また、該リードＬ1 のリード端部３よりも
短いリード端部３を備えた他方のリードＬ2 が、プリン
ト配線板Ｐの端部の接合部にワイヤーボンディングによ
り通電可能に接続されているものである。The semiconductor device substrate of the third invention shown in FIG. 5 (a) has one lead in which the half-etched portion 2 is formed only on one of the front and back surfaces of the lead end portion 3 which face each other. L1 is joined to the end of the printed wiring board P, and the other lead L2 having a lead end 3 shorter than the lead end 3 of the lead L1 is joined to the end of the printed wiring board P. It is electrically connected by wire bonding.

【００３２】なお、第３の発明の半導体装置用基板の前
記リードＬ1 、Ｌ2 としては、前述のハーフエッチング
部２を備えた長リード端部３ａと、該長リード端部３ａ
より短い短リード端部３ｂとを一体的に有する前記リー
ドフレームＬ（図２（ａ）〜（ｂ）参照）を使用するこ
とができる。As the leads L1 and L2 of the semiconductor device substrate of the third invention, a long lead end 3a provided with the above-mentioned half-etched portion 2 and the long lead end 3a.
The lead frame L (see FIGS. 2 (a) and 2 (b)) integrally having the shorter short lead end portion 3b can be used.

【００３３】また、上記第３の発明の半導体装置用基板
は、その他に、前述の一方面にのみハーフエッチング部
２を備えたリード端部３を有する第１、第２の発明に用
いるリードフレームＬ（図１（ａ）〜（ｂ）参照）を一
方のリードＬ1 、該リード端部３より短いリード端部３
のみを備えたリードを他方のリードＬ2 として、それぞ
れ別体の該リードＬ1 とリードＬ2 を使用するようにし
てもよい。The semiconductor device substrate according to the third aspect of the present invention further has lead frames 3 for use in the first and second aspects, each having a lead end portion 3 having a half-etched portion 2 on only one surface thereof. L (see FIGS. 1 (a) and 1 (b)) is one lead L1 and a lead end 3 shorter than the lead end 3.
It is also possible to use the lead provided with only as the other lead L2 and use the leads L1 and L2 which are separate bodies.

【００３４】図５（ｂ）は、図５（ａ）に示す第３の発
明の半導体装置用基板のＡ−Ａ側断面図であり、一方リ
ードＬ1 における長リード端部３ａのハーフエッチング
部２は、前記プリント配線板Ｐの端部裏面（若しくは表
面）の導電端子部などの接合部に溶融ハンダ（端子部上
にバンピングしたハンダ）にて接合され、また他方リー
ドＬ2 における短リード端部３ｂは、前記プリント配線
板Ｐの端部表面（若しくは裏面）に配置されている導電
端子部Ｔなどの接合部に、図５（ｃ）に示すようにワイ
ヤーボンデングにより金線、銅線などのワイヤーｗにて
通電接続されている。FIG. 5B is a sectional view taken along the line AA of the semiconductor device substrate of the third invention shown in FIG. 5A, and the half-etched portion 2 of the long lead end portion 3a of the lead L1 is shown. Is joined to a joint portion such as a conductive terminal portion on the back surface (or front surface) of the end portion of the printed wiring board P by melted solder (solder bumped on the terminal portion), and on the other hand, the short lead end portion 3b of the lead L2. Is attached to a joint portion such as the conductive terminal portion T arranged on the front surface (or the rear surface) of the end portion of the printed wiring board P by wire bonding, such as a gold wire or a copper wire, as shown in FIG. 5C. It is electrically connected by a wire w.

【００３５】[0035]

【発明の効果】本発明の半導体装置用基板に用いるリー
ドフレームは、リードフレームの複数本乃至多数本のピ
ン状のリード端部に、その端部における表裏両面のいず
れか一方面にハーフエッチング部を設けたものであり、
該リード端部をプリント配線板の接合部に接合する際に
は、リード端部を屈曲加工せずに、該リード端部若しく
は該リード端部より一体に延設されているリードフレー
ムのフレーム面と、前記プリント配線板面とを、比較的
凹凸の少ない平坦な形状に且つコンパクトに接合させる
ことができる効果があり、特に、リードフレームと同程
度の薄さ、若しくはリードフレームの２倍乃至数倍程度
の薄さのフレキシブルタイプ乃至はリジットタイプのプ
リント配線板をはじめとする電気部品に対応した比較的
凹凸の少ない平坦な形状の半導体装置用基板の形成に効
果的である。The lead frame used for the semiconductor device substrate of the present invention has a plurality of or a plurality of pin-shaped lead end portions of the lead frame, and a half-etched portion on either one of the front and back surfaces at the end portion. Is provided,
When joining the lead end portion to the joint portion of the printed wiring board, the lead end portion or the frame surface of the lead frame integrally extended from the lead end portion without bending the lead end portion. And the surface of the printed wiring board can be joined compactly in a flat shape having relatively few irregularities and can be compactly bonded. In particular, the thickness is about the same as that of the lead frame, or twice to several times that of the lead frame. This is effective for forming a flat semiconductor device substrate with relatively few irregularities corresponding to electric components such as a flexible type or rigid type printed wiring board having a thickness about twice that of the present invention.

【００３６】また、リード端部の表裏両面のうちのいず
れか一方面に形成される前記ハーフエッチング部は、平
面的に切り欠かれているため、前記所定部品の接合面と
面接合されるため、接合が行い易く、また接合個所の接
合強度を強化できる効果がある。Further, since the half-etched portion formed on either one of the front and back surfaces of the lead end is notched in a plane, the half-etched portion is surface-bonded to the bonding surface of the predetermined component. In addition, there is an effect that the joining can be easily performed and the joining strength at the joining point can be strengthened.

【図面の簡単な説明】[Brief description of drawings]

【図１】（ａ）は第１、第２の発明に用いるリードフレ
ームの部分拡大平面図、（ｂ）はそのＡ−Ａ側断面図で
ある。FIG. 1A is a partially enlarged plan view of a lead frame used in the first and second inventions, and FIG. 1B is a sectional view taken along the line AA of FIG.

【図２】（ａ）は第３の発明に用いるリードフレームの
部分拡大平面図、（ｂ）はそのＡ−Ａ側断面図である。2A is a partially enlarged plan view of a lead frame used in the third invention, and FIG. 2B is a sectional view taken along the line AA of FIG.

【図３】（ａ）は第１の発明の半導体装置用基板の平面
図、（ｂ）はそのＡ−Ａ側断面図である。FIG. 3A is a plan view of a semiconductor device substrate of the first invention, and FIG. 3B is a sectional view taken along the line AA of FIG.

【図４】（ａ）は第２の発明の半導体装置用基板の平面
図、（ｂ）はそのＡ−Ａ側断面図である。FIG. 4A is a plan view of a semiconductor device substrate of the second invention, and FIG. 4B is a cross-sectional view taken along the line AA of FIG.

【図５】（ａ）は第３の発明の半導体装置用基板の平面
図、（ｂ）はそのＡ−Ａ側断面図、（ｃ）はその半導体
装置用基板の接合後における平面図である。5A is a plan view of a semiconductor device substrate according to a third aspect of the invention, FIG. 5B is a sectional view taken along line AA of FIG. 5, and FIG. 5C is a plan view of the semiconductor device substrate after bonding. .

【図６】従来のリードフレーム及びそのリードフレーム
を用いた半導体装置用基板を説明する側断面図である。FIG. 6 is a side sectional view illustrating a conventional lead frame and a semiconductor device substrate using the lead frame.

【符号の説明】[Explanation of symbols]

１…金属薄板材料 ２…ハーフエッチング部 ３…リー
ド端部 ３ａ…長リード端部 ３ｂ…短リード端部 Ｌ…リードフレーム Ｌ1 、Ｌ2 …リード Ｐ…プリン
ト配線板 Ｔ…導電端子部 ｗ…ワイヤー ｃ…屈曲部 ｔ…リードフレーム厚さ ｔ1 …ハーフエ
ッチング部の厚さ1 ... Metal thin plate material 2 ... Half etching part 3 ... Lead end part 3a ... Long lead end part 3b ... Short lead end part L ... Lead frame L1, L2 ... Lead P ... Printed wiring board T ... Conductive terminal part w ... Wire c … Bent part t… lead frame thickness t1… half-etched part thickness

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】リード端部における互いに相対する表裏面
のいずれか一方面にのみハーフエッチング部が形成され
ているリードと、他方面にのみハーフエッチング部が形
成されているリードとが、その一方のリードにおけるリ
ード端部の前記ハーフエッチング部と他方のリードにお
けるリード端部の前記ハーフエッチング部とをプリント
配線板の互いに対向しない表面と裏面に配置して、それ
ぞれ該プリント配線板の接合部に接合されていることを
特徴とする半導体装着用基板。1. A lead in which a half-etched portion is formed only on one of the front and back surfaces of a lead end portion facing each other, and a lead in which a half-etched portion is formed only on the other surface. The half-etched portion at the lead end of the lead and the half-etched portion at the lead end of the other lead are arranged on the front surface and the back surface of the printed wiring board which do not face each other, respectively, at the joint portion of the printed wiring board. A semiconductor mounting substrate characterized by being bonded. 【請求項２】リード端部における互いに相対する表裏面
のいずれか一方面にのみハーフエッチング部が形成され
ているリードと、他方面にのみハーフエッチング部が形
成されているリードとが、前記一方のリードにおけるリ
ード端部間に他方のリードにおけるリード端部を配置し
且つ両リードの前記ハーフエッチング部を互いに対向さ
せて、プリント配線板の互いに対向する表面と裏面の接
合部に接合されていることを特徴とする半導体装着用基
板。2. A lead in which a half-etched portion is formed only on one surface of the front and back surfaces facing each other at a lead end and a lead in which a half-etched portion is formed only on the other surface. The lead ends of the other lead are arranged between the lead ends of the other lead, and the half-etched portions of the both leads are opposed to each other and are joined to the joining portions of the front surface and the back surface of the printed wiring board which face each other. A semiconductor mounting substrate characterized by the above. 【請求項３】長リード端部と短リード端部とを備え、長
リード端部における互いに相対する表裏面のいずれか一
方面のみにハーフエッチング部が形成されているリード
が、プリント配線板の接合部に前記長リード端部のハー
フエッチング部にて接合され且つ該プリント配線板のそ
の他の接合部と前記短リード端部とを繋ぐワイヤボンデ
ィングにより導通接続されていることを特徴とする半導
体装着用基板。3. A lead having a long lead end portion and a short lead end portion, wherein a half-etched portion is formed on only one of the front and back surfaces of the long lead end portion facing each other is a printed wiring board. A semiconductor mounting characterized by being joined to a joining portion at a half-etched portion at the end of the long lead and being electrically connected by wire bonding connecting the other joining portion of the printed wiring board and the end of the short lead. Substrate.
JP25491495A 1995-10-02 1995-10-02 Substrate for semiconductor device Pending JPH0997867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25491495A JPH0997867A (en) 1995-10-02 1995-10-02 Substrate for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25491495A JPH0997867A (en) 1995-10-02 1995-10-02 Substrate for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0997867A true JPH0997867A (en) 1997-04-08

Family

ID=17271614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25491495A Pending JPH0997867A (en) 1995-10-02 1995-10-02 Substrate for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0997867A (en)

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