JPH0397049A - Storage device - Google Patents

Abstract

PURPOSE:To set an address even when memory packages are discontinuously loaded by providing a leading address set information generating circuit to generate the leading address information of the self-memory package when the leading address set information to be sent from the loaded package can not be obtained. CONSTITUTION:A package address setting circuit 1, adjacent package leading address set information generating circuit 2, leading address set information generating circuit 3 and selection output means 4 are provided and when the memory packages are continuously loaded, the address of the memory package is set by using leading address set information dx sent from the memory package loaded in the preceding step. When the memory packages are discontinuously loaded, the address of the memory package can be set by using information dx', which are generated by the leading address set information generating circuit 3, as the leading address set information. Thus, even when the memory packages are discontinuously loaded, the leading address of an address area in the memory package can be set.

Description

[Detailed Description of the Invention] [Summary] Regarding a storage device that automatically assigns addresses to each memory package in a storage device that has a plurality of memory packages, the address setting of the memory packages is fixed even when the memory packages are installed discontinuously. With the aim of providing a storage device that can mount multiple memory packages and that automatically sets the address of the installed memory package, the system automatically sets the address of the installed memory package using the head address setting information dx sent from the buff cage installed in the previous stage. A circuit that sets an address area to be allocated to a package, and using the start address setting information dx, start address setting information dx+1 of a package mounted in the rear stage of the own package and the cage.
A circuit for generating start address setting information, which generates start address information dx' for its own memory package when the start address setting information sent from the pancase installed in the front stage cannot be obtained, and a memory package installed in the front stage. The system is designed to be equipped with at least one memory package. [Industrial Field of Application] The present invention relates to a storage device that automatically allocates addresses to each memory package in a storage device that includes a plurality of memory packages with various capacities.

In recent years, the storage capacity of storage devices in information processing devices has been increasing. With this demand for increased memory capacity, the number of memory packages mounted on the shelf is also increasing. For this reason, even if a diagnostic program was run only by installing the necessary memory packages, the diagnostic program could not be executed unless all the memory packages were installed on the shelf because the memory space could not be allocated. Additionally, if all memory packages were to be produced from scratch, it would take time to install them all because of variations in the finish of each memory package. [Prior Art] FIG. 6 shows an information processing device. In the figure, 61 is a central processing unit (hereinafter abbreviated as CPU), 62 is an input/output device (
Hereinafter abbreviated as I/O>, 63 is a shelf consisting of memory package mounting positions A1 to A5. The storage capacity of the memory packages to be installed in each of the above mounting positions A1 to A5 is determined in advance, and memory packages M1 to M5 according to the respective installed storage capacities are installed in the mounting positions A1 to A5 in this order. shall be carried out. CPU
, the addressing signal AD from the I/O is used to call the memory area of the memory packages M1 to M5 mounted on the shelf through the bus. Below this, M
1 to M2 and the memory package installed in the previous stage, M2 to M
1 is called a later-mounted memory package, and memory packages M1 to M5 are installed at mounting positions AI to A5.
When all memory packages are installed, it is called continuous installation, and when there are memory packages that are not installed, it is called discontinuous installation. conventionally,
When memory packages are installed consecutively, JP-A-55-321
Address settings for each memory package were automatically performed using the method described in Publication No. 19. The conventional address allocation method will be briefly explained below. FIG. 7 is a diagram showing an outline of a conventional memory package. In the figure, CX1 is a pan cage address setting circuit,
Memory peripheral circuit 70 and memory drive? Road 72-1 to 7
-ADo to ADH consisting of 2-4 are address designation signal terminals on the board side, and address designation signals AD. Or A D z s enters from here.

The address designation signals ADO to ADzs select a memory unit using the upper 3 bits (ADzs to AD), and select the address within the memory unit specified by the remaining 23 lower bits (ADO to ADzz). This is to specify the following. D is start address setting information that sets the start address of each memory package. An address in the memory unit is selected by calculating the logic between the address designation signals AD0 to AD■ and the start address setting information D. 71 is memory, 71-1
71-4 are from the IMByte memory unit. 73 is a board, 74 is a connector attached to the board, and CX2 is an adjacent package start address setting information generation circuit, which sends out the start address of the package mounted in the subsequent stage. Figure 8 is a detailed diagram of the memory package. In the figure,
80-1 to 80-4 are selectors, 81-1 to 8
1?4 is 1? The first to fourth memory units of IByte, 82 and 83 are decoders, 84 is an adder circuit, 85-A to 85-H are AND circuits, 86 is an OR circuit, and A to H are select! 80-1 to 80
-4 is an input signal terminal, GA or GH is a selector 80-
1 to 80-4 gate signal terminals, T0 to T, are output signal terminals of decoder 82, d1' to d. Reference numeral 1 indicates a terminal for outputting start address setting information to the subsequent memory package, and d1 to d9 indicate terminals for inputting start address setting information from the preceding memory package. The output terminal T0 of the decoder 82 receives an address signal ADzx. A.D.
When za AD■ is ro O OJ, a logic "1" appears, and the address signal ADts. A
Dta. AD! ! Logic rlJ appears when 1 is ro 0 1J. The same applies below. Selector 80-1
80-4, respectively, are connected to the output terminal of the decoder 83, and the first address setting information input terminals d+, dt. r to d3+ d4
When 0 0 0 0J is supplied, the gate signal terminal GA
becomes logic "1", and the first address is set? Information input terminal d
I. dz. ds. When ro 1 1 1J is supplied to da, the gate signal terminal GH becomes logic rlJ.

The adder circuit 84 connects the start address setting information terminal d+. d
Add the top addresses on t, ds, and di and mounting information indicating how many units of memory are mounted on the memory package. This implementation information is available at IMByte
represents the number of memory units.

The result of this addition is the start address setting information output terminal d+'
, dz'. ds. It is sent from d◆' to the next memory package.

This will be explained below with reference to FIG. Now, the start address setting information @ D (d+. dt. dl d4) is r0
Assuming 0 0 0J, selectors 80-1 to 8
Logic "1" is supplied to the gate signal terminals GA of 0-4. Under this condition, the address signal A D *s. A
Dta. If A D■ is ro 0 0J, the logic of T0 is "1" and the logic of GA is rlJ, so the output of the AND circuit 85-A is rlJ, and the output of the RIO circuit 86 is "1". The first unit memory 81-1 is driven. Similarly, address signal A I)B. A
Dta. A Dzs? 001J, the second memory unit 81-2 is driven and the address signal A
D,■ADzn,AD! When S is r0 1 0J, the third memory unit 81-3 is driven and the address signal A
D t3. AD za-ADgs is rO 1 1J
Then, the fourth memory unit 8l-4 is driven. That is, when the head address setting information D of ro O O OJ is input to this memory package, the address area from the 0th address to the 4th MByte-1 address is allocated to the memory package. Furthermore, if the start address setting information "0100" is input to this memory package, the address area from the 4th MByte address to the 12th MByte-1 address will be allocated to the memory package. FIG. 9 shows the addressing signals A Do to AD! in the memory package of FIG. ? Increase to top 5
A storage device that uses bits (ADgs to ADzy) to select a memory unit and uses the remaining lower 23 bits (AD. to ADtz) to specify an address within the specified memory unit. In the diagram, 6D+ to D are the starting address setting information for the memory packages M1 to M3. Memory package M1
The storage capacity is 4MByte, and the memory package M
The storage capacity of M2 is 8 MB, and the storage capacity of M3 is 3 MB. The head address setting information is transmitted using the backboard of the shelf. Now, if the start address setting information DI input to the memory package M1 is r0 0 0 0J, the memory bar 7 cage M1 has the Oth address to the 4th MByt.
The address area of address e-1 is allocated. Since memory package M1 has a capacity of 4 units, the mounting information of memory package M1 is ro 1 0 0J. However, l:L27 is IMByte. The mounting information of r0 1 0 0J is memory package M
The adder circuit 94 of No. 1 adds the first address setting information D1 of ro O 0 0J to generate the addition result "0100J. This addition result ro t O Oj is the first address setting information for the memory package M2 mounted in the subsequent stage. D2
The data is input to the memory package M2 as . The start address setting information Dt input to the memory package M2 is r
o 1 0 0J and the capacity of memory package M2 is 8 MB, so the memory package M2
4th MByte address to 12th MByte address
Address te-1 is assigned. Memory package M2
Since the implementation information is "1000J" and the start address setting information D2 is r0 1 0 0J, the adder circuit 94 of the memory package M2 outputs rll00J.

This addition result rl 1 0 0J is input to the memory package M3 mounted in the subsequent stage as the head address setting information D. Since the head address setting information D, input to the memory package M3 is rl 1 0 0 J, and the storage capacity of the memory package M3 is 3 MByte, the 12th MByte is input to the memory package M3.
An address area from address e to 15th MByte-1 address is given.

As mentioned above, from the memory package installed in the previous stage,
Receive the start address setting information, set the start address of the own memory package, add the above start address setting information and the mounting information of the own memory package, and generate the start address setting information of the memory package installed in the subsequent stage. The address area of each memory package was set by sending it to the memory package installed in the subsequent stage.

[Problem to be solved by the invention]

Therefore, in the conventional method, the self-start address setting information is received from the memory package installed in the previous stage, so if the memory package is not installed consecutively (especially when running a diagnostic program), the start address setting information cannot be received and the start address of the address area of the memory package is There was a problem that the settings became impossible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device in which the start address of an address area of a memory package can be set even when memory packages are mounted discontinuously.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. In the figure, 1 is a package address setting circuit, which sets the address area to be allocated to the own package using the head address setting information dx sent from the previous stage mounted pancase; 2
is an adjacent buff cage start address setting information generation circuit, which uses the start address setting information dx to generate start address setting information dx+1 of the subsequent package;
3 is a start address setting information generation circuit, and when the start address setting information dx sent from the previous stage mounted package receives a signal indicating whether or not a memory package installed in the previous stage is installed, the first address of the first stage is set. The setting information generation circuit 3 outputs the start address setting Z-8 nine fixed information dx'. ゜ ゛ [Function] In the present invention, when memory packages are installed consecutively, the output is sent from the memory package installed in the previous stage. By using the start address setting information dx, the address of the memory package can be set. Further, when the memory packages are discontinuously mounted, the addresses of the memory packages can be set by using dx generated by the start address setting information generation circuit as the start address setting information.

〔Example〕

FIGS. 2 and 3 are diagrams showing the structure of an embodiment of the present invention. Second
The figure shows the case where memory packages are continuously mounted, and FIG. 3 shows the case where memory packages are discontinuously mounted. In the figure, 1
1.21.31 is a package address setting circuit,
Set the address of the own memory package. 12.22
．． Reference numeral 32 denotes an adjacent package start address setting information generation circuit, which sends out the start address of the subsequent package, and is composed of an adder circuit that adds the start address setting information and mounting information. Reference numeral 33 denotes a start address setting information generation circuit, and when the previous stage memory package is not installed, the output of the start address setting information generation circuit 33 is controlled by the control of the gate circuit G. The head address setting information generation circuit 33 is configured of, for example, a ROM, and generates in advance the same value D,' as the head address setting information that the own package receives from the previous package. The generated head address setting information D3' is connected via a gate circuit G to the input sides of a pan-package address setting circuit 31 and an adjacent package head address setting information generating circuit 32. A gate signal g for operating the gate circuit G is connected to a lifting resistor R and is dropped to earth E via a transmission line e via M2. Through this transmission line e, it is possible to know whether the previous stage package is installed or not. When the gate signal g is at the 'L (OV)' level, the gate circuit G is closed, and when the gate signal g is at the 'H (+5V)' level, the gate circuit G is opened.The memory package M1 has a storage capacity of 4MByte. M2 has a storage capacity of 8 MB, and memory buff cage M3 has a storage capacity of 3 MB.
The memory package Ml. M2
．． It is assumed that M3 sends the first address of the package address of the subsequent memory package as the first address setting information in this order. The head address setting information is transmitted using the Sheelf backboard. Hereinafter, address setting of a storage device using a memory package according to the invention will be explained.

Now, consider the case where three memory packages are installed in succession (see Figure 2). The memory package M1 has head address setting information D. When roo00J is received, the head address setting circuit 11 sets the address of the own package in the same manner as before (see FIG. 8), and sets the address of the memory package M1 from the O address to the 4th MByte-1.
The adjacent buff cage start address setting information generation circuit 12 adds the mounting information r0 1 0 0J of M1 and the start address setting information D1, and the addition result r
o 1 0 0J Send to memory package M2 as start address setting information Dt. In memory package M2,
Received head address setting information D. Similarly, using r0100J, the 4th MByte address to the 12th MByte
Set address te-1 as an address, and set own implementation information rl 0 0 0J and start address setting information n. r01
By adding 00J, the start address setting information D, rl
100J is generated and output to memory package M3.

Address setting information generation circuit 33 of memory package M3
Since the memory package M2 is mounted, the gate circuit G is dropped to the ground wire of the memory package M2, so the gate signal g becomes "L (OV)" level and is closed. Therefore, the memory package M3 receives the start address setting information D, "1" from the memory package M2.
100J, set the 12th MByte address to the 15th MByte-1 address as the address, and add the own implementation information ro O 1 1J and the start address setting information DsrllOOJ to set the start address setting information D4rllllJ. output to memory package M4. Next, if memory package M2 is not installed (
(See Figure 3). In this case, the memory package M1 sets the address of the self-package according to the procedure described above, and the first address setting information D! Output. The output head address setting information D2 is the memory package M2.
Address setting is interrupted at this point because there is no . Since the memory package M2 is not installed in the head address setting information generation circuit 33 of the memory package M3, the lifting resistor R is not dropped to the ground E but is lifted to 5V, so the gate signal g becomes the "H (+5V)" level. Gate circuit G opens. Therefore, D, rll00J generated by the address setting information generation circuit 33 is used as package address setting information to set the address of the own package. In addition, the above D3
The value of ' is sufficient as long as it is an address that allows the program to operate even without the preceding memory package, and the address setting information does not have to be ri i 0 0J as in the case of FIG. 2. An example of the mounting position of a memory package having a head address setting information generation circuit will be shown below.

FIG. 4 shows an example of mounting the present invention (when there is no adjacent mounting of a memory package necessary for executing a diagnostic program). The figure (a) shows when the diagnostic program is used, and the figure (b) shows when operating online. (a) As shown in the figure, at least diagnosis can be made if there is a memory package containing a diagnostic program. Therefore, you can run programs just by installing the necessary memory package. Further, as shown in FIG. 13(b), when used as a normal processing device, a memory package containing each processing program is installed. This shelf has 10 mounting positions Ae or AIO, and the ones with circles in the figure are the mounting positions of the necessary memory packages.
The pass mark indicates the reception of start address information from the start address setting information generation circuit, and the cross mark indicates the reception of start address information from the memory package installed in the previous stage. First, in figure (a), mounting positions A3. A6, A.I.
O, and the loading position AI. Use the backboard with A4 and AT to ground each E In Ex. E
It is listed in s. For this reason, the loading position AI or A
3. Loading position A4 to A6, loading position A7 to AI
O can also operate as a single system. In this case, it is sufficient to install memory packages M3, M6, and MIO each having an address setting information generation circuit.
As explained in Figure 3, you can set the memory package address. Next, in figure (b), a memory package Ml containing each processing program is installed in the uninstalled position in figure (a).
．． M2. M4. M.S. M? , M8, and M9 are installed consecutively, and the address setting of the memory bankage is performed as explained in FIG. 2.

FIG. 5 shows a mounting example of the present invention (when memory packages necessary for executing a diagnostic program are mounted adjacently). The figure (a) shows when the diagnostic program is used, and the figure (b) shows when operating online. First, in figure (a), the necessary adjacent mounting position A2. When there are A5, A6, AT, and A9, the mounting positions are AI, A3. Using the backboard on A8, drop each to the ground El l Ez l B,'. In this case, memory package M2. having an address setting information generation circuit. M5. If M9 is installed, memory package M6. Since M7 can receive the package address setting information, it is possible to set the address of the memory package as explained in FIG. Next, in figure (b), memory package Ml. M3, M4. M8. MIO
By installing the memory packages, all the memory packages are installed consecutively, and the addresses of the memory packages are set as explained in FIG.

〔Effect of the invention〕

As described above, according to the present invention, even when memory packages are discontinuously mounted, addresses can be set in the same way as when memory packages are sequentially mounted. Especially when diagnosing, since the required memory package is determined, you can simply install the required memory package and perform switching tests during system development even if other memory packages are not available. You can take bus assignment tests, etc.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the principle of the present invention. Fig. 2 is a diagram showing the structure of an embodiment of the present invention when memory packages are consecutively mounted. Fig. 3 is a diagram showing the structure of an embodiment of the present invention when memory packages are discontinuously mounted. When installed, Figure 4 shows an example of installing a memory package (when there is no adjacent memory package required to run the diagnostic program)
, Figure 5 is an example of mounting a memory package (when there is a memory package necessary for running a diagnostic program installed adjacently)
, FIG. 6 shows an information processing device, FIG. 7 shows an outline of a conventional memory package, FIG. 8 shows a detailed configuration of a conventional memory package, and FIG. 9 shows an example of address assignment of the memory package. In the figure, ■ = package address setting circuit, 2: adjacent package start address setting information generation circuit, 3: start address setting information generation circuit, 4: selection output means, dX, dx+L dx': package address setting information.

Claims (1)

[Claims] 1) In a storage device that can mount a plurality of memory packages and automatically sets the address of the mounted memory package, the self-package a circuit (1) for setting an address area to be allocated to a package; a circuit (2) for generating start address setting information dx+1 for a later-stage mounted package of its own package using the first address setting information dx; If the sent start address setting information cannot be obtained, the start address setting information generation circuit (3) generates the start address information dx' of its own memory package, and receives a signal indicating whether or not a memory package installed in the previous stage is installed. When the start address setting information generation circuit (3)
A storage device comprising at least one memory package equipped with a selection output means (4) for outputting information dx'. 2) The selection output means (4) consists of a gate circuit that is opened and closed by a gate signal that is applied from the ground of the backboard through the memory package mounted in the previous stage and through the transmission line connected to the lifting resistor of the own memory package. 2. The storage device according to claim 1).