JPH077372B2 - Address assignment device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address assigning device for assigning an address by a central control unit to each of a plurality of stages of peripheral devices connected to the central control unit via a bus.

[Prior Art] FIG. 4 is a block diagram showing a configuration of a conventional address allocation device. A plurality of peripheral devices 4 to 10 are connected to the central control unit 2 via a bus 12. The bus 12 is assumed to include not only an address bus and a data bus, but also all buses for transmitting other signals such as a decode signal and a control signal. In such a configuration, in order to individually control each of the peripheral devices 4 to 10 via the bus 12 from the central control device 2, the central control device 2 assigns an address to each of the peripheral devices 4 to 10. There must be. The addresses are assigned to the peripheral devices 4 to 10, for example, by the following method. That is, each of the peripheral devices 4 to 10 is provided with a DIP switch (DSW) 4a to 10a and a different value is set to each of them. Peripherals 4-10 compare the value set in DSWs 4a-10a with the address decode signal from central controller 2. Only when the set values of the DSWs 4a to 10a correspond to the address / decode signal, the central controller 2 can access the corresponding peripheral device.
That is, the address is assigned according to the set values of the DSWs 4a to 10a of the peripheral devices 4a to 10a.

[Problems to be Solved by the Invention] However, the conventional address allocation method described above has the following problems. That is, since the operator has to set the DIP switch one by one, the setting operation is complicated, and therefore, a setting error cannot be avoided.

In addition to the method described above, an address allocation method for peripheral devices has been proposed as follows. For example, it is a method using a multi-bus such as a VME bus, and is defined as a standard for each bus.
In such a method, addresses are automatically assigned to peripheral devices, so that the above-mentioned drawbacks are eliminated. However, in order to implement this method, the bus specified in the standard must be used. Moreover, in order for the central control unit to identify the peripheral device, complicated hardware must be provided for each peripheral device.

Therefore, one of the objects of the present invention is to provide an address assigning device capable of assigning an address from a central control device to a peripheral device without requiring manual operation such as setting a dip switch. Another object of the present invention is to provide an address allocating device in which the hardware required for the address allocating operation and its control procedure are simple.

Still another object of the present invention is to provide an address assigning device capable of confirming the addresses assigned by the central control unit to a plurality of peripheral devices, respectively. Another object of the present invention is to provide an address assigning device by which the central control unit can confirm whether a predetermined number of peripheral devices are properly connected.

[Means for Solving the Problem and Its Action] According to the address assigning device of the present invention, the central controller 14
It is possible to assign different addresses to a plurality of peripheral devices connected to each other and to confirm the assigned addresses. The central controller 14 outputs a write control signal and a data signal to the bus 13 to assign different data as addresses to the plurality of peripheral devices 16-22. Each of the plurality of peripheral devices 16 to 22 has the following configuration. That is, the storage unit 68 receives and stores the data of the address corresponding to the peripheral device via the bus 13. The comparing means 74 is supplied with a corresponding decode signal obtained by decoding the addresses assigned to the plurality of peripheral devices, compares the data with the data stored in the storing means 68, and outputs an enable signal when corresponding. As a result, the desired peripheral device is selected. The first buffer means 62 is enabled in response to the enable signal from the comparing means 74 and the bus 13
And connect the peripheral internal bus. As a result, data is supplied to each element in the selected peripheral device. The second buffer means 76 is enabled according to the enable signal from the comparison means 74, passes the data stored in the storage means 68, and sends the data to the internal bus. Since the internal bus is connected to the bus 13 by the first buffer means 62, the central control unit 14 can call the address assigned to its peripheral device and confirm the assigned address. This also allows the central controller to verify that a predetermined number of peripheral devices are properly connected.

[Embodiment] Next, an embodiment relating to the address assignment device of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the address assigning device of the present invention. This address assigning device comprises a plurality of stages of peripheral devices 1 connected to a central controller 14 via a bus 13.
An address is assigned to each of 6, 18, 20, 22 by the central controller 14. Bus 13 is for transmitting address signals, data signals, address decode signals, and other control signals. In this specification, “/” added before each signal name indicates that the signal is an active low signal. The central controller 14 has a write output terminal 30 and an enable output terminal 40. The central controller 14 has a write output terminal 30 and an enable output terminal.
The write signal / A and the write enable signal / E1 are output to 40, respectively. At the same time, a data signal representing an address assigned to each of the peripheral devices 16 to 22 is output to the bus 13.
Each of the peripheral devices 16 to 22 has the following terminals, respectively. That is, the write input terminals 32, 34, 36, 38 commonly connected to the write output terminal 30 of the central controller 14, the enable input terminals 42, 44, 46, 48, and the enable output terminals 50, 52, 54,
56. Further, the peripheral devices 16 to 22 have storage means 16a to 22a for storing the addresses assigned to the peripheral devices 16 to 22 by the central controller 14. The enable input terminal 42 of the first stage peripheral device 16 is connected to the enable output terminal 40 of the central controller 14. In addition, peripheral devices from the next stage onward
The enable input terminals 44, 46, 48 of 18, 20, 22 are respectively connected to the enable output terminals 50, 52, 54 of the peripheral devices in the preceding stage.

Next, the operation of the address assigning device thus configured will be described.

First, the peripheral device 16 writes the write input terminal 32 during the valid period of the write enable signal / E1 from the enable input terminal 42.
When the write signal / A from the central control unit 14 is received, the data signal output from the central controller 14 via the bus 13 is written in the storage means 16a. The content of this data signal becomes the address of the peripheral device 16. Further, the peripheral device 16 passes the write enable signal / E1 from the enable input terminal 42 to the enable output terminal 50 while writing the address. The passed signal is set as the write enable signal / E2. The write enable signal / E2 is given to the enable input terminal 44 of the peripheral device 18 at the next stage. Next, the peripheral device 18 performs the write operation similar to that described above. That is, when the peripheral device 18 receives the write signal / A from the write input terminal 34 during the valid period of the write enable signal / E2 from the enable input terminal 44, it is output from the central controller 14 via the bus 13. The data signal is written in the storage means 18a. The content of this data signal becomes the address of the peripheral device 18. In addition, peripheral devices
18 passes the write enable signal / E2 from the enable input terminal 44 to the enable output terminal 52 while writing the address. The passed signal is set as the write enable signal / E3. The write enable signal / E3 is given to the enable input terminal 46 of the peripheral device 20 at the next stage. Less than,
By performing the same address allocation operation, enable signals / E4 and / E5 are output from the peripheral devices 20 and 22, respectively, and addresses are sequentially allocated to the peripheral device 22.

Next, the operations of the central controller 14 and the peripheral devices 16 to 22 will be described in detail with reference to the circuit diagram shown in FIG. 2 and the corresponding time chart in FIG.

FIG. 2 is a circuit diagram showing a part of a peripheral device according to an embodiment of the present invention. Note that, in FIG. 2, parts corresponding to those in FIG. 1 are denoted by the same reference numerals. Each of the plurality of peripheral devices is provided with substantially the same circuit as the circuit shown in FIG. 2. However, for simplicity, the peripheral device 16 will be described as an example here. Buffer 60 is a write enable signal
When / E1 is valid, it is enabled and gives a write signal / A to AND gate 66. Sending and receiving signals between the bus 13 and the data bus BD inside the peripheral device 16 are performed by a bus buffer.
Through 62. The bus buffer 62 is enabled when the output signal from the output terminal Q of the multiplexer 74, which will be described later, becomes valid, and data can be transmitted and received.
Data of 4 bits of the data on the bus 13 is input to the buffer 64. When the buffer 64 is enabled by the write enable signal / E1, the 4-bit data passing through the buffer 64 is transferred to the input terminals D1 to D1 of the register 68.
Given to D4. These data are from AND GATE 66
At the rising edge of the write signal / A that has passed through, the data is taken into the 4-bit register 68 and output to its output terminals Q1 to Q4 in active low. This register 68
Corresponds to the storage means 16a in FIG. The address of the peripheral device 16 is stored in the register 68 as 3-bit data. Remaining 1 written to register 68
The bit data is used as a write completion signal indicating whether or not an address is written in the register 68. The write completion signal will be described later. The 4-bit data output from the register 68 is stored in the buffer 76.
And is output to the data bus BD in the peripheral device 16. Also, each of the 3-bit address data output from the register 68 is a control input terminal of the multiplexer 74.
Given to C0-C2. The central processing circuit 14 supplies four decode signals DS1 to DS4 obtained by decoding addresses corresponding to a plurality of peripheral devices to the multiplexer 74 via the bus 13. The multiplexer 74 compares the address data and the decode signal, and selectively enables (“L”) the output terminal Q when the decode signal corresponding to the address data exists. The output of the output terminal Q functions as an enable signal as described later. Decode signal DS
1 to DS4 can be obtained by the central arithmetic circuit 14 decoding the most significant 2 bits of the selected address, in the case where the memory space is divided into four equal parts according to the number of peripheral devices. For example, when the most significant 2 bits of the selected address are "00", the central processing circuit 14 enables DS1 to "L", and when "01", enables DS2 to "L". When the signal output to the output terminal Q becomes valid (“L”), it means that the peripheral device 16 is selected from the central controller 14. By the signal output from the output terminal Q of the multiplexer 74,
The above-mentioned bus buffer 62 is enabled. Therefore,
Data is exchanged between the data bus BD inside the peripheral device 16 and the bus 13, that is, the peripheral device 16 is selected. Decoder 78, which is enabled by the output signal of multiplexer 74, receives from central controller 14 an address signal provided via bus 13 and address bus BA in peripheral device 16. In the example in which the memory is divided into four, this address signal corresponds to bits lower than the most significant 2 bits of the selected address. The decoder 78 decodes the received address signal to generate a peripheral device.
It outputs an enable signal for enabling each element in 16 such as a buffer, a memory, and other elements, and outputs other control signals. That is, an address is assigned to each of the elements in the peripheral device.
Like the data bus BD in the peripheral device 16, the address bus BA in the peripheral device 16 is connected to the bus 13 via a bus buffer (not shown). Since these bus buffers are 3-state buffers, they require control signals in addition to enable signals. However, in this embodiment, the control signals are omitted because they are not related in operation.

Next, the circuit operation of FIG. 2 will be described with reference to the time chart of FIG.

First, the central controller 14 makes the write enable signal / E1 to the enable input terminal 42 valid (“L”) (third).
(A). As a result, the buffer 60 and the buffer 64 are enabled, and one of the input terminals of the AND gate 72 becomes "L". Next, a data signal indicating an address assigned to the peripheral device 16 is output to the bus 13. Therefore,
The data signal passes through buffer 64 to register 68.
Given to the input terminal of. After the address signal is confirmed (Fig. 3 (C)), the central controller 14 writes the write signal / A.
Is output (FIG. 3 (B)). The write signal / A passes through the enabled buffer 60 and the AND gate 66 and is applied to the clock input terminal of the register 68. As a result, at the rising edge of the write signal / A, the register
The data applied to the input terminals D1 to D4 of 68 is written in the register 68. Note that the register 68 is reset by the initial setting performed before this write operation,
The output terminals Q1 to Q4 of the register 68 are all in the "H" state in advance. Therefore, by the write operation, the data signal indicating the address as described above is output to the data input terminals D1 to D3 of the register 68. In addition,
In order to output the write completion signal / B indicating that the write operation is completed from the output terminal Q4 of the register 68, the data input terminal D4 is supplied with the signal of "H". Therefore,
Before and after the write operation, the state of the output terminal Q4 of the register 68 changes from "H" to "L". That is, if the state of the write completion signal / B is "H", it indicates before writing,
If it is "L", it indicates after writing. The write completion signal / B reaches the input terminal of the AND gate 72. Therefore, the output signal of the AND gate 72, that is, the write enable signal / E2 becomes valid ("L") at the same time as the write completion signal / B becomes valid ("L") (FIG. 3 (D)). ). The write enable signal / E2 passes through the enable output terminal 50 and is given to the enable input terminal 44 of the peripheral device 18 at the next stage. Also, the above write completion signal
/ B reaches the AND gate 66 via the inverter 70.
That is, when the write completion signal / B becomes valid ("L"), the AND gate 66 is closed, and thereafter, the passage of the write signal / A input via the buffer 60 is prohibited. Therefore, rewriting to the register 68 is prohibited.

As a result of such an operation, an address is assigned to the peripheral device 16. Further, the same operation as described above is sequentially performed by the peripheral devices 18, 20, 22. As a result, FIG.
As shown in (F) and (G), write enable signal / E
3, / E4, / E5 are enable output terminals 5 of peripheral devices 18,20,22
It is output from 2,54,56. Since these operations are repeated, the description thereof will be omitted.

By performing the address allocation operation as described above,
Each of the peripheral devices 16-22 can be assigned on the address map as seen by the central controller 14. Therefore, the address decode signal DS corresponding to the assigned address is sent from the central control unit 14 to the peripheral devices 16 to 22 via the bus 13.
By giving 1 to DS4, a desired peripheral device can be selected and the selected peripheral device can be individually controlled.

In addition, whether the address allocation operation described above was performed correctly,
To check whether or not it is possible to do as follows. That is,
In FIG. 1, the central control unit 14 to the peripheral devices 16 to 22
The address assigned to the storage means of each peripheral device 16-22
By confirming that the address is stored in 16a to 22a, it can be confirmed whether or not the address allocation operation is performed correctly. This will be described with reference to FIG. That is, the address decode signals DS1 to D corresponding to the address of the peripheral device to be selected.
The S4 is supplied to the multiplexer 74. Address supplied
If the address corresponding to the decoded signal is stored in the peripheral device 16, the peripheral device 16 is selected, for example. As a result, the output signal of the output terminal Q of the multiplexer 74 is
It becomes “L” and the decoder 78 is enabled. The address assigned to each element (for example, the buffer 76) in the selected peripheral device is input to the decoder 78 via the bus 13 and the internal address bus BA. Therefore, when the decode 78 is enabled, the address corresponding to the buffer 76 is decoded by the decoder 78, and the enable signal is supplied to the buffer 76 from the output terminal Q1. Of course, the other output terminal Qx supplies the decode signal to other elements in the peripheral device. As a result, the data stored in the register 68, that is, the assignment and address to the peripheral device 16, are sequentially transferred to the buffer 76, the data bus BD in the peripheral device 16,
And is output to the bus 13 via the bus buffer 62.
As a result, the central controller 14 can read the address assigned to the peripheral device 16. If the address corresponding to the address decode signal supplied to the multiplexer 74 is not stored in the peripheral device 16, the signal for enabling the buffer 76 is not generated, and the buffer 76 is, for example, FF.
・ It is in a state where a meaningless value such as F is output. In this way, by comparing the address read from the peripheral device 16 with the address initially assigned to the peripheral device 16, it is possible to confirm whether or not the address assignment operation has been performed accurately. Therefore, the address allocation operation can be confirmed by sequentially performing the same operation for each peripheral device 18 to 22. The decoder 78 has a plurality of elements such as a buffer and a memory in the peripheral device, and is provided to decode the addresses assigned to these elements. Therefore, the enable signal from the output terminal Q of the multiplexer 74 may be directly supplied to the buffer 76 only for confirming the address assigned to each peripheral device, and the decoder 78 is not always necessary.

As described above, by confirming the address assignment, it is easy to count how many peripheral devices have read the address. By utilizing this, the following advantages occur. That is, in the case of FIG.
Consider, for example, the case where the peripheral device 20 is not connected among the four peripheral devices 16 to 22. In this case, the write enable signal reaches the peripheral device 18. However, since the enable input terminal 46 and the enable output terminal 54 which should exist in the next stage do not exist, the write enable signal is not input to the peripheral device 22. As a result, no address is assigned to the peripheral device 22. Next, when the above-mentioned address allocation is confirmed, the addresses up to the peripheral device 18 can be read, but the addresses in the subsequent stages cannot be read.
Therefore, it is recognized by the central control unit 14 that the address is assigned only to the two peripheral devices 16 and 18. Therefore, in the central controller 14, if the number of peripheral devices to be connected is compared with the number of address-assigned peripheral devices, a predetermined number of peripheral devices are correctly connected. There is an advantage that it can be judged in a positive manner.

As described above, according to the address assigning device of the present invention, the addresses are sequentially written into the respective storage means 16a to 22a of the peripheral devices 16 to 22 connected to the central control unit 14 via the bus. Be done. Therefore, it is possible to perform address assignment from the central control device to the peripheral device without requiring manual operation such as setting a dip switch. Therefore, unlike the prior art, the complicated setting operation of the DIP switch is not required. Further, there is an advantage that a malfunction due to a setting error of the DIP switch can be prevented.

Further, the hardware necessary for realizing these address allocation operations can be realized by a simple configuration as shown in the circuit diagram of FIG. The control procedure of the hardware is simple, as shown in the time chart of FIG.

In the embodiment shown in FIG. 2, the register 68 having a 4-bit structure is used. 3 out of 4 bits are
Used to store addresses assigned to peripheral devices. The reason for this will be described. 4 if there are 2 bits
Since the addresses of various types can be expressed, the addresses assigned to the four peripheral devices 16 to 22 should be able to be stored. However, it is necessary to separately indicate the state where the register 68 is reset by the initial setting. Therefore, the register
The number of bits used in 68 is increased by 1 and 3 bits are used for address storage.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described herein,
It will be apparent to those skilled in the art that various modifications and changes can be made as necessary without departing from the spirit of the present invention.

EFFECTS OF THE INVENTION As described above, according to the address assigning device of the present invention, different addresses can be assigned from the central control device to a plurality of peripheral devices connected to the central control device. You can check the address. That is, when the decode signal corresponding to the address allotted to each peripheral device is supplied to each comparing means, if the address corresponding to the supplied decode signal is not allocated, the value different from the correct address is in the center. Sent to the controller. Therefore, by sequentially changing the decode signal commonly supplied to the comparing means of the plurality of peripheral devices, it is possible to check the presence or absence of the peripheral device to which the expected address is assigned.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an address assigning device of the present invention, FIG. 2 is a circuit diagram showing a part of a peripheral device in one embodiment of the present invention, and FIG. 3 is an address in the same embodiment. FIG. 4 is a block diagram showing a configuration of a conventional address assigning device, which is a time chart corresponding to the assigning operation. 13: Bus 14: Central controller 16-22: Peripheral device 62: First buffer means 68: Storage means 74: Multiplexer 76: Second buffer means BD: Internal bus (data bus) of peripheral device BA: Peripheral device Internal bus (address bus)

Claims (1)

[Claims] 1. A central control unit that outputs a write control signal and a data signal to a bus, and the different data that are connected to the central control unit via the bus and sequentially respond to the write control signal to different data. Is an address assigning device having a plurality of peripheral devices assigned as addresses, each of the plurality of peripheral devices being supplied with storage means for storing the data from the bus and a decode signal corresponding to the address. Comparing means for comparing the data stored in the storing means with each other and outputting an enable signal when corresponding to the data, and first enabling the bus and the internal bus of the peripheral device, which are enabled according to the enable signal. The buffer means and the data stored in the storage means, which is enabled in response to the enable signal, are passed through. Second addressing means for sending to the internal bus.