JPH0394514A - Polyphase synchronizing signal generator - Google Patents

Abstract

PURPOSE:To attain delicate control by arranging delay elements endlessly in multi-stage in a loop, and selecting the number of delay elements in the loop so as to prolong the period of a clock signal. CONSTITUTION:The title generator consists of a ring circuit A in which D flip-flops 5 (D.FF 1-6) being delay elements are arranged in multi-stage endlessly in a loop. When a clock delay designation signal S is inputted to an input terminal S of a selector 6 at a desired period, an input terminal 2a is closed and an input terminal 1a is opened, then clock signals S1-S4 detours the D flip-flops 5 (D.FF 5-6) for prolonging the ring circuit A, and circulates in a loop via the input terminal 1a of the selector 6 through an inverter 7, and return to the standard D flip-flops 5 (D.FF 1-4). Thus, the loop of the ring circuit A by the flip-flop 5 is changed to 4-stage and 6-stage, resulting in the 4-phase synchronizing signal being retarded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to generating polyphase synchronization signals used in advanced logic circuit systems that finely control operation timing. The present invention relates to a multiphase synchronization signal generation device related to a so-called clock generation circuit that varies the phase of the clock.

[Prior Art] Timing design in conventional complex and advanced logic circuit systems is based on the theory of configuring circuits! ! ! Since the operating time differs depending on the scale of the element, a multiphase synchronization signal is generally used as the system clock signal. As shown in Figure 3, by using an N-phase multiphase synchronization signal with one period of the clock signals @Sa to Sn as T, the rising and falling edges of 2N clocks can be used as timing standards, and the time The resolution becomes T/2N. As a result, fine timing settings 31 can be made, so it is widely used, especially in logic circuit systems that require high-speed processing.

Furthermore, if the operation of the logic circuit differs depending on the input signal,
For example, when input signals are added or multiplied, the operating time of the circuit may vary greatly depending on the designation of the circuit's operation. In such a case, the clock signal Sa
- It is necessary to extend one round 1111T of Sn.

[Problem to be solved by the invention] An example of a conventionally used circuit is shown in FIG.

This is an example of a four-phase synchronous signal. 1 in the figure is a 3-bit counter,
2 is a counter initial I1llIti setting circuit, 3 is a decoder, and 4 is a D flip-flop that changes at the rising edge of a clock signal 3a-Sn for removing hazards from the output signal of the decoder. By changing the initial value by the initial value setting circuit 2 of the counter 1 and the operation of the decoder 3, the periods of the clock signals Sa to Sn are changed. S is a clock delay designation signal.

In such a circuit, it is necessary to specify whether to extend or not at the rising edge of the first phase clock signal Sa, and it is not possible to precisely determine υ11[l. Another drawback is that the circuit design becomes larger.

In this respect, it is an object of the present invention to provide a multiphase synchronization signal generation system that is effective and suitable for solving the above-mentioned conventional drawbacks.

[Means for Solving the Problems] The above problems can be solved by the multiphase synchronization signal generation device of the present invention,
In a device that generates a multiphase synchronization signal by circulating a clock signal through a ring circuit in which a plurality of standard delay elements and at least one extension delay element are arranged in multiple stages in a ring shape, the final stage of the standard delay element group Whether the output signal is directly fed back to the first stage of the standard delay element group without passing through the extension delay element, or is fed back to the first stage of the standard delay element group after passing through the extension delay element. This is achieved by employing the above configuration means in which the phase of the multiphase synchronization signal is varied by having a selection means for selectively switching to one of the loop formations.

[Function] The present invention takes the above-mentioned means, arranges delay elements in a loop in a multi-stage endless connection, circulates a clock signal to generate a multiphase synchronization signal, and selects the number of delay elements in the loop. Extend the period of clock {i. It is only necessary to decide whether or not to extend the clock signal by the time the clock signal arrives at the input terminal of the delay element for extension, and the insertion position of the delay element for extension can also be set arbitrarily, allowing fine-grained control. The circuit scale is also small.

[Example] An embodiment of the invention will be described with reference to FIG.

This figure is a block circuit diagram of this embodiment, and is an example of four-phase identical signals. In the figure, A is a D-type flip-flop 5 ([). A ring circuit in which FFs 1 to 6) are connected in a loop in multiple stages, 6 is a selector, and 7 is an inverter for inverting clock signals S1 to Sn.

The operation of this embodiment is as follows: First, a reference clock signal SO and an initialization signal S1 are input to all flip-flops 5 (D.FF1 to FF6) constituting the ring circuit A to input terminals D and CLK.
If a common input is made to each, standard flip-flop 5
(D.FF1-4) to open input terminal 2 of selector 6
standard flip-flop 5 through inverter 7 through a
(Return to D.FF1~4> and clock signal (S1)~(
S4) is cycled.

If the clock delay designation signal S is input to the input terminal S of the selector 6 at a desired time, the input terminal 2a is closed and the input terminal 1 is closed.
a is opened, the clock signals S1 to S4 bypass the extension flip-flops 5 (D.FF5 to 6) of the ring circuit 8, and pass through the input terminal 1a of the selector 6 to the inverter 7.
A loop is circulated through the standard flip-flop 5 (D.FFI~4).

In addition, even when shortening the period $11JT of the clock signals S1 to S4, if the clock delay designation signal S is input again to the input terminal S of the selector 6, the input terminals 1a and 2a are switched, and the extension flip-flop 5 (D.FF5-6> can be omitted).

By switching the selector 6 using the clock delay designation signal SS, the loop of the ring circuit A formed by the flip-flop 5 can be changed to four stages or six stages, and as a result, it becomes possible to delay the four-phase synchronous signal.

The operating waveforms are shown in the timing chart of FIG.

Further, the number of connection stages of the standard flip-flop and the extension flip-flop O-tube is arbitrary.

[Effects of the Invention] Thus, by using the multiphase synchronous signal generating device of the present invention, it is possible to easily generate a multiphase synchronous signal with a variable phase at any time depending on the input timing of the selector input of the clock delay designation signal. It has a great effect.

[Brief explanation of drawings]

Figures 1 and 2 are block circuit diagrams showing an embodiment of the present invention and timing charts of its operating waveforms, Figure 3 is a timing chart of multiphase synchronizing signal waveforms, and Figure 4 is a block circuit diagram of a conventional device. It is. A... Ring circuit T... Period SO... Standard clock signal S'... Initialization signal @ S... Clock delay designation signal Sa, S1... First phase clock signal Sb, 82. ...Second phase clock signal Sc, 83...Third phase clock signal Sd, S4...Fourth phase clock signal SN...Nth phase clock signal 4.5...D type flip 7 lobes (D .1 to 6
〉 6...Selector 7...Inverter FF Fig. 1 Fig. 3 Fig. 4 Fig. 2

Claims (1)

[Claims] In a device that generates a multiphase synchronization signal by circulating a clock signal through a ring circuit in which a plurality of standard delay elements and at least one extension delay element are arranged in multiple stages in a ring shape, the final stage of the standard delay element group whether the output signal is directly fed back to the first stage of the standard delay element group without passing through the extension delay element, or is fed back to the first stage of the standard delay element group after passing through the extension delay element; A multiphase periodic signal generator characterized in that the phase of the multiphase synchronization signal is made variable by having a selection means for selectively switching to one of the loop formations.