JPH11195969A - Clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generator that controls two phase clock synchronously with a reference clock and its inverted clock so as to set an H level output hold period of the two phase clock to be an integer multiple of a basic pulse width. SOLUTION: The generator is provided with a frequency divider circuit 26 that applies 1/2 division to reference clock synchronously with the reference clock and its inverted clock so as to output two signals whose phases are deviated by a half period each other, a control circuit 27 that generates a signal used to control the two output signals of the frequency divider circuit to be both an H or an L level, and an exclusive OR circuit 24 that exclusively Ors the two outputs signals of the frequency divider circuit 26. An output state of the two phase clock produced by a clock generating circuit 11 changes synchronously with the reference clock and its inverted clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator capable of changing the output state of a multi-phase clock in synchronization with a reference clock and its inverted clock.

[0002]

2. Description of the Related Art FIG. 4 shows a circuit example of a conventional clock generator. In FIG. 4, reference numeral 3 denotes a NOR circuit for outputting the NOT of the logical sum of the reference clock 1 and the control signal 2, and reference numeral 11 denotes a clock generation circuit including an inverter circuit 5 and NAND circuits 6 and 7. The clock generation circuit 11 is NOR
An output signal 4 of the circuit 3 is input, and two-phase clocks T1, T2
(8 and 9). When the control signal 2 goes high, the output signal 4 of the NOR circuit 3 goes low regardless of the state of the reference clock 1. The output signal 4 is input to the clock generation circuit 11, is directly input to one input terminal of the NAND circuit 6, is inverted by the inverter circuit 5, and is input to one input terminal of the NAND circuit 7.
If one input of NAND circuit 6 is at L level, H level is output to two-phase clock T1 (8) regardless of the state of the other input. In this state, the control signal 2 is set to L
It is kept until it changes to the level. Therefore, during the H level output period of the control signal 2, the two-phase clock T1 is held at the H level.

[0003]

FIG. 5 shows the operation timing of a conventional clock generator. The H level period or the L level period of the reference clock 1 which alternately repeats the H level and the L level is defined as a basic pulse width 31. If an attempt is made to set the H-level output period of the two-phase clock T1 (8) to an even multiple of the basic pulse width in the conventional configuration, since it is not synchronized with the reference clock, it is smaller than the basic pulse width as shown at 30. A whisker-like pulse is generated. Therefore, when controlling the memory using the two-phase clock generated by the conventional clock generator, the two-phase clock T1
The H level output period of (8) must be set to an odd multiple of the basic pulse width 31, and it is difficult to finely control the memory access cycle.

The present invention has been made to solve the above problems, and controls two-phase clocks T1 and T2 in synchronization with a reference clock and a clock obtained by inverting the reference clock.
It is an object of the present invention to provide a clock generator capable of setting an H level output holding period of 1 to an integral multiple of a basic pulse width.

[0005]

A first configuration of a clock generator according to the present invention divides a frequency of a reference clock by half in synchronization with a reference clock and a clock obtained by inverting the reference clock, and has a half cycle phase with each other. A frequency dividing circuit that outputs two shifted signals, a control circuit that generates a signal that controls both the output signals of the frequency dividing circuit to H level or L level, and an exclusive operation of the two output signals of the frequency dividing circuit An exclusive-OR circuit for calculating a logical sum is provided, and the output state of the generated two-phase clock is changed in synchronization with the reference clock and the inverted clock thereof. According to this configuration, the output state of the two-phase clock can be changed in synchronization with the reference clock and the inverted clock, and the H-level output period of the two-phase clock T1 is set to an integral multiple of the basic pulse width. be able to. As a result, it is possible to obtain a clock generator for finely controlling a memory access cycle.

The second aspect of the clock generator according to the present invention
Is configured to divide the reference clock into quarters in synchronization with the reference clock and its inverted clock to correspond to a four-phase clock generator, and to shift the quarter-period phase by four from each other. Divider circuit that outputs the output signal, a delay circuit that delays the output signal of the preceding stage by a quarter period in synchronization with the reference clock and its inverted clock, and all the output signals of the divider circuit and the delay circuit. A control circuit for generating a signal to be controlled to an H level or an L level; an exclusive OR circuit for obtaining an exclusive OR of four output signals of the frequency divider circuit and four output signals of the delay circuit; A clock generation circuit comprising a decoder circuit which receives the four output signals of the sum circuit and controls the output of each of the first to fourth phase clocks; a reference clock; and a clock obtained by inverting the reference clock. When Synchronously, characterized in that changing the output state of the generation of four-phase clocking.

The third aspect of the clock generator according to the present invention
Is adapted to divide the frequency of the reference clock by 1 / N in synchronization with the reference clock and its inverted clock to correspond to the N-phase clock generator, and to shift the phase of the reference clock by 1 / N. A delay circuit for outputting a number of signals, a delay circuit for delaying an output signal of a preceding stage by one-Nth cycle in synchronization with the reference clock and a clock obtained by inverting the reference clock; A control circuit for generating a signal for controlling all the output signals to an H level or an L level; and an exclusive circuit for performing an exclusive OR operation of N output signals of the frequency divider circuit and N output signals of the delay circuit. An OR circuit; and a clock generation circuit configured with a decoder circuit that receives N output signals of the exclusive OR circuit as inputs and controls respective outputs of clocks from a first phase to an N-th phase. ,
In synchronization with the reference clock and its inverted clock,
The output state of the generated N-phase clock is changed.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a clock generator according to an embodiment of the present invention.
In FIG. 1, reference numeral 26 denotes a frequency divider which outputs a frequency-divided signal of a reference clock having a half-period phase shift in synchronization with the reference clock. A control circuit for determining the H-level output holding period of the two-phase clock T1;
Is an exclusive-OR circuit for calculating the exclusive-OR of the output signals.

(First Embodiment) FIG. 2 is a circuit diagram of a clock generator according to a first embodiment. In FIG. 2, reference numeral 23 denotes an inverter circuit that inverts the reference clock and generates a reference clock having a half-cycle phase shift. Reference numeral 26 denotes a frequency divider which outputs a frequency-divided signal of a reference clock whose phase is shifted by a half cycle. The flip-flop circuit 14 changes the output signal in synchronization with the reference clock 1, and a clock obtained by inverting the reference clock 1. And a flip-flop circuit 16 that changes an output signal in synchronization with the flip-flop circuit 15.
Reference numeral 27 denotes a control circuit for generating a signal for controlling the output signal of the frequency dividing circuit 26 to a fixed H level or a fixed L level.
It comprises an AND circuit 17, an AND circuit 19, and an OR circuit 18. 24 is an output signal 21 of the flip-flop circuit 14 and an output signal 22 of the flip-flop circuit 16
Is an exclusive-OR circuit having the inputs of Reference numeral 11 denotes a clock generation circuit to which an output signal 25 of the exclusive OR circuit 24 is input. In this way, by generating frequency-divided signals having a phase shift of a half cycle from each other, either of both sides of the period in which both the output signal 21 and the output signal 22 are at the H level or the L level is one reference pulse period H level During the period of the one reference pulse width, the exclusive OR circuit 24 outputs T
This is the H level output period of 2. In addition, during the period when the H level is input to the control signal 2 in order to set T1 to an integral multiple of the reference pulse width, both the output signal 21 and the output signal 22 are held at the H level or the L level. The logical OR circuit 24 enters the H level output holding period of T1.

The operation of the clock generator according to the first embodiment will be described with reference to the timing chart of FIG.
When the H level is input to the RST signal 12, this becomes one of the inputs of the OR circuit 18. Therefore, the H level is input to the R inputs 20 of the flip-flop circuits 14 and 16 only during the H level of the RST signal 12. Is done.
During this period, the operations of the flip-flop circuits 14 and 16 are reset, and the output signals 21 and 22 are output.
Output the L level.

A set input 13 of the flip-flop circuit 14 and the flip-flop circuit 16 has a control signal 21 and an output signal 21 of the flip-flop circuit 14 as inputs.
Since it is the output of the AND circuit 17, it is at the H level when either of the inputs is at the L level. Since the set signal 13 is low active, the RST signal 12 and the control signal 2
Are both at the L level, the flip-flop circuit 14 inverts the output signal at each rising edge of the reference clock 1 and outputs the reference clock 1 as a half as the output signal 21.
The divided signal is output. Flip-flop circuit 16
Inverts the output signal at each rising edge of clock 15 in which reference clock 1 is inverted by inverter circuit 23,
The output signal 22 includes a clock 1 obtained by inverting the reference clock 1
5, a signal obtained by dividing the frequency by 5 is output. Therefore, the output signal 21 of the flip-flop circuit 14 and the output signal 22 of the flip-flop circuit 16 are output with a shift of a half cycle. Only when both the output signals 21 and 22 are at H level or L level, the output signal 25 of the exclusive OR circuit 24 becomes H level.

The clock generation circuit 11 uses the output signal 25 of the exclusive OR circuit 24 as an input signal.
The output signals 2 of the exclusive OR circuit 24 are output by the circuits 6 and 7.
While 5 is at the H level, the H level is output to the eight two-phase clocks T1. If the control signal 2 is set to H level when the output signal 21 of the flip-flop circuit 14 and the output signal 22 of the flip-flop circuit 16 are both L level in order to change the H level period of the two-phase clock T1 (8), A
The H level is input to the R input 20 of the flip-flop circuit 14 and the flip-flop circuit 16 by the ND circuit 19 and the OR circuit 18, and the set input 13 is set to the H level by the NAND circuit 17.

Using the H level of the R input 20 as an input,
Flip-flop circuit 14 and flip-flop circuit 16
Is reset. During this reset operation, the output signal 21
And 22 go to the L level. Since these output signals 21 and 22 are inputted to the exclusive OR circuit 24, the output 25 of the exclusive OR circuit 24 becomes H level, and this is inputted to the two-phase clock T1 by the clock generator 11.
H level is output to (8).

Therefore, the period of the two-phase clock T1 is also determined by the H level input period of the control signal 2. However, when the control signal 2 is returned to the L level to end the H level output period of the two-phase clock T1, the flip-flop is used. The loop circuit 14 returns from the reset state in synchronization with the rising edge of the reference clock 1. Similarly, the flip-flop circuit 16 returns from the reset state in synchronization with the rising edge of the clock 15 obtained by inverting the reference clock 1. As a result, the reference clock 1 or the clock 15 obtained by inverting the reference clock is used.
Output signal 2 after the rising edge
Either 1 or 22 becomes H level.

When one of the output signals 21 and 22 becomes H level, the output signal 25 of the exclusive OR circuit outputs L level, the two-phase clock T1 becomes L level, and the two-phase clock T2 becomes H level. Become. Therefore, the H-level period of the two-phase clock T1 can be set to an integer multiple including the odd multiple and the even multiple of the basic pulse width 31.

Next, in order to vary the H level period of the two-phase clock T1, the control signal 2 is changed to the H level when the output signal 21 of the flip-flop circuit 14 and the output signal 22 of the flip-flop circuit 16 are both at the H level. Then N
The L level is input to the set input 13 of the flip-flop circuits 14 and 16 by the AND circuit 17. Since the set input 13 is low active, the flip-flop circuit 14 and the flip-flop circuit 16 are set by using this L level as an input. During this set operation, the output signals 21 and 22 output the H level.

Since the output signals 21 and 22 are input to the exclusive OR circuit 24, an H level is output to the output 25 of the exclusive OR circuit 24. The H level is output as the clock T1. Therefore, the period of the two-phase clock T1 is also determined by the H level input period of the control signal 2, but the control signal 2
Is returned to the L level to end the H-level output period of the two-phase clock T1 of 8, the flip-flop circuit 14 returns from the reset state in synchronization with the rising edge of the reference clock 1. Similarly, the flip-flop circuit 16 returns from the reset state in synchronization with the rising edge of the clock 15 obtained by inverting the reference clock 1. As a result,
Reference clock 1 or clock 1 inverted from reference clock 1
After the rising edge of 5 whichever comes first,
One of the output signals 21 and 22 becomes L level.

When one of the output signals 21 and 22 becomes L level, the output signal 25 of the exclusive OR circuit outputs L level, T1 of 8 becomes L level, and T2 of 9 becomes H level. Therefore, the H level period of the two-phase clock T1 can be set to an integer multiple including an odd multiple and an even multiple of the basic pulse width of 31.

(Embodiment 2) Next, a circuit diagram of a four-phase clock generator according to a second embodiment of the present invention is shown in FIG.
Shown in FIG. 7 shows the operation timing of this circuit. In FIG. 6, reference numeral 32 denotes a frequency divider which outputs a quarter frequency signal of the reference clock which is shifted by a quarter period from each other in synchronization with the reference clock 1 or a clock obtained by inverting the reference clock, and 27 denotes a frequency divider A control circuit that aligns all 32 output signals at H level or L level and determines the H level output holding period of the four-phase clock T1. 1/4 phase shifted by 1/4 cycle in synchronization with the output signal of the frequency divider circuit that outputs the 1 frequency-divided signal and the clock obtained by inverting the reference clock.
An exclusive-OR circuit for performing an exclusive-OR operation with an output signal of a frequency-dividing circuit that outputs a frequency-divided signal;
3 to T1
Reference numeral 35 denotes a clock control circuit for controlling the four operations, and reference numeral 35 denotes a four-phase clock generation circuit.

A quarter frequency dividing circuit 36 for changing the output signal in synchronization with the reference clock and a quarter frequency dividing circuit 37 for changing the output signal in synchronization with the inverted clock of the reference clock. A delay circuit 38 for delaying the output signal of the preceding stage by a quarter period in synchronization with the reference clock, and a delay circuit for delaying the output signal of the preceding stage by a quarter of the frequency in synchronization with the inverted clock of the reference clock 39 and 4
A signal having a phase shifted by one-half period is generated. Similarly,
Delay circuit 4 for delaying the output signal of the second stage by a quarter period
Delay circuits 42 and 43 for delaying output signals of 0, 41 and the third stage by a quarter period are provided. In this combination, one set of a quarter frequency divider circuit and three sets of a quarter cycle delay circuit are added to generate four-phase output signals whose phases are shifted by a quarter cycle from each other.

The 1/4 frequency-divided signals generated in this manner and shifted by a quarter period from each other are obtained by taking the exclusive OR of the output signals generated in the respective stages.
It is possible to generate a signal having an L level period by a reference pulse width shifted in phase by a quarter period. The circuit block 34, which receives the four exclusive OR output signals as inputs, and includes four AND circuits, outputs the k-th clock from the one-phase to four-phase clocks generated by the clock generator to Tk. When a clock is used, four inputs (k
-1) A Tk clock is generated by making an AND circuit that inverts and inputs the first input signal.

During the period when the H level is input to the control signal 2 in order to set T1 to an integral multiple of the reference pulse width 31, all of the output signals 60, 61, 62 and 63 are at the H level or L level.
Since the signal is held at the level, only the AND circuit 48 outputs the H level, so that the H level output holding period of T1 is reached. The other Tk clocks become L-level output holding periods by the AND circuits 49, 50, and 51 that invert and input the (k-1) th input signal.

Therefore, the H-level input period of the control signal 2 also determines the H-level output period of the four-phase clock T1.
When the 1-level output period ends, the 1/4 frequency divider circuits 36 and 37, the delay circuits 38 and 39, 40, 41, and 42
According to steps (43) and (43), after the rising edge of the reference clock or the inverted clock of the reference clock, whichever comes first, the set or reset state is returned with a shift of a quarter period. As a result, the H-level output period of the four-phase clock T1 can be set to an integer multiple including an odd multiple and an even multiple of the basic pulse width of 31.

Third Embodiment FIG. 8 is a circuit diagram of an N-phase clock generator according to a third embodiment.
FIG. 9 shows the operation timing. In FIG. 8, reference numeral 64 denotes a frequency divider which outputs a 1 / N frequency-divided signal of the reference clock which is shifted by 1 / N cycle from each other in synchronization with the reference clock 1 or a clock obtained by inverting the reference clock. A control circuit 65 that aligns all the output signals 64 to H level or L level and determines the H level output holding period of the N-phase clock T1. An output signal of a frequency divider that outputs a frequency-divided signal and an output signal of a frequency divider that outputs a frequency-divided signal divided by 1 / N in phase with a clock obtained by inverting the reference clock; A clock control circuit 66 that receives the output signal of the frequency dividing circuit 65 or its inverted signal and controls T1 to T4, and a reference numeral 67 denotes an N-phase clock generation circuit.

A 1 / N frequency divider 36 that changes the output signal in synchronization with the reference clock, and a 1 / N frequency divider 37 that changes the output signal in synchronization with the inverted clock of the reference clock. A delay circuit 38 for delaying the output signal of the preceding stage by 1 / N period in synchronization with the reference clock, and a delay circuit for delaying the output signal of the preceding stage by 1 / N in synchronization with the inverted clock of the reference clock 39 and N
A signal having a phase shifted by one-half period is generated. Similarly,
Delay circuit 4 for delaying the output signal of the second stage by 1 / N cycle
Delay circuits 68 and 69 for delaying the output signals of the 0th and 41st stages and the (N-1) th stage by 1 / N cycle are provided. In this combination, one set of a 1 / N divider circuit and a 1 / N period delay circuit are set to N
By adding −1 set, an N-phase output signal having a phase shifted by 1 / N from each other is generated.

The 1 / N frequency-divided signals generated as described above and shifted in phase by 1 / N from each other are obtained by taking the exclusive OR of the output signals generated in the respective stages.
It is possible to generate a signal that is in the L-level period by the reference pulse width shifted in phase by 1 / N cycle. The clock control circuit 66, which receives the above-mentioned N exclusive OR output signals and is composed of N AND circuits, generates a k-th clock as a Tk clock among the generated 1-phase to N-phase clocks. In this case, an AND circuit for inverting and inputting the (k-1) th input signal of the N inputs is used.
Generate k clocks.

During the period when the H level is input to the control signal 2 in order to set T1 to an integral multiple of the reference pulse width 31, all of the output signals 60, 61, 62 and 74 are at the H level or L level.
Since the signal is held at the level, only the AND circuit 48 outputs the H level, so that the H level output holding period of T1 is reached. The other Tk clocks are the L-level output holding periods by the AND circuits 49, 50, and 71 that invert and input the (k-1) th input signal.

Therefore, the H-level output period of the N-phase clock T1 is also determined by the H-level input period of the control signal 2, but the control signal 2 is returned to the L level to change the N-phase clock T1.
When the H-level output period of 1 ends, the 1 / N frequency divider circuits 36 and 37, the delay circuits 38 and 39, 40, 41, and 68
As a result, the set or reset state is returned with a shift of 1 / N cycle after the rising edge of the reference clock or the inverted clock of the reference clock whichever comes first. As a result, the H-level output period of the N-phase clock T1 can be set to an odd multiple or an even multiple of the basic pulse width of 31.

[0029]

As described above, according to the clock generator of the present invention, the output signal of the frequency dividing circuit for dividing the reference clock in synchronization with the reference clock and the inverted clock is fixed at the H level or the L level. A control circuit for generating a control signal and an exclusive-OR circuit for performing an exclusive-OR operation on the output signal of the frequency divider circuit to synchronize the output level of the N-phase clock with the reference clock and its inverted clock. Therefore, a whisker-like pulse narrower than the conventional reference pulse width does not occur. Further, since the H-level output period of the first phase clock of the N-phase clock can be set to an integer multiple including an odd multiple and an even multiple of the basic pulse width, the memory access cycle can be finely controlled.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock generator according to the present invention.

FIG. 2 is a circuit diagram of a two-phase clock generator according to the first embodiment of the present invention.

FIG. 3 is a timing chart of the two-phase clock generator of FIG. 2;

FIG. 4 is a circuit diagram of a conventional clock generator.

FIG. 5 is a timing chart of a conventional clock generator.

FIG. 6 is a circuit diagram of a four-phase clock generator according to a second embodiment of the present invention.

FIG. 7 is a timing chart of the four-phase clock generator of FIG. 6;

FIG. 8 is a circuit diagram of an N-phase clock generator according to a third embodiment of the present invention.

FIG. 9 is a timing chart of the N-phase clock generator of FIG. 8;

[Description of Signs] 1 Reference clock 3 NOR circuit 5, 23 Inverter circuit 6, 7, 17 NAND circuit 11 Clock generation circuit 14, 16 Flip-flop circuit 18 OR circuit 19 AND circuit 24, 33 Exclusive OR circuit 26 Frequency division Circuit 27 Control circuit 32 1/4 cycle delay circuit 34 Decoder circuit 35 4 phase clock generation circuit 36, 37 1/4 frequency divider 38, 39, 40, 41, 42, 43 1/4 cycle phase delay circuit 44, 45, 46, 47 Exclusive OR circuit 48 AND circuit 64 1 / N cycle delay circuit 65, 70 Exclusive OR circuit 66 Decoder circuit 67 N-phase clock generation circuit 68, 69 1 / N cycle phase delay circuit

Claims (3)

[Claims] A frequency dividing circuit that divides a frequency of a reference clock by half in synchronization with a reference clock and a clock obtained by inverting the frequency of the reference clock and outputs two signals whose phases are shifted by a half cycle from each other; A control circuit for generating a signal for controlling both output signals of the circuit to an H level or an L level; and an exclusive OR circuit for obtaining an exclusive OR of the two output signals of the frequency dividing circuit. A clock generator for changing an output state of a generated two-phase clock in synchronization with a reference clock and an inverted clock thereof. 2. The reference clock is frequency-divided by a quarter in synchronization with a reference clock and an inverted clock thereof.
A frequency dividing circuit for outputting four signals whose phases are shifted by a quarter cycle, a delay circuit for delaying an output signal of a preceding stage by a quarter cycle in synchronization with the reference clock and a clock obtained by inverting the reference clock; All output signals of the frequency divider and the delay circuit are set to H
A control circuit for generating a signal to be controlled to a level or an L level; four output signals of the frequency divider;
An exclusive-OR circuit for performing an exclusive-OR operation with two output signals, and using the four output signals of the exclusive-OR circuit as inputs, to control the output of each of the first to fourth phase clocks. A clock generator, comprising: a clock generation circuit configured by a decoder circuit; and changing an output state of a generated four-phase clock in synchronization with the reference clock and an inverted clock thereof. 3. When an arbitrary number of N-phase clocks are generated, the reference clock is frequency-divided by 1 / N in synchronization with the reference clock and its inverted clock, and their phases are shifted by 1 / N from each other. A frequency divider that outputs N signals, a delay circuit that delays the output signal of the preceding stage by 1 / N cycle in synchronization with the reference clock and its inverted clock, the frequency divider and the delay A control circuit for generating a signal for controlling all output signals of the circuit to H level or L level; and exclusive OR of N output signals of the frequency divider circuit and N output signals of the delay circuit A clock generation circuit including an exclusive OR circuit, and a decoder circuit that receives N output signals of the exclusive OR circuit as inputs and controls respective outputs of clocks from a first phase to an Nth phase; With
In synchronization with the reference clock and its inverted clock,
A clock generator for changing an output state of a generated N-phase clock.