JPH0382221A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To make the relation of phase of two frequency division outputs stable by forming a frequency divider circuit with one flip-flop and one delay element in place of provision of the frequency divider circuit with two flip-flops. CONSTITUTION:A frequency division signal A subject to 1/2 frequency division is generated at the output terminal through the input of a clock from a square wave oscillator 11 and the frequency division signal A is inputted to input terminals 1A, 2B of a distributer 14. A frequency division signal produced by retarding by 1/2 period of the clock at a delay element 13 from the frequency division signal A is inputted to input terminals 1B, 2A of the distributer 14. With a level of an S terminal set to an L, the distributer 14 selects the signals of the input terminals 1A, 2A, and outputs the selected signal from the output terminals 1Y, 2Y and with a level of the S terminal set to an H, the distributer 14 selects the signals of the input terminals 1B, 2B and outputs the selected signal from the output terminals 1Y, 2Y and then a desired timing is obtained in the relation of frequency division signals C, D by giving the L or H level to the terminal S. Thus, the relation of phase of two frequency division outputs is made stable.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a frequency dividing circuit.

[Conventional technology]

A conventional frequency divider circuit includes two frequency dividers and an inverter.

Next, a conventional frequency dividing circuit will be explained in detail with reference to a circuit diagram.

FIG. 3 is a circuit diagram showing an example of a conventional frequency dividing circuit.

The frequency divider circuit shown in Fig. 3 consists of a square wave oscillator 1 and two F/
It includes a frequency divider formed by F (flip-flops) 2 and 3, an inverter 4, and an AND element 5. A frequency divider using F/F2 that inputs the signal (clock) of the square wave oscillator l to the CLK terminal and the reset signal to the reset terminal, and this and the CL
A frequency divider using different F/F3 inputs the inverted signal of the square wave oscillator 1 signal to the K terminal.
When a square wave is input, the output of each frequency divider generates a square wave signal having a period twice that of the square wave signal input to the CLK terminal, and which is shifted by 1/4 period from each other. Furthermore, an AND signal is taken from these two frequency-divided outputs to create a reference timing.

[Problem to be solved by the invention]

In the conventional frequency divider circuit described above, after resetting the F/F, it is not possible to decide which of the two F/Fs 2 and 3 to start dividing. In other words, one is 1/4 lower than the other.
Since there are cases where the cycle advances and cases where there is a delay of 1/4 cycle, there is a drawback that the phase relationship between the two frequency-divided outputs is not stable depending on the timing of the clock and reset release as shown in FIG. In FIG. 4, frequency-divided signals E and F indicate the outputs of flip-flops 2 and 3, respectively, and an AND signal indicates an AND signal.
The output of element 5 is shown.

[Means to solve the problem]

The frequency divider circuit of the present invention includes a square wave oscillator that outputs a clock, a flip-flop to which a reset signal is input to a reset terminal and the clock is input to a CLK terminal, and an output signal of this flip-flop is divided by 1/1 of the clock. a delay element that delays by two periods; a state in which the output signal of the flip-flop is output to one output terminal and an output signal of the delay element to the other output terminal; and an output signal of the delay element to the one output terminal; a distributor that selects a state in which the output signal of the flip-flop is output to the other output terminal; and an AND element that inputs signals from the one output terminal and the other output terminal of the distributor. It consists of:

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

Here, the principle of stabilizing the phase relationship of the output of the frequency divider of this frequency dividing circuit will be explained. First, when the clock from the square wave oscillator 11 is input to the CLK terminal of the F/F 11, a frequency-divided signal A whose frequency is divided by 1/2 is generated at the output terminal. This frequency-divided signal A is input to the input terminals IA and 2B of the distributor 14.
Enter.

The divided signal A is converted to 1 of the clock by DL (delay element) 13.
The frequency-divided signal B generated by delaying the frequency by /2 periods is inputted to the input terminals IB and 2A of the distributor 14 as shown in FIG.

When the level of the S terminal is L (low level), the output terminal IY,
2Y is a distributor that selects and outputs the signals of input terminals IA and 2A, respectively, and when the S terminal level is HC high level, output terminals IY and 2Y select and output signals of input terminals IB and 2B, respectively. 14, the phase relationship between the output signal No. 18 of the terminal IY (hereinafter referred to as the frequency divided signal C) and the output signal of the terminal 2Y (hereinafter referred to as the frequency divided signal) is given by the level of the S terminal of the distributor 14. The desired timing can be obtained by 2 Figure 2<A) and (B) show the time charts for these two cases.In the case shown in Figure 2 (A), when the S terminal is set to is 1/4 cycle ahead of the divided signal,
In the case shown in FIG. 2(B), when the S terminal is set to H, the frequency-divided signal C lags behind the frequency-divided signal by 1/4 period. In addition,
FIG. 2 shows an AND signal output by the AND element 15 which receives the frequency-divided signals C and D.

Also, since only one flip-flop is used, there is no effect from reset.

〔Effect of the invention〕

The frequency dividing circuit of the present invention can form a frequency dividing circuit with one flip-flop and one delay element instead of using two flip-flops, so it is not affected by resetting the flip-flop. This has the effect of stably realizing the phase relationship between the two frequency dividing circuits.

[Brief explanation of drawings]

FIGS. 1 and 2 are a block diagram of an embodiment of the present invention and a time chart showing the phase relationship of frequency-divided signals, and FIGS. 3 and 4 are a block diagram and a frequency-divided circuit of a conventional frequency dividing circuit, respectively. 5 is a time chart showing the phase relationship of signals. 1.11...Square wave oscillator, 2.3.12...Flip-flop, 13...Delay element, 14...Distributor.

Claims (1)

[Claims] A square wave oscillator that outputs a clock, a flip-flop whose reset terminal receives a reset signal and whose CLK terminal receives the clock, a delay element which delays the output signal of this flip-flop by 1/2 cycle of the clock, and one output. One output terminal outputs the output signal of the flip-flop and the other output terminal outputs the output signal of the delay element, and one output terminal outputs the output signal of the delay element, and the other output terminal outputs the flip-flop output signal. 1. A frequency dividing circuit comprising: a divider that selects a state of outputting an output signal of the divider; and an AND element that inputs signals from the one output terminal and the other output terminal of the divider.