JPH0394513A - Polyphase synchronizing signal generator - Google Patents

Abstract

PURPOSE:To generate a polyphase synchronizing signal in the inside of a VLSI synchronously with an external polyphase synchronizing signal and equivalent to the polyphase synchronizing signal at the outside of the VLSI by inputting two signals, a reference clock signal and a reference synchronizing signal representing the start of a 1st phase of the polyphase synchronizing signal. CONSTITUTION:A counter 1 is reset by a reference synchronizing signal indicating the start of a clock signal S1 of the 1st phase of a 4-phase synchronizing signal and counts a reference clock signal S0 being a reference of a phase difference of clock signals S1-S4 of the 4-phase synchronizing signal. The count is decoded by a decoder 2 to generate the required 4-phase synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is useful for applications where the number of input/output signals is limited. sI
The present invention relates to a multiphase synchronization signal generation device for a so-called clock generation circuit that generates a multiphase synchronization signal used in a logic circuit system including a small number of signals.

[Prior Art] Conventional timing design for complex and advanced logic circuit systems is generally performed using multiphase synchronization signals as system clock signals, since the operating time varies depending on the type of logic elements that make up the circuit. be exposed.

As shown in Fig. 4, by using an N-phase multiphase synchronous transmission with one period of the clock signal Sa-Sn as T, the rising and falling edges of 2N clocks can be used as timing standards, and the time The resolution becomes T/2N. As a result, detailed timing design is possible, so it is widely used especially in logic circuit systems that require high-speed processing.

[Problems to be Solved by the Invention] When the aforementioned N-phase multiphase synchronization signal is used as a system clock signal, N signal lines are basically required to transmit this signal. In a logic circuit system that uses many VLSIs, there is a restriction on the total number of VLSI input/output signal lines, so using a multiphase synchronous signal as a system clock signal has the drawback of increasing costs.

In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a multiphase synchronization signal generator that can input N-phase multiphase synchronization signals to a VLSI using only at least two signal lines.

[Means for Solving the Problems] The first feature of the multiphase synchronization signal generator of the present invention is to solve the problems described above, in which, in a system using a multiphase synchronization signal, the first phase of the multiphase synchronization signal is a means for receiving a reference synchronization signal instructing a start, and a configuration means for generating a predetermined multiphase synchronization signal from two signals of the reference clock signal and the reference synchronization signal; In a system using a multiphase synchronization signal having an operation mode, means for receiving a reference clock signal that is the basis of the phase difference between each phase of the multiphase synchronization signal, and for instructing the start of the first phase of the multiphase synchronization signal. means for receiving a reference synchronization signal; and means for receiving a signal specifying an operation mode;
The third feature is a configuration means for generating a multiphase synchronization signal of a predetermined mode from a signal, and a configuration means for avoiding unnecessary electromagnetic radiation by placing a frequency multiplier circuit upstream of the means for receiving a reference clock signal. This is achieved by adopting

[Function] The present invention takes the above-mentioned measures, installs a multiphase clock generation circuit that can be read externally inside a VLSI, and generates a reference clock signal that is the basis of the phase difference between each phase of a multiphase synchronization signal. , 2 of the reference synchronization signal that instructs the start of the first phase of the multiphase synchronization signal.
By inputting a signal (or a signal to which a signal specifying the operation mode is added) to vLS■, a polyphase synchronization signal that is equivalent to the VLSI external polyphase synchronization signal and synchronized with the external polyphase III signal is output to the VLSI. Generate internally. Since the multiphase synchronous signal generator of the present invention has a small circuit scale, the increase in cost due to adding this circuit to VLSI is
The effect of reducing the number of LSI signal lines is greater.

[Example 1] A first embodiment of the invention will be described with reference to FIG.

The present embodiment shown in the figure is an example of a four-phase synchronous signal. In the figure, A is a multiphase clock generation circuit, 1 is a 3-bit counter, and 2 is a decoder. FIG. 2 is a timing chart showing operating waveforms of each part.

The operation of this embodiment is such that the counter 1 is reset by the reference synchronization signal S instructing the start of the first phase clock signal 81 of the four-phase synchronization signal, and then the clock signals S1 to S4 of each phase of the four-phase synchronization signal are used. The reference clock signal SO, which is the basis of the phase difference, is counted. The count value is decoded by a decoder 2 to generate a predetermined four-phase synchronization signal.

In addition, the operation mode designation signal S input to the decoder 2
By switching and changing one, it is possible to change the decoding method and change the waveform of the reference synchronization signal S.

Furthermore, when there is only one operation mode designation signal S1 as in this embodiment, by using it also as the reference synchronization signal S, the number of signal lines input to the VLSI can be further reduced.

[Example 2] A second embodiment of the invention will be described with reference to FIG.

If precise timing is required, the frequency of the reference clock signal SO becomes high in the first embodiment shown in FIG. 1, causing problems such as unnecessary electromagnetic radiation.

In such a case, as shown in FIG. 3, a frequency multiplier circuit 3 may be placed inside the VLSI to increase the frequency. In the figure, B is a multiphase clock generation circuit, 4 is a 3-pit counter, and 5 is a decoder, which operate in the same manner as the first embodiment shown in FIG.

[Effects of the Invention] Thus, by using the multiphase synchronization signal generator of the present invention, it is possible to use multiphase synchronization signals with a small number of signal lines in a logic circuit system that uses VLSI extensively. It has a great effect.

[Brief explanation of drawings]

1 and 2 are block configuration diagrams and timing charts of operating waveforms showing a first embodiment of the present invention, and FIGS.
The figure is a block diagram showing a second embodiment of the present invention, and FIG. 4 is a timing chart of an example of a multiphase synchronization signal. A. B... Multiphase clock generation circuit 1.4... 3-bit counter 2.5... Decoder 3... Frequency multiplier circuit S
...Reference synchronization signal @ S1...Operating mode designation signal SO...Reference clock signal Sa, S1...First phase clock signal Sb. 82...Second phase clock No. 4H S3...Third
Phase clock signal S4...Third phase clock signal Sn...Nth phase clock signal T...Period 3rd r! A '4: Semi-synchronous code S Operation mode 'r: 48 key S' Count value 1 Figure 2 012345670I 23456701234567
1fJN phase Sn Fig. 4 4th phase S4

Claims (1)

[Claims] 1. In a system using a multiphase synchronization signal, means for receiving a reference clock signal that is the basis of the phase difference between each phase of the multiphase synchronization signal; A multiphase synchronization signal generating device, comprising means for receiving a reference periodic signal instructing a start, and generating a predetermined multiphase synchronization signal from two signals: the reference clock signal and the reference synchronization signal. 2. In a system using a multiphase synchronization signal having multiple operation modes, means for receiving a reference clock signal that is the basis of the phase difference between each phase of the multiphase synchronization signal, and It has a means for receiving a reference synchronization signal instructing to start, and a means for receiving a signal specifying an operation mode, and a predetermined operation mode is selected from the three signals of the reference clock signal, the reference synchronization signal, and the operation mode designation signal. A multiphase synchronous signal generator that generates a multiphase synchronous signal. 3. Claim 1, wherein the means for receiving the reference clock signal is provided with a frequency multiplier circuit at the front stage to avoid unnecessary electromagnetic radiation.
Or the multiphase synchronous signal generator according to 2.