JPH0389556A - Manufacture of semiconductor memory - Google Patents
Manufacture of semiconductor memoryInfo
- Publication number
- JPH0389556A JPH0389556A JP22633389A JP22633389A JPH0389556A JP H0389556 A JPH0389556 A JP H0389556A JP 22633389 A JP22633389 A JP 22633389A JP 22633389 A JP22633389 A JP 22633389A JP H0389556 A JPH0389556 A JP H0389556A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- forming
- silicon oxide
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 30
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 30
- 230000015572 biosynthetic process Effects 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、フローティングゲート型の電界効果トランジ
スタからなる半導体記憶装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device comprising a floating gate field effect transistor.
従来の技術
従来、電気的書き込み消去が可能なEEPROM(El
ectrically Erasable and P
rogramableROM)の1つとして、トンネル
注入により書き込み消去を行うフローティング構造の゛
半導体記憶装置がよく知られている。このフローティン
グゲート型の半導体記憶装置は、拡散層上の薄い絶縁膜
を介して電荷のトンネル注入を行い、絶縁膜上のフロー
ティングゲート電極に電荷を蓄積させ、トランジスタの
しきい値電圧を変化させて情報を記憶させることを原理
としいる。BACKGROUND OF THE INVENTION Conventionally, EEPROM (El
electrically Erasable and P
2. Description of the Related Art A semiconductor memory device with a floating structure in which writing and erasing is performed by tunnel injection is well known as one type of programmable ROM. This floating gate type semiconductor memory device tunnel-injects charges through a thin insulating film on the diffusion layer, accumulates charges in the floating gate electrode on the insulating film, and changes the threshold voltage of the transistor. The principle is to memorize information.
第2図に代表的なフローティングゲート型の半導体記憶
装置の断面構造図を示す。第2図に示すように、P型の
シリコン基板lの中にN型拡散層からなるソース領域2
及びドレイン領域3が形成され、前記ソース領域2、ド
レイン領域3にまたがって比較的厚い酸化シリコン膜4
が形成されるとともに、この酸化シリコン4の一部分の
みを開孔し、この開孔部にトンネル媒体となりうる薄い
酸化シリコン膜5が形成され、酸化シリコン膜4.5の
上にフローティングゲート電極6.酸化シリコン膜7及
びコントロールゲート電極8が順次積層された構造とな
っている。FIG. 2 shows a cross-sectional structural diagram of a typical floating gate type semiconductor memory device. As shown in FIG. 2, a source region 2 consisting of an N-type diffusion layer is formed in a P-type silicon substrate l.
and a drain region 3 are formed, and a relatively thick silicon oxide film 4 is formed over the source region 2 and the drain region 3.
is formed, and only a portion of this silicon oxide 4 is opened, a thin silicon oxide film 5 that can serve as a tunnel medium is formed in this opening, and a floating gate electrode 6. is formed on the silicon oxide film 4.5. It has a structure in which a silicon oxide film 7 and a control gate electrode 8 are sequentially laminated.
従来、第2図のごときフローティングゲート型の半導体
記憶装置を製造する場合、通常、ドレイン領域3上に比
較的厚い酸化シリコン膜4を形成し、この酸化シリコン
膜4の一部分を公知のフォトエツチング技術によりドレ
イン領域3に達するように開孔し、この開孔部に通常1
5−20Vのプログラム電圧で書き込み消去ができるよ
うに、100A程度の非常に薄い酸化シリコン膜5を形
成させる必要があるが、この非常に薄い酸化シリコン膜
5を制御性よく安定して形成するために、通常、900
℃程度の比較的低い温度で酸化させて形成させていた。Conventionally, when manufacturing a floating gate type semiconductor memory device as shown in FIG. 2, a relatively thick silicon oxide film 4 is usually formed on the drain region 3, and a portion of this silicon oxide film 4 is etched using a known photoetching technique. A hole is opened to reach the drain region 3, and usually 1
In order to be able to write and erase with a program voltage of 5-20V, it is necessary to form a very thin silicon oxide film 5 of about 100 A, but in order to form this very thin silicon oxide film 5 stably with good controllability. Usually 900
It was formed by oxidation at a relatively low temperature of around °C.
一方、トンネル絶縁膜形成後は、トンネル絶縁膜上にフ
ローティングゲート電極を形成し、さらにフローティン
グゲート電極上に絶縁膜を介してコントロールゲート電
極を形成する必要があるが、70−ティング電極及びコ
ントロールゲート電極は、ポリシリコン等の高融点金属
を通常用いるため、トンネル絶縁膜形成後の熱処理とし
ては1000℃−1100℃程度の比較的高温の熱処理
工程を用いることが通常であった。On the other hand, after forming the tunnel insulating film, it is necessary to form a floating gate electrode on the tunnel insulating film and further to form a control gate electrode on the floating gate electrode via an insulating film. Since the electrode usually uses a high melting point metal such as polysilicon, a relatively high temperature heat treatment process of about 1000° C. to 1100° C. is usually used as the heat treatment after forming the tunnel insulating film.
発明が解決しようとする課題
フローティングゲート型の半導体記憶装置は、非常に薄
いトンネル絶縁膜を介して電荷のトンネル媒体を行うこ
とにより書換えを行うものであり、その書換え回数の確
保がフローティングゲート型半導体記憶装置の最大の課
題であり、また実用上の重要な問題であるが、上述のご
とき従来の製造方法により作製されたフローティングゲ
ート型の半導体記憶装置では、繰り返し書換えを行うと
非常に破壊しやすく、精度よく安定した書換え回数を確
保することが非常に難しいといった問題点を有していた
。Problems to be Solved by the Invention Floating gate type semiconductor memory devices perform rewriting by performing charge tunneling through a very thin tunnel insulating film. The biggest problem with storage devices, and one of the most important in practical terms, is that floating gate semiconductor storage devices manufactured using the conventional manufacturing method described above are extremely susceptible to destruction if repeatedly rewritten. However, the problem was that it was very difficult to ensure an accurate and stable number of rewrites.
本発明は、上記従来の問題を解決するものであり、フロ
ーティングゲート構造の半導体記憶装置の製造方法にお
いて、繰り返し書換え特性の飛躍的な向上をはかること
ができる製造方法を提供することを目的とするものであ
る。The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a manufacturing method for a semiconductor memory device having a floating gate structure, which can dramatically improve the repeatable rewriting characteristics. It is something.
課題を解決するための手段
上記目的を達成するために、本発明は一導電型半導体シ
リコン基板の表面から内部にかけて、前記基板と反対導
電型の拡散層を形成する工程と、前記基板の表面上に第
1の絶縁膜を形成する工程と、前記第1の絶縁膜の所定
の部分に前記拡散層に達するような開孔部を形成する工
程と、前記開孔部の拡散層表面上にトンネル媒体となり
つる第2の絶縁膜を形成する工程と、前記第2の絶縁膜
上にフローティングゲート電極を形成する工程と、前記
フローティングゲート電極上に第3の絶縁膜を介してコ
ントロールゲート電極を形成する工程を少なくとも含む
半導体記憶装置の製造方法において、上記第2の絶縁膜
の形成後の全ての熱処理工程が、上記第2の絶縁膜の形
成温度+50℃以下で行うものである。Means for Solving the Problems In order to achieve the above object, the present invention provides a step of forming a diffusion layer of a conductivity type opposite to that of the substrate from the surface to the inside of a semiconductor silicon substrate of one conductivity type, and a step of forming a diffusion layer on the surface of the substrate. forming a first insulating film in the first insulating film, forming an opening in a predetermined portion of the first insulating film to reach the diffusion layer, and forming a tunnel on the surface of the diffusion layer in the opening. forming a second insulating film that serves as a medium; forming a floating gate electrode on the second insulating film; and forming a control gate electrode on the floating gate electrode via a third insulating film. In the method for manufacturing a semiconductor memory device including at least the step of forming the second insulating film, all heat treatment steps after forming the second insulating film are performed at a temperature of +50° C. or less for forming the second insulating film.
作用
本発明者の検討によれば、破壊に至る繰り返し書換え回
数は、第2の絶縁膜を形成した後の熱処理工程が大きく
依存していることがわかり、特に第2の絶縁膜形成後の
熱処理温度を、第2の絶縁膜の形成温度より50℃をこ
える高い温度にすると繰り返し書換え特性が非常に悪化
することを見い出した。According to the study conducted by the present inventor, it has been found that the number of repeated rewrites leading to destruction is largely dependent on the heat treatment process after forming the second insulating film, and in particular, the heat treatment process after forming the second insulating film. It has been found that when the temperature is set to a temperature higher than the formation temperature of the second insulating film by more than 50° C., the repeated rewriting characteristics deteriorate significantly.
本発明は、上記事実に基づきなされたもので、本発明の
ごときトンネル絶縁膜形成後の熱処理温度をトンネル絶
縁膜の形成温度+50℃以下にすることにより、繰り返
し書換えを行っても破壊しにくくなり、信頼性の確保が
非常に容易となるものである。このような繰り返し書換
え特性が飛躍的に向上するメカニズムについては、詳細
なことは不明であるが、トンネル媒体となる第2の絶縁
膜形成後の熱処理の温度を第2の絶縁膜形成温度+50
℃以下にすることにより薄い第2の絶縁膜への熱ストレ
スが緩和され、第2の絶縁膜に歪やトラップが発生する
ことが少なくなり、繰り返し書換えを行っても破壊しに
くくなるものと推定される。また、上記第2の酸化膜の
形成温度が1050℃以上になると、本発明の効果がほ
とんどなくなり、トンネル酸化膜の形成温度は1050
℃以下にする必要があることも見い出した。The present invention has been made based on the above fact, and by setting the heat treatment temperature after forming the tunnel insulating film as in the present invention to 50°C or less above the formation temperature of the tunnel insulating film, it becomes difficult to break down even when repeatedly rewritten. , it becomes very easy to ensure reliability. Although the details of the mechanism by which such repeated rewriting characteristics are dramatically improved are unknown, the temperature of the heat treatment after forming the second insulating film, which will serve as a tunnel medium, is increased by 50° to the second insulating film formation temperature.
It is estimated that by keeping the temperature below ℃, the thermal stress on the thin second insulating film will be alleviated, causing less distortion and traps in the second insulating film, and making it less likely to be destroyed even after repeated rewriting. be done. Further, when the formation temperature of the second oxide film becomes 1050°C or higher, the effect of the present invention is almost lost, and the formation temperature of the tunnel oxide film becomes 1050°C or higher.
It was also found that it is necessary to keep the temperature below ℃.
実施例 本発明の具体的な実施例を図面を用いて説明する。Example Specific embodiments of the present invention will be described with reference to the drawings.
第1図は、本発明の一実施例を示した工程順断面図であ
る
まず、第1図Aに示すようにP型シリコン基板1上に、
既知の選択拡散技術によりN型拡散層からなるソース領
域2、及びドレイン領域3を形成し、その後、酸化シリ
コン膜4を通常の熱拡散法により形成する。酸化シリコ
ン膜4の厚さは、基板からのトンネルが起こらないよう
に厚くする必要があり、本実施例では約500Aとした
。次に、ドレイン領域3上の酸化シリコン膜4の所定の
部分を既知のフォトエツチング技術によりエツチングを
行い、トンネル領域となる開口部を形成する。FIG. 1 is a step-by-step sectional view showing an embodiment of the present invention. First, as shown in FIG. 1A, on a P-type silicon substrate 1,
A source region 2 and a drain region 3 made of N-type diffusion layers are formed by a known selective diffusion technique, and then a silicon oxide film 4 is formed by a normal thermal diffusion method. The thickness of the silicon oxide film 4 needs to be thick so that tunneling from the substrate does not occur, and in this example, it was set to about 500A. Next, a predetermined portion of the silicon oxide film 4 on the drain region 3 is etched using a known photoetching technique to form an opening that will become a tunnel region.
次に、第1図Bに示すように、トンネル媒体となりうる
薄い酸化シリコン膜5を開孔部に形成するが、その形成
温度としては、1050℃以下にする必要がある。本実
施例では、1000℃、アルゴン希釈下のドライ酸素雰
囲気で実施した。また、トンネル効果を有効に利用する
には、酸化シリコンQI5の厚さを5O−150A程度
にする必要があり、本実施例では100A形成させた。Next, as shown in FIG. 1B, a thin silicon oxide film 5 that can serve as a tunnel medium is formed in the opening, but the formation temperature must be 1050° C. or lower. This example was carried out at 1000° C. in a dry oxygen atmosphere diluted with argon. Further, in order to effectively utilize the tunnel effect, the thickness of the silicon oxide QI 5 needs to be approximately 50-150A, and in this example, it was formed to be 100A.
さらに、このトンネル酸化シリコン膜5の形成後の全て
の熱処理温度は、トンネル媒体の酸化シリコン膜形成温
度+50℃以下にする必要があり、本実施例では、以下
に述べるように950℃以下で実施した。Furthermore, the temperature of all heat treatments after the formation of the tunnel silicon oxide film 5 must be lower than the silicon oxide film formation temperature of the tunnel medium + 50°C, and in this example, the temperature is 950°C or lower as described below. did.
まず、第1図Cに示すように、・酸化シリコン膜5の上
にポリシリコン膜よりなるフローティングゲート電極6
を形成する必要があるが、本実施例では、できるだけ低
温で形成させるため、まずシラン(SiH4)とフォス
フイン(PH3)との混合ガスによる減圧気相成長法に
より、リンをドープ(約6 X 10”cm−3) し
たポリシリコン膜を600℃で約5000A形成させ、
その後900℃でリンの活性化を行った。その後、周知
のフォトエツチング技術により、ポリシリコン膜よりな
るフローティングゲート電極6を形威する。次いで、フ
ローティングゲート電極6の表面を酸化して酸化シリコ
ン膜7を形威するが、本実施例では950℃、アルゴン
希釈下のドライ酸素雰囲気で実施し、酸化シリコン膜7
の厚さはフローティングゲート電極6上で約50OAと
なるようにコントロールした。その後、シラン(SiH
4)とフォスフイン(P Hs)との混合ガスによる減
圧気相成長法により、リンをドープ(約6 ×10”c
m−’)したポリシリコン膜を600℃で約5000A
形成させ、その後900℃でリンの活性化を行った。つ
いで、周知のフォトエツチング技術により、ポリシリコ
ン膜よりなるコントロールゲート電極8を形成する。First, as shown in FIG. 1C, a floating gate electrode 6 made of a polysilicon film is placed on a silicon oxide film 5.
However, in this example, in order to form it at as low a temperature as possible, phosphorus was doped (approximately 6 x 10 "cm-3)" polysilicon film was formed at 600°C and approximately 5000A,
Thereafter, phosphorus was activated at 900°C. Thereafter, a floating gate electrode 6 made of a polysilicon film is formed using a well-known photoetching technique. Next, the surface of the floating gate electrode 6 is oxidized to form the silicon oxide film 7. In this embodiment, the silicon oxide film 7 is formed at 950° C. in a dry oxygen atmosphere diluted with argon.
The thickness was controlled to be about 50 OA on the floating gate electrode 6. Then, silane (SiH
4) and phosphine (PHs) by a low pressure vapor phase growth method using a mixed gas of
m-') polysilicon film at 600℃ and approximately 5000A.
After formation, phosphorus activation was performed at 900°C. Next, a control gate electrode 8 made of a polysilicon film is formed using a well-known photoetching technique.
次に、第1図りに示すように、シラン(SiH4)と酸
素との化学反応による常圧気相成長法により、酸化シリ
コン膜9を450℃で全面に被着後、ソース、ドレイン
の押し込みと、酸化シリコン膜9のち密化のために95
0℃、30分、窒素雰囲気中で熱処理を行った。その後
、酸化シリコン膜9を既知のフォトエツチング技術によ
りコンタクト孔を開孔し、アルミニウム電極10を形威
し、第1図りのごときフローティングゲート型の半導体
記憶装置を作製することができる。Next, as shown in the first diagram, a silicon oxide film 9 is deposited on the entire surface at 450°C by atmospheric pressure vapor phase growth using a chemical reaction between silane (SiH4) and oxygen, and then the source and drain are pressed in. 95 to make the silicon oxide film 9 denser.
Heat treatment was performed at 0° C. for 30 minutes in a nitrogen atmosphere. Thereafter, a contact hole is formed in the silicon oxide film 9 by a known photoetching technique, and an aluminum electrode 10 is formed to form a floating gate type semiconductor memory device as shown in the first diagram.
以上のごとくして得られたフローティングゲート型の半
導体記憶装置の繰り返し書換え特性の一例を第3図に示
す。縦軸は累積不良率、横軸は書換え回数である。第3
図に示すように、上述の実施例の製造方法により作製し
た半導体記憶装置の書換え特性(実線11〉は、従来の
半導体記憶装置の書換え特性(実線12)に比べ、書換
え特性が非常に優れていることがわかる。FIG. 3 shows an example of the repeated rewriting characteristics of the floating gate type semiconductor memory device obtained as described above. The vertical axis is the cumulative defective rate, and the horizontal axis is the number of rewrites. Third
As shown in the figure, the rewrite characteristics (solid line 11) of the semiconductor memory device manufactured by the manufacturing method of the above-described example are much better than the rewrite characteristics (solid line 12) of the conventional semiconductor memory device. I know that there is.
発明の詳細
な説明したところから明らかなように、本発明の製造方
法によれば、100A程度の非常に薄いトンネル媒体の
酸化シリコン膜に歪やトラップが発生することが少なく
なり、精度よく安定した書換え回数を確保することがで
き、フローティングゲート型の半導体記憶装置の高信頼
性化に大きく寄与するものである。As is clear from the detailed explanation of the invention, according to the manufacturing method of the present invention, distortion and traps are less likely to occur in the silicon oxide film of the tunnel medium, which is very thin at about 100A, and is stable with high precision. The number of rewrites can be ensured, and this greatly contributes to increasing the reliability of floating gate type semiconductor memory devices.
第1図は本発明の実施例の製造方法を説明するための工
程順断面図、第2図はフローティングゲート型の半導体
記憶装置の構造を説明するための断面図、第3図は本発
明の詳細な説明するための特性図である。
1・・・・・・P型シリコン基板、2・・・・・・ソー
ス領域、3・・・・・・ドレイン領域、4・・・・・・
酸化シリコン膜、5・・・・・・トンネル媒体となりう
る薄い酸化シリコン膜、6・・・・・・フローティング
ゲート電極、7・・・・・・酸化シリコン膜、8・・・
・・・コントロールゲート電極、9・・・・・・酸化シ
リコン膜、10・・・・・・アルミニウム電極。1 is a step-by-step sectional view for explaining the manufacturing method of an embodiment of the present invention, FIG. 2 is a sectional view for explaining the structure of a floating gate type semiconductor memory device, and FIG. 3 is a sectional view for explaining the structure of a floating gate type semiconductor memory device. It is a characteristic diagram for detailed explanation. 1... P-type silicon substrate, 2... Source region, 3... Drain region, 4...
Silicon oxide film, 5... Thin silicon oxide film that can serve as a tunnel medium, 6... Floating gate electrode, 7... Silicon oxide film, 8...
... Control gate electrode, 9 ... Silicon oxide film, 10 ... Aluminum electrode.
Claims (2)
型の拡散層を形成する工程と、前記半導体基板の表面上
に第1の絶縁膜を形成する工程と、前記第1の絶縁膜の
所定の部分に前記拡散層に達するような開孔部を形成す
る工程と、前記開孔部の拡散層表面上にトンネル媒体と
なりうる第2の絶縁膜を形成する工程と、前記第2の絶
縁膜上にフローティングゲート電極を形成する工程と、
前記フローティングゲート電極上に第3の絶縁膜を介し
てコントロールゲート電極を形成する工程を少なくとも
含む半導体記憶装置の製造方法において、上記第2の絶
縁膜の形成後の全ての熱処理工程が、上記第2の絶縁膜
の形成温度+50℃以下で行われることを特徴とする半
導体記憶装置の製造方法。(1) A step of forming a diffusion layer of a conductivity type opposite to that of the same substrate on the surface of a semiconductor substrate of one conductivity type, a step of forming a first insulating film on the surface of the semiconductor substrate, and a step of forming the first insulating film on the surface of the semiconductor substrate. forming an opening that reaches the diffusion layer in a predetermined portion of the film; forming a second insulating film that can serve as a tunnel medium on the surface of the diffusion layer in the opening; forming a floating gate electrode on the insulating film;
In the method for manufacturing a semiconductor memory device including at least the step of forming a control gate electrode on the floating gate electrode via a third insulating film, all the heat treatment steps after forming the second insulating film are A method for manufacturing a semiconductor memory device, characterized in that the process is carried out at a temperature lower than the temperature for forming an insulating film in step 2 +50°C.
ことを特徴とする請求項1記載の半導体記憶装置の製造
方法。(2) The method for manufacturing a semiconductor memory device according to claim 1, wherein the temperature at which the second insulating film is formed is 1050° C. or lower.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22633389A JPH0817210B2 (en) | 1989-08-31 | 1989-08-31 | Method for manufacturing semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22633389A JPH0817210B2 (en) | 1989-08-31 | 1989-08-31 | Method for manufacturing semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0389556A true JPH0389556A (en) | 1991-04-15 |
JPH0817210B2 JPH0817210B2 (en) | 1996-02-21 |
Family
ID=16843523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22633389A Expired - Lifetime JPH0817210B2 (en) | 1989-08-31 | 1989-08-31 | Method for manufacturing semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0817210B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04315476A (en) * | 1991-04-15 | 1992-11-06 | Nippondenso Co Ltd | Method of reducing trap density in oxide film and manufacture of nonvolatile memory cell using same |
-
1989
- 1989-08-31 JP JP22633389A patent/JPH0817210B2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04315476A (en) * | 1991-04-15 | 1992-11-06 | Nippondenso Co Ltd | Method of reducing trap density in oxide film and manufacture of nonvolatile memory cell using same |
Also Published As
Publication number | Publication date |
---|---|
JPH0817210B2 (en) | 1996-02-21 |
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