JPH0387057A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0387057A JPH0387057A JP22609589A JP22609589A JPH0387057A JP H0387057 A JPH0387057 A JP H0387057A JP 22609589 A JP22609589 A JP 22609589A JP 22609589 A JP22609589 A JP 22609589A JP H0387057 A JPH0387057 A JP H0387057A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- resistance layer
- contact holes
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に拡散抵抗層を有す
る半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a diffused resistance layer.
従来、リニア回路用マスタースライス方式の半導体集積
回路の抵抗は、シート抵抗の約５〜１０倍程度の抵抗値
の抵抗、例えば低抵抗用にシート抵抗１００Ω／口で５
００Ω〜ＩＫΩの拡散抵抗層と比較的高抵抗用にシート
抵抗２にΩ／口で１ＯＫΩ〜２０にΩの多結晶シリコン
抵抗層をアレイ状に並べるか又は１本の抵抗層に抵抗値
を可変するために抵抗層上に設けた絶縁膜にあらがしめ
複数のコンタクト孔を設けて抵抗層の長さをコンタクト
孔により選択できる抵抗層をアレイ状に構成している。Conventionally, the resistance of master slice type semiconductor integrated circuits for linear circuits has a resistance value of about 5 to 10 times the sheet resistance, for example, a sheet resistance of 100 Ω/unit for low resistance.
A diffused resistance layer of 00Ω to IKΩ and a polycrystalline silicon resistance layer of 1OKΩ to 20Ω are arranged in an array with a sheet resistance of 2Ω/unit for relatively high resistance, or the resistance value can be varied in one resistance layer. In order to achieve this, a plurality of contact holes are formed in the insulating film provided on the resistive layer, and the resistive layer is configured in an array in which the length of the resistive layer can be selected by the contact holes.
上述した従来の半導体集積回路は、回路上で所定の抵抗
値を実現するために、前者は複数本の抵抗を直並列に接
続する必要があり、回路上の抵抗の本数が制限されてい
た。In the conventional semiconductor integrated circuit described above, in order to achieve a predetermined resistance value on the circuit, it is necessary to connect a plurality of resistors in series and parallel, and the number of resistors on the circuit is limited.
また後者は１本の抵抗上にコンタクト孔が複数個設けら
れ、コンタクト孔を任意に選択して配線を接続すること
により、抵抗値を可変できるが、未使用コンタクト孔内
に抵抗層が露出している為、レイアウト上配線設計の自
由度が制約されていた。In the latter case, multiple contact holes are provided on one resistor, and the resistance value can be varied by arbitrarily selecting a contact hole and connecting wiring, but the resistance layer is exposed in an unused contact hole. Because of this, the degree of freedom in wiring design was restricted due to the layout.
本発明の半導体集積回路は、半導体基板の一主面に設け
た拡散抵抗層と、前記拡散抵抗層の表面に設けた絶縁膜
と、前記拡散抵抗層上の前記絶縁膜に設けた複数のコン
タクト孔と、前記コンタクト孔の前記拡散抵抗層と接続
する配線と、前記配線と接続した以外の前記コンタクト
孔を被覆して設けた層間絶縁膜とを備えている。The semiconductor integrated circuit of the present invention includes a diffused resistance layer provided on one main surface of a semiconductor substrate, an insulating film provided on the surface of the diffused resistance layer, and a plurality of contacts provided in the insulating film on the diffused resistance layer. The contact hole includes a hole, a wiring connected to the diffused resistance layer of the contact hole, and an interlayer insulating film provided to cover the contact holes other than those connected to the wiring.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例を示す平
面図及びＡ−Ａ’線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA', showing a first embodiment of the present invention.
半導体基板１の一主面に選択的に拡散抵抗層２を設け、
拡散抵抗層２を含む表面に窒化シリコンｌｌｌ３を設け
、窒化シリコン３の上に選択的に多結晶シリコン抵抗層
４を形成する。次に、拡散抵抗層２の上の窒化シリコン
膜３に配線接続用の複数のコンタクト穴５ａ、５ｂ、５
ｃ、５ｄを設ける。次に、抵抗層と接続しないコンタク
ト孔５ｂと５ｄを被覆する酸化シリコン膜７及び多結晶
シリコン抵抗層４の上の酸化シリコン膜６をそれぞれ選
択的に形成する。次に、アルミニウム配線９を選択的に
設けて、コンタクト孔５ａと５ｃと接続し、アルミニウ
ム配線１０を選択的に設けて多結晶シリコン抵抗層４の
両端に接続し、所望の抵抗値を実現している。ここでコ
ンタクト孔５ｂ。A diffused resistance layer 2 is selectively provided on one main surface of a semiconductor substrate 1,
Silicon nitride lll3 is provided on the surface including the diffused resistance layer 2, and a polycrystalline silicon resistance layer 4 is selectively formed on the silicon nitride 3. Next, a plurality of contact holes 5a, 5b, 5 for wiring connection are formed in the silicon nitride film 3 on the diffused resistance layer 2.
c, 5d are provided. Next, a silicon oxide film 7 covering contact holes 5b and 5d not connected to the resistance layer and a silicon oxide film 6 on the polycrystalline silicon resistance layer 4 are selectively formed. Next, aluminum wiring 9 is selectively provided and connected to contact holes 5a and 5c, and aluminum wiring 10 is selectively provided and connected to both ends of polycrystalline silicon resistance layer 4 to achieve a desired resistance value. ing. Here, contact hole 5b.
５ｄ上に設けた酸化シリコン膜７の上に配線１１を設け
ることができ配線の自由度が向上できる。The wiring 11 can be provided on the silicon oxide film 7 provided on the silicon oxide film 5d, and the degree of freedom in wiring can be improved.
第２図（ａ）、（ｂ）は本発明の第２の実施例を示す平
面図及びＢ−Ｂ’線断面図である。FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line BB', showing a second embodiment of the present invention.
拡散抵抗層２の上に設けた窒化シリコン膜３に拡散抵抗
層２より小さい拡散抵抗層２と相似の開孔部１２を設け
、開孔部１２を含む表面に酸化シリコン膜７を選択的に
形成してコンタクト孔５ａ、５ｄを設け、コンタクト孔
５ａ、５ｄで拡散抵抗層２と接続するアルミニウム配線
９を形成する。この実施例では酸化シリコン膜７の上に
配線１１を設けることができる。An opening 12 similar to the diffusion resistance layer 2 smaller than the diffusion resistance layer 2 is provided in the silicon nitride film 3 provided on the diffusion resistance layer 2, and a silicon oxide film 7 is selectively formed on the surface including the opening 12. Contact holes 5a and 5d are formed, and aluminum wiring 9 is formed to be connected to the diffused resistance layer 2 through the contact holes 5a and 5d. In this embodiment, the wiring 11 can be provided on the silicon oxide film 7.
以上説明したように本発明は、拡散抵抗層の上に設けた
絶縁膜に複数のコンタクト孔を設は所要の抵抗値に相当
するコンタクト孔に配線を接続し、配線を接続しないコ
ンタクト孔を層間絶縁膜により被覆することにより、被
覆した層間絶縁膜上に他の配線を形成できるため、配線
の自由度を向上させるという効果を有する。As explained above, the present invention provides a plurality of contact holes in an insulating film provided on a diffused resistance layer, connects a wiring to a contact hole corresponding to a required resistance value, and connects a contact hole to which no wiring is connected between layers. By covering with an insulating film, other wiring can be formed on the covered interlayer insulating film, which has the effect of improving the degree of freedom of wiring.
第１図（ａ）、（ｂ）は本発明の第１の実施例を示す平
面図及びＡ−Ａ’線断面図、第２図（ａ）、（ｂ）は本
発明の第２の実施例を示す平面図及びＢ−Ｂ’線断面図
である。
１・・・半導体基板、２・・・拡散抵抗層、３・・・窒
化シリコン膜、４・・・多結晶シリコン抵抗層、５ａ。
５ｂ、５ｃ、５ｄ・・・コンタクト孔、６，７・・・酸
化シリコン膜、９．１０．１１・・・配線、１２・・・
開孔部。FIGS. 1(a) and (b) are a plan view and a cross-sectional view taken along line A-A' showing a first embodiment of the present invention, and FIGS. 2(a) and (b) are a second embodiment of the present invention. It is a top view and a BB' line sectional view which show an example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Diffused resistance layer, 3... Silicon nitride film, 4... Polycrystalline silicon resistance layer, 5a. 5b, 5c, 5d... Contact hole, 6, 7... Silicon oxide film, 9.10.11... Wiring, 12...
Open hole.
Claims (1)
抗層の表面に設けた絶縁膜と、前記拡散抵抗層上の前記
絶縁膜に設けた複数のコンタクト孔と、前記コンタクト
孔の前記拡散抵抗層と接続する配線と、前記配線と接続
した以外の前記コンタクト孔を被覆して設けた層間絶縁
膜とを備えたことを特徴とする半導体集積回路。a diffused resistance layer provided on one main surface of the semiconductor substrate; an insulating film provided on the surface of the diffused resistance layer; a plurality of contact holes provided in the insulating film on the diffused resistance layer; 1. A semiconductor integrated circuit comprising a wiring connected to a diffused resistance layer and an interlayer insulating film provided to cover the contact holes other than those connected to the wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22609589A JPH0387057A (en) | 1989-08-30 | 1989-08-30 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22609589A JPH0387057A (en) | 1989-08-30 | 1989-08-30 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0387057A true JPH0387057A (en) | 1991-04-11 |
Family
ID=16839747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22609589A Pending JPH0387057A (en) | 1989-08-30 | 1989-08-30 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0387057A (en) |
-
1989
- 1989-08-30 JP JP22609589A patent/JPH0387057A/en active Pending
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