JPH043461A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH043461A JPH043461A JP10384890A JP10384890A JPH043461A JP H043461 A JPH043461 A JP H043461A JP 10384890 A JP10384890 A JP 10384890A JP 10384890 A JP10384890 A JP 10384890A JP H043461 A JPH043461 A JP H043461A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- semiconductor integrated
- resistance value
- integrated circuit
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000010586 diagram Methods 0.000 description 9
- 239000010409 thin film Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の抵抗素子に関し、特に面積抵
抗率の異なる抵抗体で形成される抵抗素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resistive element for a semiconductor integrated circuit, and more particularly to a resistive element formed of resistors having different sheet resistivities.
従来、半導体集積回路の抵抗素子は抵抗材料として薄膜
または拡散層を用いて構成される。薄膜抵抗は製造プロ
セスが簡単でコンタクトを介さず配線されている。また
、加工精度が良く、面積抵抗率が高いため高精度な高抵
抗値が得られる。Conventionally, a resistance element of a semiconductor integrated circuit is constructed using a thin film or a diffusion layer as a resistance material. Thin film resistors have a simple manufacturing process and are wired without using contacts. In addition, since the processing accuracy is good and the sheet resistivity is high, a highly accurate high resistance value can be obtained.
拡散抵抗に於いては、加工精度が悪い反面、面積抵抗率
が低いので、精度を必要としない所の低抵抗にはパター
ン設計上少ないチップ占有面積で良い。第1図は、従来
の薄膜抵抗を用いた半導体集積回路の抵抗素子を示す図
であって、製造プロセスのコンタクトを介さず配線2に
直接第1の抵抗体1(薄膜抵抗)が接続されている。Diffused resistors have poor processing accuracy but low sheet resistivity, so a small chip area is sufficient in pattern design for low resistance where precision is not required. FIG. 1 is a diagram showing a resistance element of a semiconductor integrated circuit using a conventional thin film resistor, in which a first resistor 1 (thin film resistor) is directly connected to a wiring 2 without using a contact in the manufacturing process. There is.
半導体集積回路のパターン設計では、抵抗値Rは抵抗長
p、抵抗幅W、および面積抵抗率ρSにより算出され、
次式で表される。In pattern design of semiconductor integrated circuits, resistance value R is calculated from resistance length p, resistance width W, and sheet resistivity ρS,
It is expressed by the following formula.
R=ρ、−・・・・・・(1)
(1)式から明らかなように、面積抵抗率ρSより小さ
な抵抗値Rを必要とする場合には抵抗幅Wを大きくする
必要があり、第1図に示すようなパターン設計となる。R = ρ, -... (1) As is clear from equation (1), if a resistance value R smaller than the sheet resistivity ρS is required, the resistance width W needs to be increased, The pattern design is as shown in FIG.
第2図は高い面積抵抗率ρs1をもつ前記第1の抵抗体
1の抵抗幅Wを小さくしながらも、低い面積抵抗率ρ、
2をもつ第2の抵抗体3(拡散抵抗)を前記第1の抵抗
体1と並列に接続し、合成抵抗値Rを小さくした従来例
を示す図である。FIG. 2 shows that while the resistance width W of the first resistor 1 having a high sheet resistivity ρs1 is reduced, the sheet resistivity ρ is low.
2 is a diagram showing a conventional example in which a second resistor 3 (diffused resistor) having a resistor 2 is connected in parallel with the first resistor 1 to reduce the combined resistance value R. FIG.
第3図は第2図の等価回路図である。ここで前記第1の
抵抗体1の抵抗値をR1、前記第2の抵抗体3の抵抗値
をR2とすると、−船釣にR+>R2であるから、所望
の抵抗値Rは
R,>R2>R・・・・・(2)
という大小関係で得られる。FIG. 3 is an equivalent circuit diagram of FIG. 2. Here, if the resistance value of the first resistor 1 is R1, and the resistance value of the second resistor 3 is R2, then R+>R2 for boat fishing, so the desired resistance value R is R,>R2>R...(2) Obtained from the magnitude relationship.
上述した従来の抵抗素子は、前記第1の抵抗体1だけを
用いた場合、面積抵抗率ρ31が高いので、精度の良い
低抵抗値を得るには抵抗幅Wが大きくなりパターン設計
上かなりのスペースを要する。In the conventional resistance element described above, when only the first resistor 1 is used, the area resistivity ρ31 is high, so in order to obtain a low resistance value with high accuracy, the resistance width W becomes large, which causes considerable problems in pattern design. Requires space.
更に、前記第1の抵抗体1と前記第2の抵抗体3を並列
に接続して合成抵抗値Rを小さくした場合にもパターン
設計上更にスペースを要するという欠点がある。Furthermore, even when the first resistor 1 and the second resistor 3 are connected in parallel to reduce the combined resistance value R, there is a drawback that more space is required in terms of pattern design.
本発明は、高い面積抵抗率をもつ高精度抵抗体ヲ用い、
パターン設計上チップ占有面積を少なくでき、更に前記
高精度抵抗体から所望の分圧を取り出すことができる半
導体集積回路の抵抗素子を提供する。The present invention uses a high-precision resistor with high sheet resistivity,
Provided is a resistive element for a semiconductor integrated circuit, which can reduce the area occupied by a chip in terms of pattern design, and can extract a desired partial voltage from the high-precision resistor.
本発明の半導体集積回路の抵抗素子は、精度は良いが高
い面積抵抗率ρs1をもつ前記第1の抵抗体1と、低い
面積抵抗率ρs2をもつ前記第2の抵抗体3が並列接続
され、かつ、前記第1の抵抗体1が前記第2の抵抗体3
の上に配置された構造を有している。In the resistor element of the semiconductor integrated circuit of the present invention, the first resistor 1 having good precision but a high sheet resistivity ρs1 and the second resistor 3 having a low sheet resistivity ρs2 are connected in parallel, and the first resistor 1 is the second resistor 3
It has a structure placed on top of it.
第4図は本発明の一実施例を示す。前記第1の抵抗体1
の一端が前記第2の抵抗体3の一端と配線2で接続され
、前記第1の抵抗体1の他端は前記第2の抵抗体3の他
端と配線2て接続され前記第1の抵抗体lと前記第2の
抵抗体3は並列接続された抵抗体を形成する。更に、前
記第1の抵抗体1は前記第2の抵抗体3の上に平行に配
置された構造を有する。FIG. 4 shows an embodiment of the present invention. Said first resistor 1
One end of the first resistor 1 is connected to one end of the second resistor 3 by a wire 2, and the other end of the first resistor 1 is connected to the other end of the second resistor 3 by a wire 2. The resistor l and the second resistor 3 form a resistor connected in parallel. Furthermore, the first resistor 1 has a structure arranged above the second resistor 3 in parallel.
また、前記第2の抵抗体3上に配置された前記第1の抵
抗体1を配線2を用いて分割することVこより、高精度
の抵抗値を有する前記第1の抵抗体1から所望の分圧を
取り出すことができる。第5図は第4図の等価回路図で
ある。Further, by dividing the first resistor 1 disposed on the second resistor 3 using the wiring 2, a desired value can be obtained from the first resistor 1 having a highly accurate resistance value. Partial pressure can be taken out. FIG. 5 is an equivalent circuit diagram of FIG. 4.
以上説明したように本発明は、精度が良く、高い面積抵
抗率ρs1をもつ前記第1の抵抗体1を低い面積抵抗率
ρ、2をもつ前記第2の抵抗体3上に並列接続すること
により高精度の低抵抗値を得られると共にパターン設計
上チップ占有面積を少なくすることができる。As explained above, the present invention has good accuracy and connects the first resistor 1 having a high sheet resistivity ρs1 in parallel on the second resistor 3 having a low sheet resistivity ρ, 2. As a result, a highly accurate low resistance value can be obtained, and the area occupied by the chip can be reduced in terms of pattern design.
更に高精度抵抗体を配線2で分割することにより所望の
分圧を得ることができる。Further, by dividing the high-precision resistor by the wiring 2, a desired partial voltage can be obtained.
又、第1の抵抗体1に薄膜抵抗を使えば、レーザトリミ
ング等による精度の追いつめが可能で有り、さらに高精
度の抵抗値が得られるという効果も有る。Further, if a thin film resistor is used as the first resistor 1, it is possible to improve the accuracy by laser trimming or the like, and there is also the effect that a highly accurate resistance value can be obtained.
素子を示す図、第3図は第2図抵抗素子の等価回路図、
第4図は本発明による実施例を示す図、第5図は第4図
抵抗素子の等価回路図である。A diagram showing the element, Figure 3 is an equivalent circuit diagram of the resistor element in Figure 2,
FIG. 4 is a diagram showing an embodiment according to the present invention, and FIG. 5 is an equivalent circuit diagram of the resistor element shown in FIG. 4.
■・・・・・・第1の抵抗体、2・・・・・配線、3・
・・・・・第2の抵抗体。■...First resistor, 2...Wiring, 3.
...Second resistor.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
第1図、第2図は従来の半導体集積回路の抵抗第1図 第3図 第4図 第2図 第5図 Figures 1 and 2 are resistance diagrams of conventional semiconductor integrated circuits. Figure 3 Figure 4 Figure 2 Figure 5
Claims (1)
抵抗率の異なる第1の抵抗体と第2の抵抗体を並列に接
続し、かつ、前記第1の抵抗体は前記第2の抵抗体の上
に重ねた構造を有する半導体集積回路の抵抗素子。In a resistance element arranged in a semiconductor integrated circuit, a first resistor and a second resistor having different sheet resistivities are connected in parallel, and the first resistor is connected to the second resistor. A resistor element for a semiconductor integrated circuit that has a structure overlaid on a semiconductor integrated circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10384890A JPH043461A (en) | 1990-04-19 | 1990-04-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10384890A JPH043461A (en) | 1990-04-19 | 1990-04-19 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH043461A true JPH043461A (en) | 1992-01-08 |
Family
ID=14364863
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10384890A Pending JPH043461A (en) | 1990-04-19 | 1990-04-19 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH043461A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017079321A (en) * | 2015-10-19 | 2017-04-27 | 株式会社東芝 | Semiconductor device |
-
1990
- 1990-04-19 JP JP10384890A patent/JPH043461A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017079321A (en) * | 2015-10-19 | 2017-04-27 | 株式会社東芝 | Semiconductor device |
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