JPH0384930A - Formation of protective film - Google Patents
Formation of protective filmInfo
- Publication number
- JPH0384930A JPH0384930A JP1222189A JP22218989A JPH0384930A JP H0384930 A JPH0384930 A JP H0384930A JP 1222189 A JP1222189 A JP 1222189A JP 22218989 A JP22218989 A JP 22218989A JP H0384930 A JPH0384930 A JP H0384930A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resin layer
- protective film
- opening
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title claims abstract description 21
- 230000015572 biosynthetic process Effects 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 26
- 229920005989 resin Polymers 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 15
- 229920001721 polyimide Polymers 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 239000004642 Polyimide Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000009719 polyimide resin Substances 0.000 description 6
- 238000005755 formation reaction Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 229910052500 inorganic mineral Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011707 mineral Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体素子の形成された基板の上に設けら
れる保護膜の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a protective film provided on a substrate on which a semiconductor element is formed.
半導体装置では、通常、第３図（ｄｌにみるように、半
導体素子に必要な各領域が作り込まれ表面に絶縁（酸化
）層５２やＡＩ（アル主ニウム）等の電極用金属層５３
が形成された半導体基板（基板）５１を得た後、同半導
体基板５１表面にＣＶＤ酸化層（例えば、Ｓｉ０ｇ膜）
５４上にポリイミド系樹脂層５５が積層された２重構造
であってワイヤボンディングのための窓５７が明けられ
た保護膜５６を設ける。このワイヤボンディング窓５７
を通して金属層５３にワイヤ（図示省略）がボンディン
グ接続される。In a semiconductor device, normally, as shown in FIG.
After obtaining the semiconductor substrate (substrate) 51 on which is formed, a CVD oxide layer (for example, Si0g film) is formed on the surface of the semiconductor substrate 51.
A protective film 56 having a double structure with a polyimide resin layer 55 laminated thereon and having a window 57 for wire bonding is provided on the protective film 54 . This wire bonding window 57
A wire (not shown) is connected to the metal layer 53 through bonding.
保護膜５６は、従来、以下のようにして形成されている
。The protective film 56 is conventionally formed as follows.
まず、第３図（ａ）にみるように、ＣＶＤ法によりＣＶ
Ｄ酸化層（無機質層）５４を堆積させた後、第３図（ｂ
）にみるように、フォトリソグラフィ技術を利用して、
同酸化層５４にボンディング窓用開口５７′を明ける。First, as shown in Figure 3(a), CVD is performed using the CVD method.
After depositing the D oxide layer (inorganic layer) 54, FIG.
), using photolithography technology,
A bonding window opening 57' is formed in the oxide layer 54.
ついで、第３図（Ｃ）にみるように、ポリイミド系樹脂
層５５を積層した後、フォトリソグラフィ技術を利用し
て、同樹脂層５５にボンディング窓用開口を明ければ、
ワイヤボンディング窓５７のある保護膜５６が完成する
こととなる。Next, as shown in FIG. 3(C), after laminating a polyimide resin layer 55, an opening for a bonding window is formed in the resin layer 55 using photolithography.
A protective film 56 with a wire bonding window 57 is completed.
しかしながら、従来の２重構造の保護１！１５６形戒方
法は、第３図（ｂ）、（ｄ）の２回のフォトリソグラフ
ィ工程があり、マスク形成が２回必要であるため、コス
トや歩留まりの点で問題がある。However, the conventional double structure protection 1!156 type method requires two photolithography steps as shown in FIG. There is a problem with this.
また、半導体素子が高耐圧ブレーナ型半導体素子の場合
、通常、半導体基板５１裏面に高電位電極を設ける。一
方、第３図（ｄ）の工程終了後の半導体基板５１裏面に
は、ポリイミド系樹脂７１５５のエンチング液では除去
されない薄い自然酸化膜が残っている。このような酸化
膜が半導体基板５１裏面に残っていると、裏面電極のコ
ンタクト抵抗の増加、電極と半導体基板の接合不良、あ
るいは、熱抵抗の増加といった不都合がある。そのため
、高耐圧ブレーナ型半導体素子の場合、十分な性能を確
保するには、半導体基板５１裏面の残存酸化膜を除去す
るエツチング工程が余分に必要となる。Further, when the semiconductor element is a high-voltage Brenna type semiconductor element, a high potential electrode is usually provided on the back surface of the semiconductor substrate 51. On the other hand, on the back surface of the semiconductor substrate 51 after the process shown in FIG. 3(d) is completed, a thin natural oxide film that cannot be removed by the etching solution of the polyimide resin 7155 remains. If such an oxide film remains on the back surface of the semiconductor substrate 51, there are disadvantages such as increased contact resistance of the back electrode, poor bonding between the electrode and the semiconductor substrate, or increased thermal resistance. Therefore, in the case of a high breakdown voltage Brainer type semiconductor element, an extra etching step is required to remove the remaining oxide film on the back surface of the semiconductor substrate 51 in order to ensure sufficient performance.
この発明は、上記事情に鑑み、マスク形成回数が少なく
、基板裏面の酸化膜が保護膜完成時点では残らないよう
に保護膜を形成することができる方法を提供することを
課題とする。In view of the above-mentioned circumstances, it is an object of the present invention to provide a method that can form a protective film so that the number of mask formations is small and no oxide film remains on the back surface of the substrate when the protective film is completed.
前記課題を解決するため、第１図（Ｃ１にみるように、
無機質Ｍ（例えば、ＣＶＤ＠化層）４上に樹脂層（例え
ば、ポリイミド系樹脂層）５が積層された２重構造であ
ってワイヤボンディング窓７が明けられている保護膜６
を、半導体素子の形成された基板（例えば、シリコン半
導体基板）１表面に設けるにあたり、この発明では、第
１図山）にみるように、表面に無機質層４と樹脂ｒｆｉ
５が積層され同樹脂層５には前記窓用開口１０が明けら
れている前記基板１を用い、この樹脂層５をマスクにし
て、下の無機質層４に前記窓用開口１１をエツチングに
より明けるようにしている。In order to solve the above problem, as shown in Figure 1 (C1),
A protective film 6 having a double structure in which a resin layer (for example, a polyimide resin layer) 5 is laminated on an inorganic material M (for example, a CVD layer) 4, and a wire bonding window 7 is opened therein.
As shown in FIG.
5 is laminated and the window opening 10 is formed in the resin layer 5. Using the resin layer 5 as a mask, the window opening 11 is formed in the underlying inorganic layer 4 by etching. That's what I do.
無機質層４としては５ｉｎｓからなるＣＶＤ酸化層が例
示され、樹脂層５にはポリイミド系樹脂層が例示される
のであるが、これらに限らず、無機質層４や樹脂１５が
他の無機物質や無機質層のエンチング液に侵されない樹
脂からなるようであってもよい。Examples of the inorganic layer 4 include a CVD oxidized layer of 5ins, and examples of the resin layer 5 include a polyimide resin layer; however, the inorganic layer 4 and the resin 15 may be made of other inorganic substances or minerals. The layer may be made of a resin that is not attacked by the etching liquid.
基板１に形威される半導体素子としては、例えば、基板
裏面に電極を設ける縦型の高耐圧ブレーナ型半導体素子
が挙げられる。この縦型高耐圧ブレーナ型半導体素子の
具体的なものには、サイリスク、トランジスタ、ダイオ
ード、ＩＧＢＴ、パワーＭＯＳ等が例示されるが、基板
に形威される半導体素子はこれらに限らない。Examples of the semiconductor element formed on the substrate 1 include a vertical high-voltage Brenna type semiconductor element in which electrodes are provided on the back surface of the substrate. Specific examples of this vertical high-voltage brainer type semiconductor device include a SIRISK, a transistor, a diode, an IGBT, a power MOS, etc., but the semiconductor device formed on the substrate is not limited to these.
この発明の保護膜の形成方法では、無機質層のエツチン
グ前に樹脂層を形威し、樹脂層の方だけにワイヤボンデ
ィング窓用開口を先に明ける。そして、このワイヤボン
ディング窓用開口の明いた樹脂層をマスクに使い、下の
無機質層にボンディング窓用開口をエツチングにより形
成する。したがって、困難なマスク形成が樹脂層の開口
工程で必要なだけで、無機質層の開口工程では不要であ
る。しかも、樹脂層の開口と無機質層の開口は互いにず
れることなく、ぴったりと一致する。そのため、製造コ
スト低減や歩留まり向上が可能となる。In the method for forming a protective film of the present invention, the resin layer is shaped before etching the inorganic layer, and openings for wire bonding windows are first opened only in the resin layer. Then, using this resin layer with the wire bonding window opening as a mask, the bonding window opening is formed in the underlying inorganic layer by etching. Therefore, difficult mask formation is only necessary in the step of opening the resin layer, but not in the step of opening the inorganic layer. Furthermore, the openings in the resin layer and the openings in the inorganic layer do not shift from each other and match exactly. Therefore, it is possible to reduce manufacturing costs and improve yield.
無機質層（例えば、ＣＶ Ｄ ５ｉｎｓ層）エツチング
では、同じ無機質である基板裏面の自然酸化膜（ｓｔｏ
霊１１１）が同時にエツチング除去され、保護膜の完成
時点で既に残存していない。そのため、高耐圧ブレーナ
型半導体素子で基板裏面に電極を設ける場合でも、改め
て自然酸化膜を除去するエツチング工程が要らない。When etching an inorganic layer (for example, a CVD 5ins layer), a natural oxide film (sto
111) is removed by etching at the same time, and no longer remains when the protective film is completed. Therefore, even when an electrode is provided on the back surface of the substrate in a high-voltage Brenna type semiconductor element, there is no need for an additional etching process to remove the natural oxide film.
続いて、この発明の具体的な実施例を、図面を参照しな
がら詳しく説明する。Next, specific embodiments of the present invention will be described in detail with reference to the drawings.
第１図（ａｌ〜（Ｃ）は、この発明にかかる方法の一例
による保護膜形成の様子を工程順にあられす。FIGS. 1A to 1C show the formation of a protective film according to an example of the method according to the present invention in the order of steps.
第１図（ａｌにみるように、半導体素子に必要な各領域
が作り込まれ表面に絶縁（酸化）層２やＡｇ（アルミニ
ウム）等の電極用金属層３が形成された半導体基板（基
板）ｌの上に、ＣＶＤ法を用いＣＶＤ酸化層（例えば、
Ｓｉ０目臭）４を堆積させ、続いて、ポリイミド系樹脂
層５を積層する。As shown in Figure 1 (al), a semiconductor substrate (substrate) in which various regions necessary for a semiconductor element are formed and an insulating (oxidized) layer 2 and an electrode metal layer 3 such as Ag (aluminum) are formed on the surface. A CVD oxide layer (e.g.
After that, a polyimide resin layer 5 is laminated.
つぎに、フォトリソグラフィ法を用いマスクを樹脂層５
の上に設はエツチング処理することにより、第１図（ｂ
ｌにみるように、樹脂層５にワイヤボンディング窓用開
口１０を明ける。Next, a mask is formed on the resin layer 5 using a photolithography method.
By performing an etching process on top of the
As shown in FIG. 1, an opening 10 for a wire bonding window is formed in the resin layer 5.
続いて、開口１０を明けた樹脂Ｎ５をマスクとして、Ｃ
ＶＤ酸化層４にワイヤボンディング窓用開口１１を明け
れば、開口１０．１１からなるワイヤボンディング窓７
のある保護１！！！６が完成することになる。Next, using the resin N5 with the opening 10 as a mask, C
If a wire bonding window opening 11 is formed in the VD oxide layer 4, a wire bonding window 7 consisting of the opening 10.11 is formed.
Protection 1! ! ! 6 will be completed.
ＣＶＤ酸化層４のエツチングの際には、フン酸（ＨＦ）
と適当な緩衝剤（例えば、フン化アンモニウム）を含む
エツチング液（バッファードフソ酸液と呼ばれたりもす
る）を用いている。この液を用いると、ＣＶＤ酸化層４
とポリイミド系４Ｍ脂層５の接着信頼性を損なう（例え
ば、剥離等）ことなく、ＣＶＤ酸化層４および半導体基
板１裏面の自然酸化膜のエツチング除去が行えるのであ
るなお、第２図は、半導体素子として縦型静電誘導サイ
リスタが形成された半導体基板ｌにＣＶＤ酸化層４上に
ボリイくド系樹脂層５が積層された二重構造の保護膜６
が設けられてなる半導体装置の端の部分をあられす。When etching the CVD oxide layer 4, use hydronic acid (HF).
An etching solution (sometimes called a buffered fluoride solution) containing a suitable buffer (for example, ammonium fluoride) is used. When this solution is used, the CVD oxide layer 4
The CVD oxide layer 4 and the natural oxide film on the back surface of the semiconductor substrate 1 can be removed by etching without impairing the adhesion reliability of the polyimide 4M resin layer 5 (for example, peeling). A double-structured protective film 6 in which a boiled resin layer 5 is laminated on a CVD oxide layer 4 on a semiconductor substrate l on which a vertical electrostatic induction thyristor is formed as an element.
The end portion of the semiconductor device is covered with rain.
半導体基板１では、カソード領域（Ｎ”層）やゲート領
域ＣＰ”層〉は図示外の基板中央表面部分に形成され、
アノード領域（Ｐ”１）ｌｂは基板裏面に形成されてい
る。カソード・アノード間のＮ−層１ａは高比抵抗領域
（ベース領域）である、１０層ＩＣ・・・は基板中央の
活性領域を囲むように形成されたガードリング領域であ
る。In the semiconductor substrate 1, a cathode region (N" layer) and a gate region CP" layer are formed in a central surface portion of the substrate (not shown),
The anode region (P"1) lb is formed on the back surface of the substrate. The N- layer 1a between the cathode and anode is a high resistivity region (base region). The 10-layer IC... is an active region in the center of the substrate. This is a guard ring area formed to surround the.
保護ｌ１ｌＩ６におけるワイヤボンディング窓７はカソ
ード電極層ＡＩ！金属層３のボンディング用域に明けら
れた後、ワイヤがボンディングされることはいうまでも
ない。勿論、ゲート電極用Ａ／金属層のボンディング域
にもワイヤボンディング窓が同時に明けられることもい
うまでもない。The wire bonding window 7 in the protection l1lI6 is connected to the cathode electrode layer AI! It goes without saying that the wire is bonded after the bonding area of the metal layer 3 has been opened. Of course, it goes without saying that a wire bonding window is also opened in the bonding area of the gate electrode A/metal layer at the same time.
この半導体装置では、アノード電極９の設けられる半導
体基板１裏面には自然酸化膜がないため、電極９のコン
タクト抵抗増加や接合不良の問題、さらには熱抵抗増大
が解消されている。In this semiconductor device, since there is no native oxide film on the back surface of the semiconductor substrate 1 on which the anode electrode 9 is provided, the problems of increased contact resistance and poor bonding of the electrode 9, as well as increased thermal resistance, are solved.
以上に述べたように、この発明にかかる保護膜の形成方
法では、マスク形成回数が少なくなるため、製造コスト
低減や歩留まり向上ができるようになり、しかも、基板
裏面の酸化膜が保護膜完成時点では残らないため、高信
頼・高性能の高耐圧ブレーナ型半導体素子のある半導体
装置の製造工程が簡略化できる。As described above, in the method for forming a protective film according to the present invention, the number of times of mask formation is reduced, making it possible to reduce manufacturing costs and improve yield. Therefore, the manufacturing process of a semiconductor device having a highly reliable and high performance high breakdown voltage brainer type semiconductor element can be simplified.
【図面の簡単な説明】
第１図は、この発明の方法の一例による保護膜形成の様
子を工程順にあられす概略断面図、第２図は、この発明
により形成された保護膜を備える半導体装置の一部端部
分をあられす概略断面図、第３図は、従来の方法による
保護膜形成の様子を工程順にあられす概略断面図である
。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a schematic cross-sectional view showing the process of forming a protective film according to an example of the method of the present invention, and FIG. 2 is a semiconductor device equipped with a protective film formed according to the present invention. FIG. 3 is a schematic cross-sectional view showing the process of forming a protective film by a conventional method.
Claims (1)
ワイヤボンディング窓が明けられている保護膜を、半導
体素子の形成された基板表面に設けるにあたり、表面に
前記無機質層と樹脂層が積層され同樹脂層には前記窓用
開口が明けられている前記基板を用い、この樹脂層をマ
スクにして、下の無機質層に前記窓用開口をエッチング
により明けるようにすることを特徴とする保護膜の形成
方法。1. When providing a protective film with a double structure in which a resin layer is laminated on an inorganic layer and a wire bonding window is opened on the surface of a substrate on which a semiconductor element is formed, the inorganic layer and resin layer are layered on the surface. The substrate is laminated and the resin layer has the window opening, and the window opening is etched into the underlying inorganic layer using the resin layer as a mask. How to form a protective film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1222189A JPH0384930A (en) | 1989-08-28 | 1989-08-28 | Formation of protective film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1222189A JPH0384930A (en) | 1989-08-28 | 1989-08-28 | Formation of protective film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0384930A true JPH0384930A (en) | 1991-04-10 |
Family
ID=16778550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1222189A Pending JPH0384930A (en) | 1989-08-28 | 1989-08-28 | Formation of protective film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0384930A (en) |
-
1989
- 1989-08-28 JP JP1222189A patent/JPH0384930A/en active Pending
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