JPH038374A - Electrostatic induction transistor - Google Patents

Abstract

PURPOSE:To prevent deterioration in breakdown strength and breakdown of an element by making the breadth of a gate to be formed at an utmost end of a drain layer longer than the breadth of the other gate while forming a semiconductor region having high impurity concentration at a part directly under the utmost end part. CONSTITUTION:The horizontal length W2 of a P<+> type gate region 31 to be provided on the peripheral part of an element is made longer than a p<+> type gate region 13. Then, an n<+> type drain region 32 having higher impurity concentration than that of an n<-> type epitaxial layer 12' is provided on a part of the part positioned directly under the region 31 of the peripheral part on an n<-> type substrate. Thereby, when reversed bias voltage is applied between the drain - the gate, a primary avalanche yield is generated in the junction part of the region 31 and a layer 12' before the avalanche yield is generated in the junction part of the region 13 and the epitaxial layer 12'. Subsequently, a secondary avalanche yield is generated in the interface part of the layer 12' and the region 32, but positive holes due thereto do not flow into an n<+> type source region 14. Accordingly, deterioration in breakdown strength and damage of the element can be prevented.

Description

[Detailed Description of the Invention] [Summary] The width of the gate of the second conductivity type formed at the end of the first conductivity type drain layer on the full surface side is determined from the width of other gates of the second conductivity type. and forming a predetermined layer of the first conductive type semiconductor region on a part of the long-width end portion of the first conductive type semiconductor substrate located directly under the second conductive type gate. By forming the semiconductor substrate with a large thickness, secondary avalanche breakdown when a reverse bias voltage is applied between the gate and the drain can be avoided. The generation is limited to the interface between the first conductivity type semiconductor region and the first conductivity type drain layer. As a result, even if a reverse bias voltage higher than the withstand voltage is applied between the gate and drain, the hot carriers generated due to the secondary avalanche breakdown are
This prevents the inflow into the source region of the conductivity type, and it is possible to prevent deterioration of the breakdown voltage of the device and further prevent destruction of the device when a reverse bias voltage higher than the breakdown voltage is applied between the gate and drain.

[Industrial application field]

The present invention provides a static induction transistor (StaticIn
The present invention relates to a static induction transistor (transistor), and particularly to a static induction transistor capable of preventing deterioration of the breakdown voltage of the device and prevention of destruction of the device even when a reverse bias voltage higher than the breakdown voltage is applied between the gate and drain.

[Conventional technology]

Static induction transistors (hereinafter abbreviated as SIT) can easily be made into multi-channels by having a vertical structure, so they can handle large currents.
By inserting a high resistance layer between the drains, the gate
Since it is possible to make the breakdown voltage between the drains high, it is suitable for high power applications.

FIG. 4 is a sectional view showing the structure of a conventional 5ITIO.

In the figure, an n-type substrate 11 made of Si or the like has an n
- type epitaxial layer 12 is formed, and its n- type epitaxial layer 12 is formed.
A p゛ type gate region 13□ 13,13.13゜ and an n+ type source region 1 are provided on the whole surface side of the type epitaxial layer 12.
4, 14.14 is formed. Also, the p' type gate 6M region 13. The n° type source region 14 is the n° type source region 14.
Gate electrodes 16 . each made of A1 etc. are formed through contact holes formed by partially etching the oxide film 15 formed on the entire surface of the - type epitaxial layer 12 . It is connected to the source electrode 17. Also, n
A drain electrode 18 made of A1 or the like is formed on the other main surface of the square substrate 11 .

In the above configuration, n in the n'' type epitaxial N12
Below the ゛ type source region 14 and the P ゛ type gate region 1
The region sandwiched between 3 and 13 serves as a channel region 19, and the n-type epitaxial layer 12 and n°-type substrate layer 1 serve as a drain region.

The 5ITIO having the above configuration is a normally-off type SIT, and when a forward bias voltage higher than a predetermined voltage value is not applied between the gate electrode 16 and the source electrode 17, the channel region 19 is entirely depleted. Source -
No current flows between the drains.

Next, FIGS. 5(a) and 5(b) show the gate electrode CG when measuring the drain-source breakdown voltage (BVD-) and drain-gate breakdown voltage (BVDGO), respectively.
16. Source electrode (S) 17 and drain electrode (D
) is a diagram showing a method of applying voltage to 1B.

When measuring the drain-source breakdown voltage (BVo=-), as shown in FIG.
and a reverse bias voltage V is applied to the drain electrode.

Further, when measuring the drain-gate breakdown voltage (BV, . . . ), a reverse bias voltage 1 is applied between the gate electrode 16 and the drain electrode 18.

In this way, the drain-source breakdown voltage (B Vo-,
).

In any measurement of the drain-gate breakdown voltage (BV, Go), the gate-drain is reverse biased. Therefore, when measuring both the drain-source breakdown voltage (BVoss) and the drain-gate breakdown voltage (BVOGO), the junction between the p-type gate region 13 and the n-type epitaxial layer (drain layer) 12 is reverse biased. Because
A wide depletion region 21 is formed on both sides of the junction surface between the two regions, particularly in the n-type epitaxial layer 12 with a low impurity concentration (see FIG. 4). When the reverse bias voltage (2) is further increased, the depletion region 21 reaches the interface between the n- type epitaxial layer 12 and the n+-type substrate 11, as shown in FIG. Then, in the depletion region 21, the electric field E at the junction surface between the p' type gate region 13 and the n- type epitaxial layer 12 to which the maximum electric field E□8 is applied is a critical electric field Ec that causes avalanche breakdown.
rit, a first-order avalanche breakdown occurs at the junction between the p-type gate region 13 and the n-type epitaxial layer N12, and electrons are avalanche-like in the depletion region 21.
Hole pairs come to be generated (in FIG. 5, the generated electrons are shown by black circles, and the correct cards are shown by white circles). and,
The electron, which is one carrier of the generated electron/genuine tag pair, is accelerated by the electric field within the depletion region 21, and its kinetic energy increases (becomes a hot electron), causing the formation of an n-type epitaxial layer with many crystal defects. 12 and n
Secondary avalanche breakdown occurs at the interface of the ゛-type substrate 11. This n-type epitaxial layer 12 and n.

Of the electron-hole pairs generated at the interface of the type substrate 11, the electrons are accelerated by the electric field in the depletion region 21, become so-called hot electrons, and travel to the n-type substrate 11. The electric field of Inflow.

[Problem to be solved by the invention]

As described above, when the holes generated due to the second avalanche breakdown flow into the channel region 19 and the n-type source region 14 as real holes, the breakdown voltage characteristics of the device deteriorate and even the device may be destroyed. It may lead to Fifth
Drain-source breakdown voltage BVo as shown in figure (a)
- When measuring -, the presence of holes flowing into the n'-type source region 14 can be observed as a source current I.

The above element breakdown occurs when the holes (hot holes) generated by the second avalanche breakdown flow into the n° type source region 14, and the energy obtained by the electric field in the depletion region 21 is transferred to the n° type source region 14. It is predicted that this occurs due to heat being released at the interface between the source region 14 and the n-type epitaxial layer 12.

In the present invention, even if avalanche breakdown occurs in the drain layer when a reverse bias voltage higher than the withstand voltage is applied between the drain and gate, carriers generated by the avalanche breakdown flow into the channel region and the source region. not,
Therefore, it is an object of the present invention to provide a static induction transistor (SIT) that does not cause deterioration in breakdown voltage or breakdown of the device.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a semiconductor substrate of a first conductivity type, and a semiconductor substrate of the first conductivity type formed on one main surface side of the semiconductor substrate of the first conductivity type, which has a lower conductivity than the semiconductor substrate. a first semiconductor region having an impurity concentration; and a first semiconductor region formed near one main surface of the first semiconductor region.
at least one second semiconductor region of a conductive type and having a high impurity concentration, formed in the vicinity of the second semiconductor region near one principal surface of the first semiconductor region and separated from the second semiconductor region by a predetermined distance; In the static induction transistor comprising a third semiconductor region of a second conductivity type, the width of the third semiconductor region formed at the extreme end near one main surface of the first semiconductor region is , which is longer than the other third semiconductor regions by a predetermined length, and is located directly below the third semiconductor region on one main surface of the first conductivity type semiconductor substrate. , the fourth semiconductor region of the first conductivity type and high impurity concentration is formed to have a predetermined thickness.

The fourth semiconductor region of the first conductivity type is, for example, as claimed in claim 2.
As described, the inner end of the element is formed a predetermined distance away from the region immediately below the second semiconductor region of the first conductivity type.

[For production]

In the present invention, the width of the third semiconductor region of the second conductivity type, which becomes the gate, is formed at the end of the first surface side of the first semiconductor region of the first conductivity type, which becomes the drain layer. The first semiconductor region is longer than the width of the third semiconductor region of the second conductivity type, and is located directly below the third semiconductor region on one main surface of the first conductivity type semiconductor substrate. Since the fourth semiconductor region of the first conductivity type, which has a higher impurity concentration than the first semiconductor region, is formed with a predetermined thickness, when a reverse bias voltage is applied between the drain and the gate, The formed depletion layer region reaches the interface between the first semiconductor region and the fourth semiconductor region earlier than the interface between the first semiconductor region and the semiconductor substrate.

Then, when the reverse bias voltage applied between the drain and the gate is further increased, the depletion layer region further spreads inside the first semiconductor region and the fourth semiconductor region, but Since the impurity concentration is higher than that of the first semiconductor region, the junction between the third semiconductor region, which is the gate at the extreme end above the fourth semiconductor region, and the first semiconductor region is , the critical electric field at which avalanche breakdown occurs is reached earlier than at the junction between the third semiconductor region, which is another gate, and the first semiconductor region.

When avalanche breakdown occurs at the junction between the third semiconductor region at the extreme end and the first semiconductor region due to the critical electric field, hot carriers generated by the avalanche breakdown are transferred to the junction by the electric field in the depletion layer region. It reaches the interface between the fourth semiconductor region and the first semiconductor region, and causes secondary avalanche breakdown at the interface. The width of the third semiconductor region, which is the gate at the end, is formed to be sufficiently longer than the width of the other third semiconductor region, which is the gate. The side end portion is formed away from the region immediately below the second semiconductor region by a distance that prevents hot carriers generated by the second avalanche breakdown from flowing into the second semiconductor region serving as a source. be done. Therefore, the second
Hot carriers generated by the next avalanche breakdown do not flow into the second semiconductor region of the first conductivity type, which is a source provided on the whole surface side of the first semiconductor region, and are Most of the liquid flows into the third semiconductor region, which is the gate at the end located above the interface of the fourth semiconductor region. For this reason, the drain
Even if a reverse bias voltage higher than the breakdown voltage value is applied between the gates, the breakdown voltage of the device will not deteriorate and the device will not be destroyed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional configuration diagram of a static induction transistor (SIT) which is an embodiment of the present invention.

Note that the same regions as the SIT shown in FIG.
).

The difference from the conventional 5ITIO shown in FIG. Second, the agate region 13 is longer than the n°°
The p gate region 31 (hereinafter referred to as
An n+ type drain region 32 having a higher impurity concentration than the n- type epitaxial layer 12' is provided in a part of the portion directly under the peripheral p° gate region 31).

In the above configuration, the impurity concentration of the source region 14 is approximately IXIO" cm, and the depth (film thickness) is approximately 0.3 μm.
The impurity concentration of the m, p + type source region 13 and the peripheral p°° gate region 31 is approximately I
9. The thickness) is approximately 3.5 μm. Further, the width W of the p'-type agate region 13 is about 9 μm, the width W2 of the peripheral p-type gate region 31 is about 40 μm, and the width W3 of the n-type drain region 32 is about 20 μm. Therefore, from the end of the n0 type drain region 32 on the inside side of the element,
The distance W4 parallel to the top surface of the device to the end of the peripheral p gate region 31 on the device side is approximately 30 μm, and n°
The inner end of the type drain region 32 element is separated from the region immediately below the n.type source region 14 by about 30 μm or more.

Further, the impurity concentration of the n-type epitaxial layer 12' is about I x 10'Scm-'', and the impurity concentration from the bottom surface of the peripheral p° type gate region 31 to the interface between the n-type substrate 11 and the n-type epitaxial layer 12' The distance is approximately 10 μm.

Further, the impurity concentration of the n'-type human train region 2 is about I
XIO"cm-', and the film thickness is approximately 2μm
It becomes.

Therefore, the distance 1h2 from the bottom of the peripheral p'' gate region 31 to the interface between the n'' type drain region 2 and the n- type epitaxial layer 12' is approximately 8 .mu.m. Further, the impurity concentration of the n+ type substrate 11 is approximately I x 10
' 8cm-3.

In this way, the vertical distance ttz (=8 μm) between the bottom surface of the peripheral p-type gate SR region 31 and the top surface of the n-type drain region 2 is equal to the vertical distance ttz (=8 μm)
The bottom surface of the p-type agate region 13 other than the area 31 and the n-type agate region 11
The distance between the top surface and the top surface is shorter than + (=10 μm).

Therefore, as shown in FIG. 5(a) or FIG. , A-A'' cross section p°° gate region 13-n-type epitaxial layer 12'-n' substrate 1 shown in FIG.
1) and B-B' cross section (peripheral pear-shaped gate area 3l-n
− type epitaxial layer 12′−n” type drain region 32
The electric field strength E between
It becomes as shown in .

In the figures (a) and (b), the vertical axis shows the electric field strength E, and the horizontal axis shows the distance from the interface between the p-type agate region 13 and the n-type epitaxial layer 12' (in the case of the A-A' cross section).
, the distance from the interface between the peripheral p'gate region 13 and the n-type epitaxial layer 12' (in the case of the B-B' cross section). Moreover, the electric field E crlL is p°° gate region 1
3 and the n-type epitaxial layer 12' and the surrounding p
This is the critical electric field at which avalanche breakdown occurs at the junction between the gate region 31 and the n-type epitaxial layer 12'.

As is well known, the gradient of the electric field E is determined by the impurity concentration. Therefore, when the impurity concentrations of the p'' gate region 31 around the p'' type agate region 13 are made equal (i.e.,
The p゛gate region 31 around the p゛type agate region 13,
When a reverse bias voltage is applied between the drain and the gate, the inside of the p' gate region 13 and the surrounding p
.

The gradient of the electric field E in the depletion layer region formed in the 81 region 31 is the same as shown in FIGS. 2(a) and 2(b). Further, the n-type epitaxial layer 12' is A
-A' cross section and B-B' cross section, so the electric field E in the depletion layer formed in the n-type epitaxial layer 12' in the A-A' cross section and the B-B' cross section is The slope of is also the same. Furthermore, since the impurity concentration of the n-type drain region 32 is higher than that of the n-type epitaxial layer 12', the gradient of the electric field E in the depletion layer region formed in the n-type drain region 32 is It becomes larger than the electric field E in the depletion layer formed within the depletion layer.

The solid lines 101 and 101' in FIG. 5(a) indicate the reverse bias voltage .
, the n-type epitaxial layer 12
The depletion layer region within ' is the n-type epitaxial N12'
The electric field intensity distribution (A-A” cross section) of the p” type gate region 13 and the n − type epitaxial layer 12 when reaching the interface between the n° type drain region 2 and the peripheral p type The electric field intensity distribution (BB' cross section) of the gate SM region 31 and the n-type epitaxial layer 12' is shown. As shown in (a) and (b) of the same figure, the reverse bias voltage ■
1, the junction between the p-type agate region 13 and the n-type epitaxial layer 12' (hereinafter referred to as A-A for convenience)
'The electric field strength of the pn junction in the cross section) and the surrounding p°
type gate S'fl region 31 and n-type epitaxial N12
The electric field strength at the junction with the junction with the Therefore, the critical electric field E cr □ has not yet been reached.

Next, the reverse bias voltage (■) is further increased, and when the reverse bias voltage (■1) reaches a predetermined voltage value (■2), the second
As shown in Figure (a), in the AA' cross section, n-
The depletion layer in the type epitaxial layer 12' further spreads to the n'' substrate 11 side, and eventually the n'' substrate 11 also becomes a depletion layer. As the depletion layer is formed, the electric field intensity distribution changes as shown by the broken line 102 in FIG. is dEI
, and becomes E2. However, this electric field E2 does not reach the critical electric field Eerlt at which avalanche breakdown occurs, and avalanche breakdown does not occur at the junction between p'gate region 13 and n-type epitaxial layer 112'.

On the other hand, in the B-B' cross section, the n+ type drain region 32 also becomes a depletion layer due to the application of the reverse bias voltage V2, but as described above, the impurity concentration of the n+ type drain region 32 is lower than that of the n type epitaxial layer. Since the impurity concentration is higher than that of N12', the n-type drain region 32
The extension of the depletion layer in the n-type epitaxial layer 12' is smaller than that in the n-type epitaxial layer 12'. Therefore, the same reverse bias voltage V, (=
V2), the peripheral p°° gate region 31 and n
The increase dE2 in the electric field E at the junction of the - type epitaxial layer 12' is greater than the increase dE2 in the electric field E at the junction between the p' gate region 13 and the n-type epitaxial layer 12' in the A-A' cross section. The junction between the peripheral p° gate region 31 and the n-type epitaxial layer 12' is larger than the junction between the peripheral p° gate region 13 and the n-type epitaxial layer 12'.
The critical electric field E crlt at which avalanche breakdown occurs is reached earlier (in other words, with a smaller reverse bias voltage 3) than at the junction of . Peripheral p゛゛gate region 3
As shown in FIG. 3, the electric field at the junction between 1 and the n-type epitaxial layer 12' is the critical electric field EC□.

When this reaches, a primary avalanche breakdown occurs at the junction between the peripheral p gate region 31 and the n-type epitaxial layer 12', and this primary avalanche breakdown further causes a breakdown between the n-type epitaxial layer 12' and the n-type epitaxial layer 12'. n.

Secondary avalanche breakdown occurs at the interface of the type drain region 32. The electric field in the depletion layer in the n-type epitaxial layer 12' is approximately perpendicular to the n°° substrate 11,
Also, an n type drain region 32 and an n type adjacent to the peripheral p type gate region 31.

Since it is formed at a sufficient distance from the region immediately below the type source region 14, among the holes and electrons generated in pairs due to the secondary avalanche breakdown, the holes are located at the peripheral p°° gate. n゛゛ source region 14 adjacent to region 21
All the peripheral p゛゛gate region 31
is flowing into the country. Therefore, the holes generated by this second avalanche breakdown are not injected into the channel region 19 and the n°° source region 14, leading to deterioration of the breakdown voltage of the device and
No element destruction occurs.

That is, when a reverse bias voltage is applied between the drain and the gate, the peripheral p' gate is A primary avalanche breakdown occurs at the junction between region 31 and n-type epitaxial layer 12'.

Following this primary avalanche breakdown, secondary avalanche breakdown occurs at the interface between the n-type epitaxial layer 12' and the n°-type drain region 32;
The holes generated by the next avalanche breakdown do not become hot holes and flow into the n°° source region 14, so unlike conventional SIT, the breakdown voltage of the device does not deteriorate or the device is destroyed. There isn't.

Note that the n'' type drain region 32 is formed using, for example, P(
After forming a high concentration region of impurity (P) partially at the position where the n-type drain region 2 is to be formed on the whole surface of the n-type substrate 11 by ion implantation or deposition of phosphorus), a high concentration region of impurity (P) is formed by epitaxial growth. It can be formed automatically by performing the step of forming the n-type epitaxial layer 12'. That is, an n-type epitaxial layer 12' is formed by epitaxial growth on an n-type substrate ll.
In the process of growing the n-type epitaxial layer 12', P (phosphorus) diffuses from the high concentration region of impurity (P) near one main surface of the n-type substrate 11 into the n-type epitaxial layer 12'. A °-type drain region 32 is formed. As is well known, P (phosphorus) has a gettering effect, so when the n-type drain region 32 is formed in the above manufacturing method, the interface between the n-type substrate 11 and the n-type tray region 32 is Crystal defects are gettered.

Although the above embodiment is an example of application to a surface-gate type n-channel SIT, the present invention can of course be applied to a surface-gate type p-channel SIT with the conductivity type reversed. Alternatively, it can be easily applied to a p-channel buried gate type SIT. Further, the device is not limited to a Si device, but may be a compound semiconductor such as Ge or Gaps.

〔Effect of the invention〕

According to the present invention, the width of the third semiconductor region (gate) of the second conductivity type provided at the extreme end of the device is made longer than the width of the third semiconductor region (gate) of the other second conductivity type. , and a part of the end portion of the element immediately below the third semiconductor region on the full surface of the semiconductor substrate of the first conductivity type, which is formed on the full surface of the semiconductor substrate of the first conductivity type. Since the fourth semiconductor region of the first conductivity type with higher impurity concentration than the first semiconductor region is formed, avalanche breakdown will not occur if a reverse bias voltage higher than the withstand voltage is applied between the drain and the gate. Hot carriers, which are generated in a limited manner only between the third semiconductor region provided at the extreme end of the element and the fourth semiconductor region, and which are generated due to the avalanche breakdown, are transferred to the second semiconductor region of the first conductivity type. There is no flow into (source).

As a result, even if a reverse bias voltage higher than the breakdown voltage value is applied between the drain and the gate, the breakdown voltage of the device does not deteriorate or the device is destroyed as in the conventional case.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional configuration diagram of an electrostatic induction transistor which is an embodiment of the present invention, and FIG. 2(a) and (b> are respectively A-A in FIG.
Figure 3 showing the electric field distribution in the 'cross section and the B-B' cross section.
The figure shows the critical electric field E C at which avalanche breakdown occurs at the junction surface of the peripheral p gate H region n epitaxial drain layer.
A diagram showing the electric field distribution when r1t is reached. Figure 4 is a cross-sectional diagram of a conventional static induction transistor. Figures 5 (a) and (b) are diagrams of the voltage when reverse biasing between the gate and drain. It is a figure which shows the application method. 11...n' source region, 12... p'' gate region, 13... n+ type drain layer, 14... n- type epitaxial drain layer, 15...
... Channel region, 16... Gate electrode, 17... Source electrode, 18... Drain electrode, 19... Oxide film, 21... Peripheral p°° gate region, 32... N+ type Drain region diagram 1

Claims (1)

[Scope of Claims] 1) A semiconductor substrate of a first conductivity type, and a semiconductor substrate of the first conductivity type formed on one main surface side of the semiconductor substrate of the first conductivity type and having an impurity concentration lower than that of the semiconductor substrate. a first semiconductor region; and the first semiconductor region formed near one main surface of the first semiconductor region.
a second semiconductor region of a conductive type and having a high impurity concentration; In a static induction transistor comprising a second conductivity type third semiconductor region, the width of the third semiconductor region formed at the extreme end near one main surface of the first semiconductor region is set to a width of another conductivity type. A part of a portion that is longer than the width of the third semiconductor region by a predetermined length and is located directly below the third semiconductor region on one main surface of the first conductivity type semiconductor substrate, A static induction transistor characterized in that the fourth semiconductor region of the first conductivity type and having a high impurity concentration is formed to have a predetermined thickness. 2) A claim characterized in that an end portion of the fourth semiconductor region of the first conductivity type on the inside side of the element is separated from a region immediately below the second semiconductor region of the first conductivity type by a predetermined distance. Item 1. The electrostatic induction transistor according to item 1.