JPH0383288A - Memory initializing system - Google Patents

Abstract

PURPOSE:To efficiently generate diagnosis data by initializing the whole content of a memory at once by means of a control signal and outputting a defined value even if any address is accessed. CONSTITUTION:When an address signal is inputted to an address decoder 3, a corresponding word line W comes to an 'H' level. When a first word line W comes to the 'H' level, transistors 5 and 6 connected to the first word line W are turned on, and memory cells 4 are connected to a bit line B and the inverse of B. When the state of the bit line B and the inverse of B is read in such a state, the value of the memory cells 4 can be learnt. When a desired value is impressed on the bit line B and the inverse of B, data can be written on the memory cells 4. When the control signal C comes to the 'H' level, all the word lines W come to the 'H' level and TR 5 and 6 connected to all the word lines W are turned on. Consequently, the defined value can be obtained even if any address is accessed.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory initialization method, the present invention aims to provide a memory initialization method that can initialize the entire contents of the memory at once using a control signal. a memory cell array having a plurality of focus line pairs, a plurality of memory cells arranged in a matrix, a bit line driving means connected to the control signal line, and a bit line driving means connected to the control signal line. word line driving means, the word line driving means is configured to apply a signal at a predetermined level to all the word lines when the signal on the control line is a predetermined value, and the bit line driving means is configured to apply a signal at a predetermined level to all the word lines. The configuration is such that when the signal on the control signal line is at a predetermined value, a signal for setting the value of the memory cell to a predetermined value is applied to each of all bit line pairs.

[Industrial application field]

The present invention relates to a memory initialization scheme configured such that the contents of all memory cells are initialized at once by a control signal.

(Prior Art) The contents of memories such as RAM and register files are unknown when the power is turned on. LS with built-in memory
When performing a failure test on a circuit related to memory output in an I (for example, a microprocessor), it is necessary to determine the contents of the memory, and it is necessary to write data to the memory.

[Problem to be solved by the invention]

However, in LSI microprocessors and the like that have a built-in memory, the memory cannot be directly seen from the outside, so data must be written into the memory by applying various signal patterns to input bins. This has been a cause of an increase in the time required to create diagnostic data and the number of patterns.

The present invention was created in view of this point, and it is an object of the present invention to provide a memory initialization method that can initialize all contents of a memory at once using a control signal.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. The memory initialization method of the present invention includes a memory cell array 20, a bit line driving means 30 connected to a control signal line, and a word line driving means 4 connected to the control signal line.
0.

The memory cell array 20 includes a plurality of word lines W, .
W,...,Wi, multiple bit line pairs BP,...
BP, . are configured to be connected to respective bit line pairs.

The word line driving means 40 drives all the word lines W, W2 . . . when the signal on the control line is at a predetermined value.
..., W, 4 are configured to apply a signal of a predetermined level.

The bit line driving means 30 drives all bit line pairs BP+ when the signal on the control signal line is at a predetermined value.
, BPz, . . . , BPN are configured to apply a signal for setting the value of the memory cell to a predetermined value.

[Effect]

When the control signal reaches a predetermined level (for example, high level), the word line driving means 40 drives all the word lines.
Lines W,, Wt, . . . , WM are set at a predetermined level (high level). When a word line reaches a predetermined level, the memory cells belonging to the word line are connected to their respective bit line pairs. Further, when the control signal reaches a predetermined level (for example, a high level), the bit line driving means 30 outputs the value of the memory cell to each of all bit line pairs BP, BP, . . . , BP. A signal is applied to set the value to a predetermined value (for example, logic O). By the above operation, a predetermined value is written to all memory cells in the memory cell array.

〔Example〕

FIG. 2 is a block diagram of one embodiment of the present invention.

In the figure, 1 is a bit line charging transistor, 2 is a word line buffer, 3 is an address decoder, 4 is a memory cell, 5 and 6 are transistors, 7 to 9 are inverters, and W is a word line buffer. Lines B and B indicate bit lines, and C indicates a control signal, respectively.

Transistor 1 is P-channel MO3! - transistors, and transistors 5 and 6 are N-channel MOS) transistors. The P-channel MOS transistor is turned on when the gate is at l L n level, and the N-channel MOS transistor is turned on when the gate is at l L n level.
The S transistor is turned on when its gate is at "°H" level. Word line buffer 2 is an OR gate,
The control signal C is input to the upper input, and the output of the address decoder 3 is input to the lower input. The address decoder 3 decodes the address and sets the signal on the corresponding output line to the "l Hl" level.

Memory cell 4 is a latch, which is formed by inverters 7 and 8. Inverter 9 inverts the control signal, and the output of inverter 9 is applied to the gate of transistor 1. Although FIG. 2 shows a memory with M rows and 1 column, the actual memory has M rows and 1 column.
It has rows and N columns.

When the address signal is input to address decoder 3,
The corresponding word line W becomes "H" level. 1st
Assuming that the 1st word line W becomes "H" level, transistors 5 and 6 connected to the 1st word line W are turned on, and the memory cell 4 is connected to the bit line B.

Connected to B. In this state, bit line B
, B, the value of the memory cell 4 can be known, and by applying a desired value on the bit lines B, B, data can be written to the memory cell 4.

When the control signal C becomes "H" level, all word lines W become "'H" level, and transistors 5 and 6 connected to all word lines W are turned on. Further, the "H" level control signal C is inverted by the inverter 9, and a "L" level signal is applied to the gate of the transistor 1, turning on the transistor 1. When the transistor 1 is turned on, the bit line B goes to the "H" level, and logic O is written to all memory cells 4. When the control signal C goes to the "L" level, the transistor I turns off, and the word line B goes to the "H" level. Since the buffer 2 receives input from the decoder 3, it operates normally.

FIG. 3 is a diagram showing an example of the configuration of a power-on reset circuit. In the figure, 10 is an inverter, 11 is a resistor,
12 each indicates a capacitor.

When the power is turned on, the potential at point A is at the "L" level, and as time passes, the potential at point A gradually increases. A
When the potential at point A is at the "L" level, the output of the inverter 10 is at the "H" level, and when the potential at point A is at the H level, the output from the inverter 10 is at the "'L" level.

The output of inverter tO becomes control signal C.

FIG. 4 is a diagram showing potential changes in the power-on reset circuit. The potential at point A gradually increases with time. A
Is the potential at the point the threshold V? When the voltage is below H, the output of the inverter 10 is at the "H" level, and the potential at point A is equal to the threshold V? )I
In the state where the voltage exceeds the threshold value VtH, the output of the inverter 10 is at the "Ln level." The memory is initialized until the potential at the point A reaches the threshold value VtH.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, all memory contents can be initialized at once by a control signal, so a fixed value is output no matter what address is accessed, and there is no need to perform a write operation during diagnosis. Since no undefined values are output, efficient diagnostic data can be created. Note that the present invention is also applicable to memories such as register files.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is a block diagram of a configuration example of a power-on reset circuit, and Fig. 4 is a block diagram of a power-on reset circuit. FIG. 3 is a diagram showing potential changes. 1... Bit line charging transistor, 2
...word line buffer, 3...address...
Decoder, 4...Memory cell, 5 and 6...Transistor, 7-9...Inverter, 10...Inverter, 11...Resistor, 12...Capacitor, W...
Word uin, B and B... pit line, C... control signal.

Claims (1)

[Claims] A plurality of word lines (W_1, W_2,..., W_M
), a plurality of bit line pairs (BP_1, BP_2...,
BP_N) and a plurality of memory cells arranged in a matrix, and when the signal of the i-th word line is at a predetermined level, all the memory cells belonging to the i-th row are connected to the corresponding bit line. A memory cell array (20) configured to be connected in pairs, a bit line driving means (30) connected to a control signal line, and a word line driving means (40) connected to a control signal line. ), and the word line driving means (40) drives all the word lines (W_1) when the signal on the control line is a predetermined value.
, W_2..., W_M), and the bit line driving means (30) is configured to apply a signal of a predetermined level to all the bit line pairs (
BP_1, BP_2, ..., BP_N) is configured to apply a signal for setting a value of a memory cell to a predetermined value.