JPH0382184A - High resistance buried semiconductor laser and manufacture thereof - Google Patents
High resistance buried semiconductor laser and manufacture thereofInfo
- Publication number
- JPH0382184A JPH0382184A JP21901789A JP21901789A JPH0382184A JP H0382184 A JPH0382184 A JP H0382184A JP 21901789 A JP21901789 A JP 21901789A JP 21901789 A JP21901789 A JP 21901789A JP H0382184 A JPH0382184 A JP H0382184A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- type
- type semiconductor
- mesa
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 124
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 27
- 238000005253 cladding Methods 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000010355 oscillation Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 97
- 238000009792 diffusion process Methods 0.000 description 11
- 230000003287 optical effect Effects 0.000 description 9
- 239000013078 crystal Substances 0.000 description 7
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005524 hole trap Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- MODGUXHMLLXODK-UHFFFAOYSA-N [Br].CO Chemical compound [Br].CO MODGUXHMLLXODK-UHFFFAOYSA-N 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- NBJBFKVCPBJQMR-APKOLTMOSA-N nff 1 Chemical compound C([C@H](NC(=O)[C@H](CCC(N)=O)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H]1CCCN1C(=O)[C@H](CCCCN)NC(=O)[C@@H]1CCCN1C(=O)CC=1C2=CC=C(C=C2OC(=O)C=1)OC)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)NCC(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCCNC=1C(=CC(=CC=1)[N+]([O-])=O)[N+]([O-])=O)C(=O)NCC(O)=O)C1=CC=CC=C1 NBJBFKVCPBJQMR-APKOLTMOSA-N 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、光通信用光源等に用いられる高抵抗埋め込み
半導体レーザとその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-resistance buried semiconductor laser used as a light source for optical communications and a method for manufacturing the same.
(従来の技術)
光フアイバ通信技術は近年目覚ましい進展を遂げ、40
0Mb/s、 1.6Gb/sなどの大容量の光通信シ
ステムが日本国内をはじめ、海底ケーブルを通じて外国
との間にも導入されている。この光通信技術になくては
ならないキーデバイスが光信号の光源となる半導体レー
ザである。システムの長距離、大容量化に伴い、半導体
レーザにもさらに高出力化、高速化が求められている。(Conventional technology) Optical fiber communication technology has made remarkable progress in recent years, and
High-capacity optical communication systems such as 0 Mb/s and 1.6 Gb/s have been introduced not only within Japan but also with foreign countries via submarine cables. A key device indispensable to this optical communication technology is a semiconductor laser, which serves as a light source for optical signals. As systems become longer-distance and larger-capacity, semiconductor lasers are also required to have even higher output and faster speed.
現在一般的に使用されている半導体レーザは、電流ブロ
ック領域がpnpnのサイリスタ構造になっている。し
かし、この構造では、電流を増加させるとサイリスタが
ターンオンしたり、サイリスタを構成するトランジスタ
のゲインが大きい時には無視できない程度の電流が流れ
、光出力が飽和してしまう恐れがある。また、サイリス
タに寄生容量が存在するため、RC時定数が大きく、高
速変調が実現しにくい。Semiconductor lasers commonly used at present have a thyristor structure in which the current blocking region is pnpn. However, with this structure, when the current increases, the thyristor may turn on, or when the gain of the transistor constituting the thyristor is large, a non-negligible amount of current flows, and the optical output may become saturated. Furthermore, since the thyristor has parasitic capacitance, the RC time constant is large, making it difficult to achieve high-speed modulation.
一方、電流ブロック領域に高抵抗半導体層を用いた半導
体レーザは、漏れ電流か少ないので低いしきい動作が可
能であり、また寄生容量が少ないため、高速変調も可能
となることから、最近さかんに研究開発が行われている
。On the other hand, semiconductor lasers that use a high-resistance semiconductor layer in the current blocking region have been gaining popularity recently because they have low leakage current, allowing low threshold operation, and have low parasitic capacitance, making high-speed modulation possible. Research and development is underway.
その高抵抗埋め込み半導体レーザの従来例を第3図に示
す。第3図(a)はp型InP基板1上にp型InPク
ラッド層2、InGsAsP活性層3、n型InPクラ
ッド層4からなるダブルヘテロ構造がメサ状に形成され
、これが半絶縁(SI)InP層5で埋めこまれ、その
上にn型InP層7が全面に、さらに両側にp型電極2
1およびn型電極22が形成された構造からなる。また
第3図(b)はn型InP基板8を用いた場合で、それ
ぞれのInP層の導電形が(a)と異なっているほか、
p側のオーミックコンタクトを取るために、p+型In
GaAsPコンタクト層10がp側電極21に接して形
成されている。A conventional example of such a high-resistance buried semiconductor laser is shown in FIG. In FIG. 3(a), a mesa-shaped double heterostructure consisting of a p-type InP cladding layer 2, an InGsAsP active layer 3, and an n-type InP cladding layer 4 is formed on a p-type InP substrate 1, and this is a semi-insulating (SI) structure. It is buried with an InP layer 5, on which an n-type InP layer 7 is formed over the entire surface, and p-type electrodes 2 are formed on both sides.
1 and an n-type electrode 22 are formed. Further, FIG. 3(b) shows the case where an n-type InP substrate 8 is used, and the conductivity type of each InP layer is different from that in FIG. 3(a).
In order to make ohmic contact on the p side, p+ type In
A GaAsP contact layer 10 is formed in contact with the p-side electrode 21.
(発明が解決しようとする課題)
電流ブロック構造に用いられる半絶縁半導体層は、電流
がまったく流れない絶縁物ではない。たとえば、もっと
も一般的である鉄(Fe)をドーピングしたInPの場
合、InPの禁制帯の中に深い準位を形成したFeは電
子トラップとして機能する。すなわち、Feをドープし
たInPをp型およびn型InPではさんで交流電圧を
印加した場合、n型InPからFeドープInPに注入
される電子はFeトラップにより捕獲される。p型In
PからFeドープInPに注入される正孔は、Feアク
セプタにすでに捕獲されている電子と再結合し、これは
再結合電流となる。このため、第3図のような構造では
、p型InP層l、2(第3図(a))または2.9(
第3図(b))から半絶縁InP層5に流れる漏れ電流
が存在し、十分な電流ブロック効果が得られずしきい値
電流の増大や効率の低下、光出力の飽和などの原因とな
る。(Problems to be Solved by the Invention) The semi-insulating semiconductor layer used in the current block structure is not an insulator through which no current flows. For example, in the case of InP doped with iron (Fe), which is the most common, the Fe that forms a deep level in the forbidden band of InP functions as an electron trap. That is, when an AC voltage is applied to Fe-doped InP sandwiched between p-type and n-type InP, electrons injected from the n-type InP to the Fe-doped InP are captured by Fe traps. p-type In
Holes injected from P into Fe-doped InP recombine with electrons already captured by Fe acceptors, resulting in a recombination current. Therefore, in the structure shown in FIG. 3, the p-type InP layer 1,2 (FIG. 3(a)) or 2.9(
As shown in Fig. 3(b), there is a leakage current flowing through the semi-insulating InP layer 5, and a sufficient current blocking effect cannot be obtained, causing an increase in threshold current, a decrease in efficiency, and saturation of optical output. .
深い不純物にチタン(Ti)やコバルト(Co)といっ
た正孔トラップを用いた場合は正孔トラップとして働く
のでn型InP4.7(第3図(a))または4.8(
第3図(b))から半絶縁InP層5に電流が流れる。When a hole trap such as titanium (Ti) or cobalt (Co) is used as a deep impurity, it works as a hole trap, so n-type InP4.7 (Figure 3 (a)) or 4.8 (
A current flows through the semi-insulating InP layer 5 from FIG. 3(b).
こうした問題点を解決しなければ、高抵抗埋め込み半導
体レーザの低しきい値、高効率かつ高速変調可能という
特徴を充分生かすことはできなかった。Unless these problems are solved, the features of high-resistance buried semiconductor lasers, such as low threshold voltage, high efficiency, and high-speed modulation, cannot be fully utilized.
(課題を解決するための手段)
本発明の高抵抗埋め込み半導体レーザは、第1導電型半
導体基板上に、少なくとも前記半導体基板よりエネルギ
ーギャップの小さい半導体活性層及び第2導電型半導体
クラッド層からなるダブルヘテロ構造が、ストライプ状
のメサに形成され、そのメサの両側に正孔を捕獲する準
位を有した半絶縁半導体層及びp型半導体層を含む半導
体埋め込み層が前記半導体基板がp型のときはこの順に
、n型のときはこの逆の順に形成され、さらに前記メサ
の上及び半導体埋め込み層の上に第2導電型半導体が形
成され、前記ストライプ状のメサの側面のn型半導体ク
ラッド層と前記半絶縁半導体層との間にp型半導体層が
あることを特徴とする。(Means for Solving the Problems) A high-resistance buried semiconductor laser of the present invention includes, on a first conductivity type semiconductor substrate, at least a semiconductor active layer having a smaller energy gap than the semiconductor substrate and a second conductivity type semiconductor cladding layer. A double heterostructure is formed in a striped mesa, and a semiconductor buried layer including a semi-insulating semiconductor layer having a level for trapping holes and a p-type semiconductor layer on both sides of the mesa is formed when the semiconductor substrate is p-type. A second conductivity type semiconductor is formed on the mesa and on the semiconductor buried layer, and an n-type semiconductor cladding on the side surface of the striped mesa is formed. A p-type semiconductor layer is provided between the semiconductor layer and the semi-insulating semiconductor layer.
本発明の製造方法は、第1導電型半導体半導体基板上に
、少なくとも半導体活性層および第2導電型半導体クラ
ッド層からなる半導体層を形成する工程と、前記活性層
を含む半導体層を、ストライプ状の絶縁膜をマスクにし
てエツチングしメサを形成する工程と、前記基板がp型
のときは正孔を捕獲する準位を有した半絶縁半導体層と
p型半導体装置なる半導体埋め込み層をこの順に、前記
基板がn型のときはこの逆の順に、埋め込み成長により
形成すると同時にその埋め込み成長中にp型半導体層中
のp型不純物の拡散により前記ストライプ状のメサの側
面のn型半導体クラッド層との界面で前記半絶縁半導体
がp型に変わる工程と、前記絶縁膜を除去した後に第2
導電型半導体層を全面に成長する工程とを含むことを特
徴とする。The manufacturing method of the present invention includes a step of forming a semiconductor layer including at least a semiconductor active layer and a second conductivity type semiconductor cladding layer on a first conductivity type semiconductor substrate, and forming the semiconductor layer including the active layer in a stripe shape. etching using the insulating film as a mask to form a mesa, and when the substrate is p-type, a semi-insulating semiconductor layer having a hole capturing level and a semiconductor buried layer constituting a p-type semiconductor device are formed in this order. , when the substrate is n-type, an n-type semiconductor cladding layer is formed on the side surface of the striped mesa by diffusion of the p-type impurity in the p-type semiconductor layer during the buried growth at the same time as the substrate is formed by buried growth. a step in which the semi-insulating semiconductor changes to p-type at the interface with the semi-insulating semiconductor, and a second step after removing the insulating film
The method is characterized by including a step of growing a conductive semiconductor layer over the entire surface.
(作用)
高抵抗の半絶縁半導体(SI)層として正孔(ホール)
を捕獲する不純物を用いたp−8I−n構造では、p型
半導体からS躇へ注入される正孔は捕獲される。しかし
n型半導体からSI層へ注入される電子は捕獲されず、
8画中にすでに捕獲されている正孔と再結合する。これ
が漏れ電流となり高抵抗層を用いた電流ブロック効果が
十分に発揮されない。(Function) Holes as a high-resistance semi-insulating semiconductor (SI) layer
In the p-8I-n structure using an impurity that captures , holes injected from the p-type semiconductor into S are captured. However, the electrons injected from the n-type semiconductor into the SI layer are not captured,
It recombines with the holes already captured in the 8th picture. This becomes a leakage current, and the current blocking effect using the high resistance layer is not sufficiently exhibited.
本発明の高抵抗埋め込み半導体レーザでは電流ブロック
領域をp−8I−p−n構造とし、ここでの漏れ電流を
なくした。さらにそのメサ側面においてもp−8r−n
構造をなくすためメサの側面と半絶縁半導体層の間にp
型半導体層を入れて、p−8I−p−n構造として漏れ
電流をなくし、しかもそのp型半導体層を濃度の低いp
−層として抵抗を高くすることによって、このメサ側面
のp−半導体層を通ってメサのp型半導体クラッド層か
らn型半導体クラッド層へ流れる漏れ電流を非常に小さ
くすることができる。このようにして漏れ電流をなくす
ことができるので、低発振閾値電流、高発光効率が得ら
れる。In the high-resistance buried semiconductor laser of the present invention, the current block region has a p-8I-pn structure to eliminate leakage current there. Furthermore, on the mesa side, p-8r-n
P between the mesa side and the semi-insulating semiconductor layer to eliminate the structure.
A p-type semiconductor layer is added to eliminate leakage current as a p-8I-pn structure.
By increasing the resistance of the - layer, the leakage current flowing from the p-type semiconductor cladding layer of the mesa to the n-type semiconductor cladding layer through the p-semiconductor layer on the side surface of the mesa can be made very small. Since leakage current can be eliminated in this way, a low oscillation threshold current and high luminous efficiency can be obtained.
本発明の製造方法では、p型半導体層からp型不純物が
埋め込み成長の過程で自動的に半絶縁半導体層に拡散す
ることにより、メサ側面との界面で半絶縁半導体層がp
−型に変わり、良好な電流ブロック構造が容易に再現性
良く得られる。In the manufacturing method of the present invention, the p-type impurity from the p-type semiconductor layer is automatically diffused into the semi-insulating semiconductor layer during the buried growth process, so that the semi-insulating semiconductor layer becomes p-type at the interface with the mesa side surface.
- A good current block structure can be easily obtained with good reproducibility.
我々は不純物となるCoをドーピングした半絶縁InP
層、およびドナーとなるSiをドーピングしたn型In
P層の上にZnをドーピングしたp型InP層(キャリ
ア濃度1×1018cm−3)を成長し、SIMS測定
によってZnの拡散の度合いを調べた。結晶成長には有
機金属気相成長法(MOVPEもしくはMOCVD)を
用いた。その結果、第2図(a)に示すように、半絶縁
InP層には約0.3pmのZnの拡散が観測されたの
に対し、第2図(b)に示すように、n型InP層には
Znはほとんど拡散しなかった。このように、Znの半
絶縁半導体への拡散は通常の結晶成長条件下では0.3
pm程度である。nff1半導体層へのZnの拡散はほ
とんどなくp−型に反転することはない。また、メサの
側面に形成されるp−型InP層に拡散したZnの濃度
はp型半導体層中のZn濃度の十分の一程度であるので
、拡散により生じたp−型InP層は抵抗が高く、ここ
を流れる漏れ電流は非常に小さい。We used semi-insulating InP doped with Co as an impurity.
layer, and n-type In doped with Si to serve as a donor.
A p-type InP layer doped with Zn (carrier concentration 1×10 18 cm −3 ) was grown on the P layer, and the degree of Zn diffusion was examined by SIMS measurement. Metal organic vapor phase epitaxy (MOVPE or MOCVD) was used for crystal growth. As a result, as shown in Figure 2(a), Zn diffusion of about 0.3 pm was observed in the semi-insulating InP layer, whereas as shown in Figure 2(b), Zn diffusion was observed in the semi-insulating InP layer. Zn hardly diffused into the layer. Thus, the diffusion of Zn into a semi-insulating semiconductor is 0.3 under normal crystal growth conditions.
It is about pm. There is almost no diffusion of Zn into the nff1 semiconductor layer, and there is no inversion to the p-type. Furthermore, since the concentration of Zn diffused into the p-type InP layer formed on the side surface of the mesa is about one-tenth of the Zn concentration in the p-type semiconductor layer, the p-type InP layer formed by diffusion has a low resistance. The leakage current flowing through it is very small.
この製造方法では特別な拡散工程はなく、結晶成長中に
p型半導体から半絶縁半導体に拡散することを利用して
いる。従って制御性、再現性が良く半導体レーザを高歩
留りに作製できる。This manufacturing method does not require any special diffusion process, and utilizes diffusion from a p-type semiconductor to a semi-insulating semiconductor during crystal growth. Therefore, semiconductor lasers can be manufactured with good controllability and reproducibility at a high yield.
(実施例)
本発明の高抵抗埋め込み半導体レーザを実際に試作した
結果について、以下に述べる。第1図は試作した半導体
レーザの構造を表す断面図であり、(a)はp型半導体
基板を用いた場合で第一導電型がp型、第2導電型がn
型であり、(b)はn型半導体基板を用いた場合で導電
型が(a)と逆であるが、ここでは(a)の場合につい
て詳細に説明する。(Example) The results of actually prototyping the high-resistance buried semiconductor laser of the present invention will be described below. FIG. 1 is a cross-sectional view showing the structure of a prototype semiconductor laser, in which (a) shows a case where a p-type semiconductor substrate is used, the first conductivity type is p-type, and the second conductivity type is n-type.
(b) is a case where an n-type semiconductor substrate is used and the conductivity type is opposite to (a), but here, the case (a) will be explained in detail.
すべての結晶成長、MOVPEで行った。まず、p型I
nP基板1の上に、Znドープp型InPクラッド層2
(キャリア濃度5X1017cm−3、層厚1pm)、
ノンドープInGaAsP活性層3(層厚0.2pm)
、Siドープn型InPクラッド層4(キャリア濃度4
X1018cm−3、層厚0.4pm)からなるダブル
ヘテロ構造結晶を成長じた。次に表面5i02膜を堆積
してフォトリソグラフィ技術により幅1.5pmのスト
ライプに加工し、塩酸系および臭素−メタノール系のエ
ツチング液を用いてp型InP基板1に達するまでメサ
エッチングを行った。そして、5i02ストライブをマ
スクとして、高抵抗のCOドープ半半絶縁In面層5未
捕獲トラップ濃度2×1016cm−3、層厚的2.3
pm)、Znドープp型InP層6(キャリア濃度1×
1011018C、層厚0.5pm)を埋め込み成長じ
た。半絶縁InP層5とp型InP層6の界面が、n型
InPクラッド層4と5i02ストライブの界面とほぼ
同一平面上になるようにした。さらに、5i02ストラ
イブを除去した後、全面にSiドープn型InP層7(
キャリア濃度2×1018cm−3、層厚1.3pm)
を成長じた。断面を走査型電子顕微鏡(SEM)で賎察
するためにウェハの一部を取りおき、残りのウェハはn
側電極22としてAuGeNiを蒸着した後、430°
Cで5分間熱処理し、全体の厚さが約1100pになる
ようにp型InP基板1を研磨し、さらにp側電極21
としてTi/Pt/Auをスパッタした後、430’C
で5分間熱処理した。こうしてプロセスを終えたウェハ
は共振器長300pmになるようにへき関し、Siヒー
トシンク上にマウントして組み立て、素子特性を評価し
た。All crystal growth was done by MOVPE. First, p-type I
A Zn-doped p-type InP cladding layer 2 is formed on the nP substrate 1.
(carrier concentration 5X1017cm-3, layer thickness 1pm),
Non-doped InGaAsP active layer 3 (layer thickness 0.2 pm)
, Si-doped n-type InP cladding layer 4 (carrier concentration 4
A double heterostructure crystal consisting of a layer thickness of 0.4 pm and a thickness of 0.4 pm was grown. Next, a surface 5i02 film was deposited and processed into stripes with a width of 1.5 pm by photolithography, and mesa etching was performed using a hydrochloric acid-based and bromine-methanol-based etching solution until the p-type InP substrate 1 was reached. Then, using the 5i02 stripe as a mask, a high resistance CO-doped semi-semi-insulating In surface layer 5 with an uncaptured trap concentration of 2 x 1016 cm-3 and a layer thickness of 2.3
pm), Zn-doped p-type InP layer 6 (carrier concentration 1×
1011018C, layer thickness 0.5 pm) was buried and grown. The interface between the semi-insulating InP layer 5 and the p-type InP layer 6 was arranged to be approximately on the same plane as the interface between the n-type InP cladding layer 4 and the 5i02 stripe. Furthermore, after removing the 5i02 stripes, the Si-doped n-type InP layer 7 (
carrier concentration 2 x 1018 cm-3, layer thickness 1.3 pm)
has grown. A portion of the wafer was set aside for cross-section observation using a scanning electron microscope (SEM), and the remaining wafer was
After depositing AuGeNi as the side electrode 22, 430°
The p-type InP substrate 1 is heat-treated with C for 5 minutes, polished to a total thickness of about 1100p, and the p-side electrode 21
After sputtering Ti/Pt/Au as
was heat-treated for 5 minutes. The wafers thus processed were separated so that the resonator length was 300 pm, mounted on a Si heat sink and assembled, and the device characteristics were evaluated.
SEM観察の結果、Znが半絶縁InP層5内に約0.
3pm拡散してp−型InP層11を形成し、n型In
Pクラッド層4の界面で半絶縁InP層5がp型に変化
しp″″′型InP層11となっていることがわかった
。拡散により、半絶縁InP層5の層厚は約1.711
mに減少した。活性層幅は1.5pmであった。As a result of SEM observation, Zn is present in the semi-insulating InP layer 5 at a concentration of approximately 0.
A p-type InP layer 11 is formed by diffusion of 3 pm, and an n-type InP layer 11 is formed.
It was found that the semi-insulating InP layer 5 changed to p-type at the interface of the P cladding layer 4 and became a p'''' type InP layer 11. Due to diffusion, the layer thickness of the semi-insulating InP layer 5 is approximately 1.711
decreased to m. The active layer width was 1.5 pm.
切り出した素子の電流−光出力特性を測定したところ、
しきい値電流が平均10mA(最小7mA)、効率が平
均0.23W/A、最高光出力が平均30mW(最高4
2mW)と良好な結果を得た。これは、高抵抗埋め込み
によって埋め込み部での漏れ電流が減少したためであり
、特にp型InP層6および結晶成長時に形成されるp
−型InP層11の存在によって、n型にInP層(4
,7)から半絶縁InP層5へ流れる再結合電流がなく
なったためである。また、素子容量は約4pFと小さく
、小信号周波数応答特性を測定したところ、低周波域で
の応答の低下(ロールオフ)が少ない特性が得られ、1
5mW光出力時の変調周波数帯域は12GHzであった
。これらの特性は従来の高抵抗埋め込み半導体レーザに
比べ閾値電流、最高光出力の点で優れ、従来のp−n−
p−n型ブロツク構造をもつレーザに比べ閾値電流、変
調帯域の点で優れている。また製造が容易で従来の約2
倍の歩留りであった。When we measured the current-light output characteristics of the cut out element, we found that
Threshold current is average 10mA (minimum 7mA), efficiency is average 0.23W/A, maximum light output is average 30mW (maximum 4
Good results were obtained (2 mW). This is because the leakage current in the buried portion is reduced by high-resistance embedding, and in particular, the p-type InP layer 6 and the p-type InP layer 6 formed during crystal growth.
The presence of the - type InP layer 11 makes the n-type InP layer (4
, 7) to the semi-insulating InP layer 5 is no longer present. In addition, the element capacitance is small at approximately 4 pF, and when we measured the small signal frequency response characteristics, we obtained characteristics with little response drop (roll-off) in the low frequency range.
The modulation frequency band at 5 mW optical output was 12 GHz. These characteristics are superior to conventional high-resistance buried semiconductor lasers in terms of threshold current and maximum optical output, and they are superior to conventional high-resistance buried semiconductor lasers in terms of threshold current and maximum optical output.
It is superior to lasers with a pn block structure in terms of threshold current and modulation band. In addition, it is easy to manufacture and about 2 times the conventional
The yield was twice as high.
以上述べた結果は第1図(a)の、p型InP基板1を
用いた場合であったが、第1図(b)のようなn型In
P基板8を用いた場合も同様である。p型InP層6.
9およびp型InPクラッド層2がら半絶縁InP層5
へZnが拡散して半絶縁InP層5とn型InPクラッ
ド層4の間にp−型InP層11が形成されるようにす
ればよい。この例では、p側のオーミックコンタクトを
とるために、p+型InGaAsPコンタクト層10が
用いられている。The results described above were obtained using the p-type InP substrate 1 shown in FIG. 1(a), but when using the n-type InP substrate 1 shown in FIG.
The same applies when the P substrate 8 is used. p-type InP layer6.
9 and p-type InP cladding layer 2 as well as semi-insulating InP layer 5
Zn may be diffused into the p-type InP layer 11 to be formed between the semi-insulating InP layer 5 and the n-type InP cladding layer 4. In this example, a p+ type InGaAsP contact layer 10 is used to establish a p-side ohmic contact.
実施例では高抵抗層を形成するためのドーパントとして
Coを用いたが、Tiなどの同様な物性を有する元素を
用いても本発明の主旨になんら変わりはない。また、I
nGaAsP/InPでなく AlGaAs/GaAs
、AIGaInP/GaInP等の他の化合物混晶から
なるダブルヘテロ構造を用いても同様の効果がある。In the embodiment, Co was used as a dopant for forming the high resistance layer, but the gist of the present invention does not change at all even if an element having similar physical properties such as Ti is used. Also, I
AlGaAs/GaAs instead of nGaAsP/InP
, AIGaInP/GaInP and other compound mixed crystal double heterostructures can have similar effects.
(発明の効果)
本発明によれば、漏れ電流がなく低閾値で高効率な特性
であり、しかも寄生容量が小さく高速変調可能な半導体
レーザが得られ、本発明の製造方法によれば高性能な半
導体レーザが歩留り良く、再現性良く得られる。(Effects of the Invention) According to the present invention, a semiconductor laser with no leakage current, low threshold value, high efficiency characteristics, small parasitic capacitance, and high-speed modulation can be obtained, and the manufacturing method of the present invention provides a high-performance semiconductor laser. A semiconductor laser with high yield and good reproducibility can be obtained.
第1図(aXb)は本発明の高抵抗埋め込み半導体レー
ザの構造を表す断面図であり、それぞれp型半導体基板
、n型半導体基板を用いた場合である。第2図(aXb
)は本発明の詳細な説明する、半導体多層構造のSIM
S測定による濃度プロファイルの図である。また、第3
図(aXb)は従来の高抵抗埋め込み半導体レーザの構
造を表す断面図である。
図中、1・・・p型半導体基板、2・・・p型半導体ク
ラッド層、3・・・半導体活性層、4・・・n型半導体
クラッド層、5・・・半絶縁半導体層、6・・・p型半
導体層、7・・・n型半導体層、8・・・n型半導体基
板、9・・・p型半導体層、10・・・p生型半導体コ
ンタクト層、11・・・p−型半導体層、21・・・p
側電極、22・・n側電極である。FIG. 1 (aXb) is a cross-sectional view showing the structure of a high-resistance buried semiconductor laser of the present invention, using a p-type semiconductor substrate and an n-type semiconductor substrate, respectively. Figure 2 (aXb
) is a semiconductor multilayer structure SIM, which provides a detailed explanation of the present invention.
FIG. 3 is a diagram of a concentration profile obtained by S measurement. Also, the third
Figures (aXb) are cross-sectional views showing the structure of a conventional high-resistance buried semiconductor laser. In the figure, 1... p-type semiconductor substrate, 2... p-type semiconductor cladding layer, 3... semiconductor active layer, 4... n-type semiconductor cladding layer, 5... semi-insulating semiconductor layer, 6... ... p-type semiconductor layer, 7... n-type semiconductor layer, 8... n-type semiconductor substrate, 9... p-type semiconductor layer, 10... p-type semiconductor contact layer, 11... p-type semiconductor layer, 21...p
side electrode, 22... n-side electrode.
Claims (2)
体基板よりエネルギーギャップの小さい半導体活性層及
び第2導電型半導体クラッド層からなるダブルヘテロ構
造が、ストライプ状のメサに形成され、そのメサの両側
に正孔を捕獲する準位を有した半絶縁半導体層及びp型
半導体層を含む半導体埋め込み層が前記半導体基板がp
型のときはこの順にn型のときはこの逆の順に形成され
、さらに前記メサの上及び半導体埋め込み層の上に第2
導電型半導体が形成され、前記ストライプ状のメサの側
面のn型半導体クラッド層と前記半絶縁半導体層との間
にp型半導体層があることを特徴とする高抵抗埋め込み
半導体レーザ。(1) On a first conductivity type semiconductor substrate, a double heterostructure consisting of a semiconductor active layer and a second conductivity type semiconductor cladding layer having at least a smaller energy gap than the semiconductor substrate is formed in a striped mesa, and the mesa is A semiconductor buried layer including a semi-insulating semiconductor layer and a p-type semiconductor layer having a level for trapping holes on both sides is arranged so that the semiconductor substrate is p-type.
A second layer is formed in this order when the type is formed, and in the reverse order when the type is formed.
A high-resistance buried semiconductor laser characterized in that a conductive type semiconductor is formed and a p-type semiconductor layer is provided between an n-type semiconductor cladding layer on the side surface of the striped mesa and the semi-insulating semiconductor layer.
導体活性層および第2導電型半導体クラッド層からなる
半導体層を形成する工程と、前記活性層を含む半導体層
を、ストライプ状の絶縁膜をマスクにしてエッチングし
メサを形成する工程と、前記基板がp型のときは正孔を
捕獲する準位を有した半絶縁半導体層とp型半導体から
なる半導体埋め込み層をこの順に、前記基板がn型のと
きはこの逆の順に、埋め込み成長により形成すると同時
にその埋め込み成長中にp型半導体層中のp型不純物の
拡散により前記ストライプ状のメサの側面のn型半導体
クラッド層との界面で前記半絶縁半導体がp型に変わる
工程と、前記絶縁膜を除去した後に第2導電型半導体層
を全面に成長する工程とを含むことを特徴とする高抵抗
埋め込み半導体レーザの製造方法。(2) Forming a semiconductor layer consisting of at least a semiconductor active layer and a second conductivity type semiconductor cladding layer on a first conductivity type semiconductor semiconductor substrate, and forming a striped insulating film on the semiconductor layer including the active layer. The substrate is etched using a mask to form a mesa, and when the substrate is a p-type, a semi-insulating semiconductor layer having a hole capturing level and a semiconductor buried layer consisting of a p-type semiconductor are formed in this order. In the case of n-type, in the reverse order, it is formed by buried growth, and at the same time, during the buried growth, the p-type impurity in the p-type semiconductor layer is diffused, so that the interface with the n-type semiconductor cladding layer on the side surface of the striped mesa is formed. A method for manufacturing a high-resistance buried semiconductor laser, comprising the steps of changing the semi-insulating semiconductor to p-type, and growing a second conductivity type semiconductor layer over the entire surface after removing the insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1219017A JP2550718B2 (en) | 1989-08-25 | 1989-08-25 | High-resistance embedded semiconductor laser and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1219017A JP2550718B2 (en) | 1989-08-25 | 1989-08-25 | High-resistance embedded semiconductor laser and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0382184A true JPH0382184A (en) | 1991-04-08 |
JP2550718B2 JP2550718B2 (en) | 1996-11-06 |
Family
ID=16728950
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013182976A (en) * | 2012-03-01 | 2013-09-12 | Mitsubishi Electric Corp | Buried type optical semiconductor element |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5390786A (en) * | 1977-01-20 | 1978-08-09 | Matsushita Electric Ind Co Ltd | Semiconductor light emitting device and its production |
JPS61290790A (en) * | 1985-06-18 | 1986-12-20 | Fujitsu Ltd | Manufacture of light-emitting element |
JPS63133587A (en) * | 1986-11-25 | 1988-06-06 | Nec Corp | Buried structure semiconductor laser |
JPH02283085A (en) * | 1989-04-25 | 1990-11-20 | Oki Electric Ind Co Ltd | Semiconductor laser |
-
1989
- 1989-08-25 JP JP1219017A patent/JP2550718B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5390786A (en) * | 1977-01-20 | 1978-08-09 | Matsushita Electric Ind Co Ltd | Semiconductor light emitting device and its production |
JPS61290790A (en) * | 1985-06-18 | 1986-12-20 | Fujitsu Ltd | Manufacture of light-emitting element |
JPS63133587A (en) * | 1986-11-25 | 1988-06-06 | Nec Corp | Buried structure semiconductor laser |
JPH02283085A (en) * | 1989-04-25 | 1990-11-20 | Oki Electric Ind Co Ltd | Semiconductor laser |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013182976A (en) * | 2012-03-01 | 2013-09-12 | Mitsubishi Electric Corp | Buried type optical semiconductor element |
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Publication number | Publication date |
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JP2550718B2 (en) | 1996-11-06 |
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