JPH0381839A - Method for resetting system - Google Patents

Abstract

PURPOSE:To improve the reliability of the whole system by preparing timer circuits corresponding to respective programs, surely detecting program runaway in each program processing operation, and outputting a system reset signal. CONSTITUTION:The timer circuits 111 to 11n corresponding to n programs for processing process data inputted from a plant are connected and respective detection start signals SA1 to SAn, detection end signals ED1 to EDn and timer reset signals TR1 to TRn are inputted to these timer circuits 111 to 11n. Each timer circuit counts up the time required from the start of processing operation of its corresponding program up to the processing operation end and when the required time exceeds the allowable time, a program set signal PR1 or PRn is outputted. The output signal is used as the system reset signal SR of the whole system as it is through an OR circuit 12. Even if program runaway occurs in plural programs, each of them surely is detected and the signal SR is outputted, so that the reliability of the whole system sharply is improved.

Description

[Detailed Description of the Invention] [Effects of the Invention] (Industrial Application Field) The present invention relates to a system reset method in an information processing system such as a computer that includes a plurality of programs. The present invention relates to a system reset method that detects whether or not program runaway has occurred, reliably detects program runaway, and outputs a system reset signal.

(Prior Art) For example, in a process control system installed in a factory, etc., various data processes are sequentially executed on process data outputted from the plant as a control target, for example, at regular intervals T0. , calculates the control amount to be finally sent to the plant. In this case, generally a plurality of independent programs are stored for each type of data processing, and when data processing by one program is completed, the next program is started to execute the next data processing.

Note that for programs that can process data in parallel, a plurality of programs may be processed in parallel.

In such a process control device, the control amount, which is the result of data processing, has a constant period T. If the output is not output every time, the program is likely to run out of control. When program runaway occurs, there is a concern that an incorrect data processing result will be output at a certain point beyond the fixed period T0, and an incorrect control amount will be sent to the plant.

To prevent this from happening, generally, a process control system outputs a system reset signal that detects when a program has run out of control and forcibly returns the processing operating state of all programs to their initial state. Built-in system reset function.

FIGS. 9 and 10 are circuit diagrams and time charts specifically showing the system reset function described above. That is, within the timer circuit 1, there is a counting section 2. consisting of a counter.
An oscillator 3 that outputs a clock signal to the counting section 2, a detection level storage section 4, a comparison section 5, and the like are incorporated. Then, a timer reset signal TRT is output to the counter 2 prior to the start of a series of program processing operation states. When a series of program processing operations is completed and new process data is input, the timer reset signal TR↑ is output again before starting a series of program processing operations for this process data.

Therefore, when a series of programs are operating in order and normally, the timer reset signal TRT is manually inputted to the counting section 2 at regular intervals T0.

Therefore, when the timer reset signal TR is inputted, the counting section 2 clears the count value of the number of clocks of the clock signal inputted from the oscillator 3 to zero. Then, counting of the number of clocks is started again from O.

The count value CN is input to the comparator 5, and the detection level storage unit 4
It is compared with the tolerance value LDT stored in . This allowable value LDT is set in advance in the detection level storage section 4 using the detection level signal LDT. The allowable value LDA is a normal cycle T. As long as the timer reset signal TR is being input, the count value CN is set to a value that will not be reached.

Therefore, under normal conditions, the count value CN is the allowable value L
Since it is smaller than D↑, the system reset signal SR is not outputted from the comparator 5.

Here, for example, if the processing operation of one program moves to another processing step, or the contents of one program are rewritten due to external noise, the program processing operation may diverge, and the required time will be It will not end within Therefore, the series of program processing operations will not be completed within the permissible time, the above-mentioned timer reset signal TRT will not be output, and the count value CN of the counting unit 3 will not exceed the permissible value LD〒 stored in the detection level storage unit 4. exceed. As a result, the timer circuit 1 outputs a high (H) level system reset signal SR.

However, the system reset method having the configuration shown in FIGS. 9 and 10 still has the following problems.

That is, as described above, the allowable value LD set in the detection level storage section 4 is a value set with a margin in mind for the time required from the start to the end of a series of program processing operations. Therefore, it is not an acceptable value for the time required for each individual program.

Therefore, for example, even if one program runs out of control and the required time for that program becomes significantly longer than the specified required time, if some abnormality occurs in another program and the required time becomes shorter. In this case, both required times are canceled out, and the count value CN corresponding to the total required time is the allowable value LD.

The following may occur. In such a case, timer circuit 1
does not output the system reset signal SR.

Therefore, it is considered that each program has processed normally. However, in reality, the input process data is incorrectly processed.

(Problem to be Solved by the Invention) As described above, according to the conventional system reset method, a series of programs consisting of multiple programs is regarded as one program, and the allowable time is set according to the total time required. Since the presence or absence of program runaway was monitored based on the total allowable time, there was a problem in that program runaway could not be accurately detected when abnormalities occurred in multiple programs at the same time.

The present invention was made in view of these circumstances, and
By providing a timer circuit for each program, we can reliably detect program runaway during each program processing operation, and provide a system reset method that can greatly improve the reliability of the entire system by immediately outputting a system reset signal. The purpose is to

C Configuration of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention detects runaway program processing when program processing runs out of control in the processing execution process of each program in a plurality of programs. In the system reset method that outputs a reset signal, it is provided for each program and measures the time required from the start of the processing operation to the end of the processing operation of the corresponding program, and when the required time exceeds a predetermined allowable time, the program It includes a plurality of timer circuits that output reset signals, and an OR circuit that outputs a logical sum signal of program reset signals output from each of the timer circuits as a system reset signal.

Further, in another invention, in addition to the above-mentioned means, each allowable time set in advance for each timer circuit can be set for each timer according to the processing content of each program.

(Operation) According to the system reset method configured in this way,
A timer circuit is provided for each program to measure the time required from the start of the processing operation to the end of the processing operation of the corresponding program, and when the required time exceeds the allowable time, a program reset signal is output. Then, this program reset signal directly becomes the entire system reset signal via the OR circuit.

That is, even if multiple programs are progera at the same time,
Even if a system runaway occurs, it is reliably detected and a system reset signal is output.

Further, in another invention, an allowable time is set in each timer circuit for each program according to the processing content of that program. In other words, it is possible to support a system in which various programs with different processing contents and processing times are incorporated under optimal conditions.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the system reset method of the embodiment. Note that to simplify the explanation, a case will be described in which the present invention is incorporated into a process control system.

A timer circuit 1 is provided for each of n programs (1) to (n) that process process data input from the plant.
1. ~11. are provided, and each timer circuit 11+~
11. , detection level signal LD, detection start signal SA, -8A, detection end signal ED, ~ED, , respectively.
A timer reset signal TRl-TR is input. And each timer circuit 11□-11. Each program reset signal PR, -PR is output when a program runs out of control.

is outputted as a system reset signal SR via one OR circuit 12. In addition, each timer circuit 111 to 1
1. A clock signal a is input from the oscillator 13 to the oscillator 13.

The timer circuit 111 is configured as shown in FIG. For example, a detection start signal SA indicating the start of the processing operation for the corresponding program (1) output from a processor (not shown) is inputted to the set terminal S of the flip-flop 14, and a detection signal SA indicating the end of the processing operation for the corresponding program (1) is also detected. End signal EN1 is sent to flip-flop 14
It is input to the reset terminal R of. flip flop 14
The output signal from the output terminal Q is input to the gate terminal G of the counting section 15 formed by a counter.

A clock signal a is input from the oscillator 13 to the clock terminal CP of the counting section 15 . The counting unit 15 receives the output signal SugaH of the flip-flop 14 which is input to the gate terminal G.
During the level period, the number of clocks of the clock signal a applied to the clock terminal CP is counted and the counted value CN is sent to the next comparator 16.

Further, the detection end signal EN is inputted to the reset terminal R of the counting section 15 via the OR gate 17.゛Also,
A timer reset signal TR is inputted to this reset terminal R from the aforementioned processor via the OR gate 17. The counting section 15 resets the count value CN to O when an H level signal is input to the reset terminal R.

Further, a detection level signal LD is input from the processor to the detection level storage section 18. The detection level storage unit 18 stores a tolerance value LD corresponding to the tolerance time set by the detection level signal LD, and sends it to the comparator 16. The comparator 16 compares the input count value CN and the allowable value LD, and when the count value CN exceeds the allowable value LD, outputs an H level program reset signal PR. Note that the allowable value LD is set to a value corresponding to the allowable time obtained by adding a predetermined grace time to each predetermined required time for executing each of the programs (1) to (n). In this embodiment, the time is set to approximately twice the predetermined required time.

Note that the other timer circuits 11□ to 117 also have the same configuration.

In a system reset method having such a circuit configuration, when process data is input, a processor (not shown) executes each program (1) to (1) in a predetermined order.
n) in sequence. Furthermore, for programs that can be processed in parallel, multiple programs are executed simultaneously. Each of the programs (1) to (n) is executed according to the flowchart shown in FIG.

In other words, when executing one program, S(
In step) 1, the detection level signal LD is sent to the timer circuit 11 corresponding to the corresponding program. Next, in S2, a detection start signal SA is similarly sent to the corresponding timer circuit 11. Thereafter, in S3, execution processing for the corresponding program is executed. When the processing of the corresponding program is completed, a detection end signal SEN is outputted to the corresponding timer circuit 11 at 84.

FIG. 4 is a time chart showing the operation of the timer circuit 111 corresponding to, for example, program (1).

In a state where process data is being input at a predetermined period T0, program (1) is also started at a predetermined period T0. In a normal case, the time required for the program processing operation does not exceed the allowable time, so the comparator 16 never outputs the program reset signal PR at the H level. However, if the corresponding program (1) goes out of control for some reason, the detection end signal EN is not output, so the counter 15 is not reset and the count value CN exceeds the allowable value LD, causing the comparator 16 to output the program. A reset signal PR is output.

Timer circuit 11. The program reset signal PRr outputted from the logical sum circuit 12 is outputted as a system reset signal SR. When the system reset signal S is output, all programs (1) to (n) including the currently executing program return to their initial states.

Similar processing operations are performed for other programs (2) to (n).

In this way, the timer circuits 111 to 11 . By providing , program runaway is detected for each program, and
A system reset signal SR is output.

Therefore, unlike the conventional method, program abnormalities occur in multiple programs at the same time, and each program abnormality cancels out each other.As a result, the time required for a series of program processing operations falls within the allowable time, and the program abnormality occurs. It is possible to avoid the situation of not being detected.

Therefore, the reliability of the system to which this system reset method is applied can be greatly improved.

Note that various circuits other than the embodiment shown in FIG. 2 are conceivable for the timer circuit 11. For example, it is also possible to fix the gate terminal G of the counting section 15 at H level and apply the AND signal of the output signal of the flip-flop 14 and the clock signal a of the oscillator 13 to the clock terminal CP.

Further, in the embodiment, the flip-flop 14. Counting part 15
．． Detection level storage unit 18. Although the comparator 16 is constructed of individual circuit members, a subtraction counter whose initial value can be preset may also be used.

In this case, an allowable value LD is set as the initial value, and this initial value LD is subtracted using the clock signal a.

Then, when the detection end signal EN is input to the reset terminal R, the count value CN is returned to the initial value LD. Furthermore, when the count value CN is subtracted to 0, a program reset signal PR is output.

FIG. 5 is a flowchart showing program control on the processor side showing a system reset method according to another embodiment of the present invention. Note that each circuit configuration is the same as in FIGS. 1 and 2.

When the flowchart starts, a detection end signal EN is sent to the timer circuit 11 corresponding to the program to be executed in S5. Next, a detection level signal LDP corresponding to a predetermined required time of the program is sent to the detection level storage section 18.
Set the allowable value LD to . Next, a detection start signal SA is sent out, and the processing of the corresponding program is executed. When the program processing is completed, a detection end signal EN is sent.

Next, in S6, the detection level signal LD corresponding to the program start grace time is sent to the detection level storage unit 1.
Set the allowable value LDI to 8. Next, in S7, a detection start signal SA is sent out.

If the next process data is input in S8, the process returns to S5, outputs the detection end signal EN, and starts program processing for the next data process.

Note that if the next process data is not input in S8, either the process control system itself has stopped or the process data input has been stopped, so the detection completion signal EN is output to stop this abnormality detection operation.

FIG. 6 shows each signal LDp,
Timer circuit 11 when sending LDt, SA, and ED
3 is a time chart showing the operation of FIG.

If the system reset method has such a configuration, if the time from the completion of the program processing operation for one process data to the start of the program processing operation for the next process data exceeds the allowable time, something will happen. It is determined that an error has occurred and the program has not been started, and the program reset signal P is sent as in the case of program runaway.
R is output.

That is, in this embodiment, if an abnormality occurs during the program processing operation period and the program processing operation stop period, the system reset signal SR is output, so that the reliability of the entire system can be further improved.

FIG. 7 is a flowchart showing program control on the processor side, showing a system reset method according to yet another embodiment of the present invention. Note that each circuit configuration is the same as in FIGS. 1 and 2.

In this embodiment, each timer circuit 11.corresponds to each program (1) to (n). ~11. Each program (1>~
It is set for each program (1) to (n) according to the processing content and processing operation time of (n).

That is, when the flowchart is started, the program to be executed this time is determined in S9, and when the program to be executed is determined, the detection level signal LD corresponding to the permissible time set in advance for the corresponding program is sent to the corresponding timer. circuit 11
to the detection level storage unit 18 and store the corresponding tolerance value L in the detection level storage unit 18.
Set D.

In this way, the optimal allowable time LD, ~LD, can be set for each program (1) to (n), so when processing process data, the optimal processing length corresponding to each data processing can be set. This makes it possible to design a program that is easy to use.

By the way, the allowable time for all programs (1) to (n)
If a constant value LD is set for a long time, program runaway occurs in each program and the time until the system reset signal SR is output is not constant, so some programs may remain in a runaway state for a long time. , there were concerns that it would have a negative impact on other programs during that time. Therefore, in the conventional system, it is necessary to design each program so that the time required for each program does not vary greatly.

FIG. 8 is a flowchart showing program control on the processor side, showing a system reset method according to yet another embodiment of the present invention. Note that each circuit configuration is the same as in FIGS. 1 and 2.

This example shows a case where each program (1) to (n) is executed in chronological order, and each program (X)
, (Y), and (Z) are relatively long, and the required times are significantly different.

Therefore, the corresponding tolerance value LDx for each program,
The values of LDy and LDz are different.

That is, when the flowchart is started, in S10, the detection level signal LDX corresponding to the predetermined required time of the first program (X) is sent to the timer circuit 11x corresponding to the program.
Send to. Then, a detection start signal SA is sent to the corresponding timer circuit 11x, and the actual program (X) is processed. When the program processing is completed, the corresponding timer circuit 11
A detection end signal EN is sent to x.

Since the processing for one program (X) has been completed above, the program processing for the next program (Y) is started in S11. Then, when the program processing for the program (Y) is completed in the same procedure, the program processing for the final program (Z) is executed from S12 onwards.

Next, the feature of detecting program runaway when each program is executed in chronological order as described above will be explained.

For example, each program (X), (Y), (Z)
The required time is 5ss, 1sec, 1, respectively.
In the case of a large distance of 0 sec, the total required time is 11.05 sec. In this case, according to the conventional method shown in FIG. 9, the total allowable time is, for example, 15
sec.

In this case, program (X) is executed first, so
If program runaway occurs in program (X),
The system reset signal SR will be output about 15 seconds after the runaway occurs. Since the runaway state continues for these 15 seconds, there is a concern that an incorrect control amount may be sent to the plant during those 15 seconds.

However, in the embodiment shown in FIG. 8, each program (X), (Y), (Z)
and each program (X), (Y), (
By setting each allowable time corresponding to the required time of the program for each program (Z), even if a program runaway occurs, the duration of the program runaway can be minimized. Therefore, the safety of the system can be further improved.

[Effects of the Invention] As explained above, according to the system reset method of the present invention, a timer circuit is provided for each program to measure the time required from the start of the program processing operation to the end of the processing operation, and the required time is set to the allowable time. When the limit is exceeded, a system reset signal is sent. Therefore, it is possible to reliably detect each program runaway during each program processing operation, and by immediately outputting a system reset signal, all programs can be forcibly returned to their initial state, greatly improving the reliability of the entire system. You can improve.

Further, by setting a permissible time for each program, program runaway can be detected in a shorter time, and the reliability can be further improved.

[Brief explanation of drawings]

1 to 4 show a system reset method according to an embodiment of the present invention, FIG. 1 is a block diagram showing the overall configuration, FIG. 2 is a block diagram showing a timer circuit, 3 is a flowchart showing the operation, FIG. 4 is a time chart showing the operation, FIG. 5 is a flowchart showing the operation of the system reset method according to another embodiment of the present invention, and FIG. 6 is the method of the same embodiment. 7 and 8 are flowcharts showing the operation of a system reset method according to still another embodiment of the present invention, and FIG. 9 is a block diagram showing the conventional system reset method, and FIG. 10
The figure is a time chart showing the operation of the conventional method. 11□〜11. ... timer circuit, 12 ... OR circuit, 13 ... oscillator, 14 ... flip-flop,
15... Counting section, 16... Comparing section, 17... Orate, 18... Detection level storage section.

Claims (2)

[Claims] (1) In a system reset method that detects program runaway when program processing runs out of control during the processing execution process of each program in a plurality of programs and outputs a system reset signal, a system reset signal is provided for each program.
A plurality of timer circuits that measure the time required from the start of the processing operation to the end of the processing operation of the applicable program and output a program reset signal when the required time exceeds a predetermined allowable time, and an output from each of these timer circuits. A system reset method that includes an OR circuit that outputs an OR signal of program reset signals that are output as a system reset signal. (2) The system reset method according to claim 1, wherein each allowable time set in advance for each timer circuit is set for each timer according to the processing content of each program.