JPH02114339A - Cpu monitoring device - Google Patents

Abstract

PURPOSE:To reduce the size of a program by comparing the address of an address signal outputted from a CPU with a previously stored corresponding address in the order of execution, and at the time of coincidence of both values, returning a clock part to an initial value, measuring time and then outputting a CPU reset signal after the passage of a prescribed time. CONSTITUTION:The title device is constituted so as to monitor the runaway of the CPU 1 by monitoring whether the order of the address of an address signal outputted from the CPU 1 is normal or not. Time previously set up in the clock part 4 is set up to a value larger than the maximum execution time from one address stored in a code string coincidence detecting means 3 up to the next address at the time of executing a program normally. Therefore, when the execution order is deviated from the array of program size instructions, an address signal AD corresponding to the succeeding address is not inputted, so that the signal is inputted with a large delay from the previously determined time. Consequently, a CPU reset signal is outputted from the clock part 4, the runaway of the CPU 16 can be detected and the program size can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CPU monitoring device, and more particularly to a CPU monitoring device for monitoring CPU runaway in a microcomputer system.

[Conventional technology]

In a microcomputer system, noise or other causes may cause the CPU to deviate from the sequence of instruction codes (program) that is originally supposed to be executed, causing the CPU to run out of control.

Conventionally, in order to monitor such phenomena in microcomputer systems, the CPU
A clock section that resets the clock section and a reset instruction that resets this clock section are included in a complex part of the program, and if this reset instruction is not output for a certain period of time, it is assumed that the CPU has gone out of control and the CPU is reset. Ta.

Moreover, it must be confirmed that these reset instructions are not executed independently, but in order. For this reason, an instruction to write into memory that the part of the reset instruction has been executed is placed immediately adjacent to each reset instruction, and an instruction to detect that the immediately previous reset instruction part has been executed.

(IEICE Fault Tolerant System Study Group Material, FTS87-28, January 1988) It is usually necessary to arrange about four instructions to check the execution order before and after these reset instructions.

[Problem to be solved by the invention]

The conventional CPU monitoring device described above has a configuration in which reset commands are inserted in multiple places in a program, and the CPU is reset if the reset commands are not output for a certain period of time, and the execution order of these reset commands is determined. Since about four instructions are placed before and after these reset instructions for confirmation, there are disadvantages in that the program size increases and the overhead in execution time cannot be ignored.

An object of the present invention is to provide a CPU monitoring device that can reduce program size and reduce execution time overhead.

[Means to solve the problem]

The CPU monitoring device of the present invention includes a storage unit that stores a predetermined program and sequentially reads each instruction of the program according to an address signal from the CPU, and a predetermined number of the program when the program is normally executed. A symbol that stores in advance a plurality of addresses in which instructions are stored in the order of execution, compares the address of the address signal with the corresponding address stored in advance in the order of execution, and outputs a match detection signal when they match. a column coincidence detection means; and a clock section that returns to the initial value each time the coincidence detection signal is input, measures the time since the coincidence detection signal is input, and outputs a CPU reset signal when a predetermined time elapses. It has

[Effect]

In the present invention, runaway of the CPU is monitored based on whether or not the address order of address signals output from the CPU is normal, so the reset instruction and the execution order of this reset instruction are included in the program. There is no need for a confirmation instruction, so overhead can be eliminated and the program size can be reduced.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In this embodiment, a predetermined program is stored and the CP
a storage unit 2 that sequentially reads each instruction IN of the program according to an address signal AD from the UI and transmits it to the CPU 1;
A plurality of addresses where predetermined instructions of this program are stored when the program is normally executed are stored in advance in the order of execution, and the address of the address signal AD and this pre-stored corresponding address are stored in advance. symbol string coincidence detection means 3 which compares the symbols in execution order and outputs a coincidence detection signal DS when they match;
The clock section 4 measures the time since input of the CPU 1 and outputs a CPU reset signal R3 that returns the CPU to a specific state when a predetermined time has elapsed.

The predetermined time of the clock unit 4 is set to be larger than the maximum execution time from one address to the next address stored in the symbol string match detection means 3 when the program is normally executed. has been done.

Therefore, if the execution order deviates from the sequence of instructions in the program, the address signal AD corresponding to the next address will not be input or will be input much later than a predetermined time. A reset signal R3 is output, and runaway of the CPU 16 can be detected. Further, a state in which the CPU reset signal R3 is not output indicates that the programs are being executed normally in order.

The details of the symbol string coincidence detection means 3 are described in Japanese Patent Application No. 60-18110 and Japanese Patent Application No. 60-235755, which have already been filed by the present applicant.

Further, the clock section 4 can be easily configured using a monostable multivibrator, a counter/timer LSI for peripheral use in a microprocessor, or the like.

〔Effect of the invention〕

As explained above, the present invention stores in advance the addresses of a plurality of predetermined instructions of a program stored in a storage unit in the normal execution order, and stores the addresses of an address signal from the CPU in advance. Compare the corresponding addresses in the order of execution, and when they match, output a match detection signal to return the clock to the initial value and measure time, and when this measurement time has passed a predetermined time, output a CPU reset signal. With this configuration, there is no need to incorporate a runaway detection instruction into the program as in the conventional case, so the program size can be reduced and execution time overhead can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...CPU, 2...Storage part, 3...Symbol string coincidence detection means, 4...Clock part.

Claims (1)

[Claims] A storage unit that stores a predetermined program and sequentially reads each instruction of the program according to an address signal from the CPU, and an address where the predetermined instructions of this program are stored when the program is normally executed. symbol string coincidence detection means for storing a plurality of symbols in advance in the order of execution, comparing the address of the address signal with the corresponding address stored in advance in the order of execution and outputting a coincidence detection signal when they match; The device is characterized by having a clock unit that returns to the initial value each time a detection signal is input, measures the time since the coincidence detection signal is input, and outputs a CPU reset signal when a predetermined time has elapsed. C
PU monitoring device.