JPH0381340B2 - - Google Patents

Info

Publication number
JPH0381340B2
JPH0381340B2 JP57165360A JP16536082A JPH0381340B2 JP H0381340 B2 JPH0381340 B2 JP H0381340B2 JP 57165360 A JP57165360 A JP 57165360A JP 16536082 A JP16536082 A JP 16536082A JP H0381340 B2 JPH0381340 B2 JP H0381340B2
Authority
JP
Japan
Prior art keywords
phase
clock
station
master station
slave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57165360A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5954343A (ja
Inventor
Susumu Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16536082A priority Critical patent/JPS5954343A/ja
Publication of JPS5954343A publication Critical patent/JPS5954343A/ja
Publication of JPH0381340B2 publication Critical patent/JPH0381340B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
JP16536082A 1982-09-22 1982-09-22 時分割多方向通信方式 Granted JPS5954343A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16536082A JPS5954343A (ja) 1982-09-22 1982-09-22 時分割多方向通信方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16536082A JPS5954343A (ja) 1982-09-22 1982-09-22 時分割多方向通信方式

Publications (2)

Publication Number Publication Date
JPS5954343A JPS5954343A (ja) 1984-03-29
JPH0381340B2 true JPH0381340B2 (enExample) 1991-12-27

Family

ID=15810883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16536082A Granted JPS5954343A (ja) 1982-09-22 1982-09-22 時分割多方向通信方式

Country Status (1)

Country Link
JP (1) JPS5954343A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2545787B2 (ja) * 1986-02-13 1996-10-23 日本電気株式会社 多方向多重無線通信方式
JPH05308336A (ja) * 1992-04-28 1993-11-19 Kokusai Electric Co Ltd 時分割多重信号受信回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56168455A (en) * 1980-05-08 1981-12-24 Fujitsu Ltd Time-division and multidirection communication system

Also Published As

Publication number Publication date
JPS5954343A (ja) 1984-03-29

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