JPH0381178B2 - - Google Patents

Info

Publication number
JPH0381178B2
JPH0381178B2 JP60119642A JP11964285A JPH0381178B2 JP H0381178 B2 JPH0381178 B2 JP H0381178B2 JP 60119642 A JP60119642 A JP 60119642A JP 11964285 A JP11964285 A JP 11964285A JP H0381178 B2 JPH0381178 B2 JP H0381178B2
Authority
JP
Japan
Prior art keywords
registers
graph manager
node
graph
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60119642A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6134629A (ja
Inventor
Rii Rotsugusudon Gearii
Robaato Sheiberu Maaku
Arubaato Uiriamuzu Junia Furanku
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of JPS6134629A publication Critical patent/JPS6134629A/ja
Publication of JPH0381178B2 publication Critical patent/JPH0381178B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4494—Execution paradigms, e.g. implementations of programming paradigms data driven

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
JP11964285A 1984-06-05 1985-05-31 グラフマネジャー Granted JPS6134629A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US617526 1984-06-05
US06/617,526 US4644464A (en) 1984-06-05 1984-06-05 Graph manager for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

Publications (2)

Publication Number Publication Date
JPS6134629A JPS6134629A (ja) 1986-02-18
JPH0381178B2 true JPH0381178B2 (enExample) 1991-12-27

Family

ID=24473991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11964285A Granted JPS6134629A (ja) 1984-06-05 1985-05-31 グラフマネジャー

Country Status (4)

Country Link
US (1) US4644464A (enExample)
EP (1) EP0164996A3 (enExample)
JP (1) JPS6134629A (enExample)
CA (1) CA1229175A (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8316463D0 (en) * 1983-06-16 1983-07-20 Secr Defence Priority resolution in bus oriented computer systems
US4654780A (en) * 1984-06-05 1987-03-31 Burroughs Corporation Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
US4615003A (en) * 1984-06-05 1986-09-30 Burroughs Corporation Condition concentrator and control store for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
US4734848A (en) * 1984-07-17 1988-03-29 Hitachi, Ltd. Combination reduction processing method and apparatus
US5047918A (en) * 1985-12-31 1991-09-10 Tektronix, Inc. File management system
US4922413A (en) * 1987-03-24 1990-05-01 Center For Innovative Technology Method for concurrent execution of primitive operations by dynamically assigning operations based upon computational marked graph and availability of data
SE9002558D0 (sv) * 1990-08-02 1990-08-02 Carlstedt Elektronik Ab Processor
DE4430195B4 (de) * 1993-12-13 2004-09-23 Hewlett-Packard Co. (N.D.Ges.D.Staates Delaware), Palo Alto Verfahren zur Auswertung von Booleschen Ausdrücken

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU613401A1 (ru) * 1976-07-07 1978-06-30 Предприятие П/Я В-2892 Запоминающее устройство
US4463421A (en) * 1980-11-24 1984-07-31 Texas Instruments Incorporated Serial/parallel input/output bus for microprocessor system
IT1134780B (it) * 1980-12-18 1986-08-13 Honeywell Inf Systems Unita' di controllo microprogrammata con rete di salti multipli
US4447875A (en) * 1981-07-07 1984-05-08 Burroughs Corporation Reduction processor for executing programs stored as treelike graphs employing variable-free applicative language codes
JPS60119644A (ja) * 1983-12-01 1985-06-27 Toshiba Corp 光学ヘッド
JPS60119643A (ja) * 1983-12-01 1985-06-27 Matsushita Electric Ind Co Ltd 光検出器
US4654780A (en) * 1984-06-05 1987-03-31 Burroughs Corporation Parallel register transfer mechanism for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes
US4615003A (en) * 1984-06-05 1986-09-30 Burroughs Corporation Condition concentrator and control store for a reduction processor evaluating programs stored as binary directed graphs employing variable-free applicative language codes

Also Published As

Publication number Publication date
EP0164996A3 (en) 1989-08-30
JPS6134629A (ja) 1986-02-18
US4644464A (en) 1987-02-17
EP0164996A2 (en) 1985-12-18
CA1229175A (en) 1987-11-10

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