JPH038105B2 - - Google Patents

Info

Publication number
JPH038105B2
JPH038105B2 JP56126531A JP12653181A JPH038105B2 JP H038105 B2 JPH038105 B2 JP H038105B2 JP 56126531 A JP56126531 A JP 56126531A JP 12653181 A JP12653181 A JP 12653181A JP H038105 B2 JPH038105 B2 JP H038105B2
Authority
JP
Japan
Prior art keywords
film
region
epitaxial layer
area
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56126531A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5827341A (ja
Inventor
Tadashi Kirisako
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56126531A priority Critical patent/JPS5827341A/ja
Publication of JPS5827341A publication Critical patent/JPS5827341A/ja
Publication of JPH038105B2 publication Critical patent/JPH038105B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
JP56126531A 1981-08-11 1981-08-11 半導体装置の製造方法 Granted JPS5827341A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56126531A JPS5827341A (ja) 1981-08-11 1981-08-11 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56126531A JPS5827341A (ja) 1981-08-11 1981-08-11 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5827341A JPS5827341A (ja) 1983-02-18
JPH038105B2 true JPH038105B2 (enrdf_load_stackoverflow) 1991-02-05

Family

ID=14937503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56126531A Granted JPS5827341A (ja) 1981-08-11 1981-08-11 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5827341A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5780352A (en) * 1995-10-23 1998-07-14 Motorola, Inc. Method of forming an isolation oxide for silicon-on-insulator technology

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51146186A (en) * 1975-06-11 1976-12-15 Hitachi Ltd Diode device fabrication method
US4289550A (en) * 1979-05-25 1981-09-15 Raytheon Company Method of forming closely spaced device regions utilizing selective etching and diffusion

Also Published As

Publication number Publication date
JPS5827341A (ja) 1983-02-18

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