JPH038105B2 - - Google Patents
Info
- Publication number
- JPH038105B2 JPH038105B2 JP56126531A JP12653181A JPH038105B2 JP H038105 B2 JPH038105 B2 JP H038105B2 JP 56126531 A JP56126531 A JP 56126531A JP 12653181 A JP12653181 A JP 12653181A JP H038105 B2 JPH038105 B2 JP H038105B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- epitaxial layer
- area
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Weting (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56126531A JPS5827341A (ja) | 1981-08-11 | 1981-08-11 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56126531A JPS5827341A (ja) | 1981-08-11 | 1981-08-11 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5827341A JPS5827341A (ja) | 1983-02-18 |
JPH038105B2 true JPH038105B2 (enrdf_load_stackoverflow) | 1991-02-05 |
Family
ID=14937503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56126531A Granted JPS5827341A (ja) | 1981-08-11 | 1981-08-11 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5827341A (enrdf_load_stackoverflow) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5780352A (en) * | 1995-10-23 | 1998-07-14 | Motorola, Inc. | Method of forming an isolation oxide for silicon-on-insulator technology |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51146186A (en) * | 1975-06-11 | 1976-12-15 | Hitachi Ltd | Diode device fabrication method |
US4289550A (en) * | 1979-05-25 | 1981-09-15 | Raytheon Company | Method of forming closely spaced device regions utilizing selective etching and diffusion |
-
1981
- 1981-08-11 JP JP56126531A patent/JPS5827341A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5827341A (ja) | 1983-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0724291B1 (en) | Semiconductor device having an improved trench isolation and method for forming the same | |
JP2679639B2 (ja) | 半導体装置及びその製造方法 | |
EP0782185B1 (en) | Process of fabricating semiconductor device having isolating oxide rising out of groove | |
JPH0355984B2 (enrdf_load_stackoverflow) | ||
US4871684A (en) | Self-aligned polysilicon emitter and contact structure for high performance bipolar transistors | |
JP3039978B2 (ja) | 集積misfetデバイス中に電界分離構造及びゲート構造を形成する方法 | |
JPS6252950B2 (enrdf_load_stackoverflow) | ||
JPH0482180B2 (enrdf_load_stackoverflow) | ||
US5763316A (en) | Substrate isolation process to minimize junction leakage | |
JPH038105B2 (enrdf_load_stackoverflow) | ||
US4469535A (en) | Method of fabricating semiconductor integrated circuit devices | |
KR0140444B1 (ko) | 바이폴라 소자 제조방법 | |
JP3360970B2 (ja) | 半導体装置の製造方法 | |
JP3224320B2 (ja) | 半導体素子の製造方法 | |
JPH04279045A (ja) | フィールド酸化膜形成方法 | |
JP2763105B2 (ja) | 半導体装置の製造方法 | |
JP2723539B2 (ja) | マスタースライス型半導体装置 | |
KR950010878B1 (ko) | 바이폴라 트랜지스터 제조방법 | |
JPH0136709B2 (enrdf_load_stackoverflow) | ||
JPS6239538B2 (enrdf_load_stackoverflow) | ||
JPH04361533A (ja) | 半導体集積回路装置の製造方法 | |
JPH0117256B2 (enrdf_load_stackoverflow) | ||
JPH0235465B2 (enrdf_load_stackoverflow) | ||
JPS58175843A (ja) | 半導体集積回路の製造方法 | |
JPS6185839A (ja) | 半導体集積回路の製造方法 |