JPH0380340A - Information processor having input/output device simulating function - Google Patents

Abstract

PURPOSE:To minimize the deterioration of the output access speed due to the wait by providing an access end factor selection means into a transfer means to select the access end factors of the output accesses produced from an access means in the holding order of output access end factor signals. CONSTITUTION:A simulation means sets the value to an output access end factor holding means 7 to show the end of a data transfer operation to the simulation means when the synchronization is needed with an output access of a processor 1. When no synchronization is needed, the simulation means sets the value to the means 7 to show that the output access contents are stored by a transfer means 4. When the processor has an output access to a similar input/output device 13 to be simulated, the means 4 containing an access end factor signal 6 informs an access means 2 of the end of the output access at generation of the factor shown by the value set to the means 7. Thus the output access is completed. Thus it is possible to minimize the deterioration of the output access speed due to the wait.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that controls an input/output device through input/output access of a processor, and particularly to an information processing device that simulates the input/output device.

[Conventional technology]

In order to access an input/output device from a processor, it is necessary to send a command to the input/output device using the processor's input/output access, or to start the input/output device by creating a channel program that can be interpreted by the input/output device. The former method is mainly used in small-scale computer systems such as personal computers, and the latter method is used in relatively large-scale computer systems such as general-purpose computers. Generally, personal computers are provided with various operating systems, but at the same time only a single operating system is available.
Because only one system operated, users using different operating systems had to restart their personal computers each time they changed operating systems. To overcome this inconvenience, multi-OS workstations have emerged that run multiple operating systems simultaneously.

Generally, operating systems are designed to run independently, so sharing input/output devices with other operating systems is not considered. Therefore, in multi-OS workstations, a second As shown in the figure, operating system 1
recognition means 3 that recognizes input/output access from processor 1 running on processor 0 to the input/output device based on the input/output device address issued by access means 2; and a host operating system that runs on host processor 11 and manages the entire workstation. - A delivery means 4 for notifying the system 12 of access contents and for notifying the operating system 10 of processing results, and a simulator for simulating the operation of input/output devices in the host operating system 12 By providing the means 5, input/output access issued by the operating system 10 to the input/output device is simulated.

In such an information processing apparatus, when an input/output access is performed from software running on the processor 1 to an input/output device to be simulated, the operation is as follows. First, the recognition means 3 recognizes the access issued by the processor 1 and activates the transfer means 4 and the simulation means 5. The delivery means 4 is the recognition means 3
When activated by the recognizing means 3, the simulating means 5 issues a wait request to the processor 1 to cause the processor 1 to wait, and also captures the contents of the input/output access being performed by the processor 1. A request is made to the delivery means 4 to deliver the contents of the access. In response to this request, the transfer means 4 transfers the access contents to the simulating means 5. If the access from the processor 1 is an output access, the transfer means 4 transfers the weight to the processor 1 when the transfer operation to the simulating means 5 is completed. Release the request and return to processor 1
restart the process. The simulating means 5 simulates the input/output device according to the access contents passed from the passing means 4.

When the access from the processor 1 is an input access, the simulating means 5 sets in the passing means 4 the result of the simulated operation of the input/output device, that is, the value that the processor 1 should receive by the input access. When the transfer means 4 receives this value, it transfers it to the processor 1, cancels the wait request to the processor 1, and causes the processor 1 to resume processing. Through this series of operations, the software running on the processor 1 can operate without being aware of whether an actual input/output device is connected or an input/output device simulated by the simulating means 5. It makes it possible. In addition,
When simulating input/output device operation in the simulating means 5, a similar input/output bag W, 1 similar to the device to be simulated is used.
3 may be used, or such input/output devices may not be used at all.

Further, by providing the request buffer 18 in the transfer means 4, when the access from the processor 1 is an output access, the output access is completed when the transfer means 4 takes in the content of the output access, and the processor 1
A method has also been proposed that allows processing to be restarted.

In this way, in a multi-OS workstation where the output access issued by the processor is temporarily buffered by the request buffer 18 in the delivery means 4, the output access completion time of the processor and the data delivery from the delivery means 4 to the simulating means 5 are determined. There may be a time lag between the completion times of the

On the other hand, some input/output devices achieve synchronization through output access issued by a processor.

For example, the processor 1 is an input/output device that cancels an interrupt request when a command is issued by output access. In this case, the software running on the processor 1 is created on the premise of synchronization by output access. That is,
It is assumed that the interrupt request is cleared immediately after the processor completes the output access. If such software is run on a conventional multi-OS workstation, it may not work properly due to the time lag mentioned above.
In the S workstation, all output accesses are made to wait until the transfer operation from the transfer means 4 to the simulation means 5 is completed.

[Problem to be solved by the invention]

In a conventional information processing device in which output access is buffered in the transfer means, there is a time difference between the output access completion time issued by the access means of the processor and the completion time of data transfer from the transfer means to the simulation means. occurs. Therefore, in order to run software that accesses input/output devices that are synchronized by output commands issued by the processor, all output accesses have to wait until the completion of the transfer operation from the transfer means to the simulation means. . As a result, there was a problem in that the buffering function of the transfer means did not work effectively.

[Means to solve the problem]

In the present invention, the output access completion factor holding means set by the simulating means is provided, and the delivery means further stores the output access completion factors issued from the access means in the order in which they are held in the output access completion factor means. The above problem is solved by providing an access completion factor selection means for selecting the access completion factor.

[Effect]

In the simulating means, when it is necessary to synchronize with the output access of the processor, the data transfer operation completion 1 for the r simulating means is stored in the output access completion factor holding means.
Set a value that indicates. If this is not the case, the simulating means sets a value indicating storage 1 of the output access contents by the j transfer means in the output access completion factor holding means. When an output access is made from the processor to the input/output device to be simulated, the transfer means that includes the access completion factor selection means generates a factor indicated by the value set in the output access completion factor holding means. At this point, the output access is completed by notifying the access means of the completion of the output access.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, in the information processing apparatus according to this embodiment, an access means 2 inside a processor 1 performs input/output access to an input/output device, and the processor can also receive a wait signal 16. If this signal is active, processor 1 suspends completion of the input/output access until wait signal 16 becomes inactive. Access to the input/output device is performed through a bus connected to the access means 2. The buses include an address bus 14 and a data bus 15. When the processor 1 accesses an input/output device, the access means 2 outputs the address of the input/output device to the address bus 14. This address distinguishes the input/output device to be accessed.

The recognition means 3 and the delivery means 4 are also connected to the bus.

The recognition means 3 constantly monitors the address bus 14,
When output to the address bus 14 of the input/output device to be simulated, by enabling the recognition means output 17,
The delivery means 4 and the simulation means 5 are activated. The delivery means 4 includes a request buffer 18. This allows information indicating the content of the access from processor 1, that is, "the values of address bus 14 and data bus 15, and whether processor 1 is performing an input access or an output access." Buffering is possible. The access contents held in the request buffer 18 are passed to the simulating means 5 in response to a request from the simulating means 5.

The simulation means 5 is built into a host processor 11 that manages the entire system. When the simulation means 5 is activated by the recognition means 3, it receives the access content from the delivery means 4. This interprets input/output accesses issued from processor 1. The simulating means 5 simulates the input/output device according to this interpretation result, and if necessary at this time, operates the similar input/output device 13 that it controls. Further, the simulating means 5 can control the output access completion factor instruction signal 19 by setting a value in the output access completion factor holding means 7. In the simulated operation of the input/output device by the simulation means 5, when it becomes necessary to synchronize with the output access of the processor, a value indicating "r data transfer operation to the simulation means is completed" is set in the output access completion factor holding means 7. do. If this is not the case, the simulating means stores the output access contents in the output access completion factor instruction holding means 7 by the r transfer means.
Set a value that indicates.

In this information processing apparatus, the operation when the processor 1 performs output access to the input/output device to be simulated is as follows. First, the recognition means 3 activates the delivery means and the simulation means by enabling the recognition means output 17. The transfer means 4 activated by the recognition means 3 activates the wait signal 16 of the processor 1 to make the processor 1 wait, and takes in the access contents.At this time, this output access completion factor instruction signal 19 indicates the output access contents by the r transfer means. If there is a free space in the request buffer built in the transfer means 4, the wait signal of the processor is made inactive immediately after the access contents are recorded in the request buffer 18. That is, when the transfer means completes the operation of recording the access contents in the request buffer 18, the access completion factor selection means 6 immediately makes the wait signal 16 of the processor 1 inactive. As a result, processor 1 resumes operation. If there is no free space in the request buffer, the transfer means 4 activates the wait signal 16 to keep the processor 1 in a wait state. In this case, the output access completion factor instruction signal 19, which passes the access content to the simulator 5 and causes the processor 1 to wait until a free area is generated in the request buffer, indicates the completion of the data transfer operation to the simulator 5. If so, the access completion factor selection means 6 keeps the wait signal 16 of the processor 1 active.

In this case, when the transfer operation to the simulation means 5 is completed, the access completion factor selection means 6 in the transfer means 4 makes the wait signal 16 inactive, thereby canceling the request to the processor 1 and starting the processing in the processor 1. Let it restart.

As explained above, in the information processing device according to the present invention,
The simulating means 5 sets a value in the output access completion factor holding means 7, so that the completion factor of the output access issued by the processor 1 is stored in the output access contents storage 1 and rf/11. It becomes possible to select from among the data transfer operation completion 1 for the pseudo means. In other words, if it is necessary to synchronize with the output access issued by the processor 1 when performing a simulation operation, the completion factor of the output access is set as ``Completion of data transfer operation to the simulation means'', and in other cases, , it becomes possible to set the completion factor of the output access to the storage J of the output access contents by the transfer means. Therefore, in the information processing apparatus according to the present invention, it is possible to minimize the wait period required for synchronization through output access.

Note that the operation when the processor 1 performs input access to the input/output device to be simulated is similar to that of an information processing apparatus according to the prior art. That is, when the transfer means 4 is activated by the recognition means 3, it makes the processor 1 wait and passes the access contents to the simulation means 5 upon a request from the simulation means 5. The simulation means 5 creates data to be received by the processor 1. When the transfer means 4 receives the simulated result, it outputs it to the data bus 15 and makes the wait signal 16 inactive. The processor 1 receives the value of the data bus 15 at the time when the wait signal 16 becomes inactive, that is, the simulated result, as the result of the input access.

〔Effect of the invention〕

The present invention provides an information processing device that simulates an input/output device.
Even when executing software that accesses input/output devices that are synchronized by output commands issued by a processor, there is an effect that speed reduction due to output access waits can be minimized.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of an information processing apparatus according to the prior art. 1... Processor, 2... Access means, 3...
Recognition means, 4... Delivery means, 5... Simulation means,
6... Access completion factor selection means, 7... Output access completion factor holding means, 10... Operating system, 11... Host processor, 12... Host operating system, 13... Similar input/output device, 14...address bus, 15...data bus,
16...Wait signal, 17...Recognition means output, 1
8...Request buffer, 19...Output access completion factor holding means.

Claims (1)

[Claims] A means for accessing an input/output device, a recognition means for recognizing that a specific input/output device is being accessed, a simulating means for simulating the operation of the input/output device, and a communication between the simulating means and the processor for requesting and receiving requests from the processor. An information processing device that is provided with a transfer means for transferring execution results in the simulation means and is capable of simulating the operation of an input/output device, further provided with an output access completion holding means set by the simulation means. , an input/output device simulation characterized in that the delivery means includes access completion factor selection means for selecting a completion factor for an output access issued from the access means in accordance with a value held in the output access completion factor holding means. An information processing device with functions.