JPH0379867B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a metal-based chip carrier used as a substrate for electronic devices such as IC packages.

[Background Art] Electronic devices such as IC packages are manufactured by packaging an electronic component chip such as a semiconductor chip attached to a lead frame by resin sealing or airtight sealing. As the number of terminals in such electronic devices increases, attempts are being made to use wiring boards instead of lead frames as carriers for supporting electronic component chips. Furthermore, in response to the increase in the number of terminals, attempts have been made to draw out the terminals from all sides of the wiring board as a carrier.

Figure 4 shows an example of a chip carrier A in which such terminals are pulled out from all sides.
A conductor circuit 9 for lead wires is provided on the surface of the wiring board 5, and a through-hole plating layer 7 is formed on the inner periphery of the semicircular through-holes 6 provided at each of the four ends of the wiring board 5. It is formed by making the plating layer 7 and the conductor circuit 9 continuous, and connecting each conductor circuit 9 to an electronic component chip 11 such as a semiconductor chip mounted in the center of the wiring board 5 by bonding 12 such as wire bonding. has been done. This chip carrier A is mounted on the surface of a wiring board etc. on which printed wiring etc. are applied, and is put into use by connecting the through-hole plating layer 7, which will become the terminal part, to the wiring circuit of the wiring board by soldering or the like. Ru.

Here, the recent increase in the degree of integration of electronic component chips 11 is accompanied by heat generation, and a device for dissipating this heat is required. Therefore, consideration is being given to creating the wiring board 5 constituting the chip carrier A using a metal plate as a substrate and allowing the heat generated by the electronic component chip 11 to escape through the good thermal conductivity of the metal board 2. In manufacturing the chip carrier A as shown in FIG. 4 using a metal plate as a substrate, it is necessary to ensure insulation between the metal substrate 2 and the through-hole plating layer 7 and the conductor circuit 9. For example, Figure 5,
A method as shown in FIG. 6 has been proposed.

That is, first, as shown in FIGS. 5a and 6a, a through hole 1 is formed in a metal substrate 2 made of a steel plate, an iron plate, an aluminum plate, or an alloy plate thereof. The through holes 1 are provided so as to be arranged along the outline of a square, and are provided in a number corresponding to the number of terminals of the chip carrier A. Next, as shown in FIG. 7, a metal foil 14 such as copper foil or aluminum foil is layered on the surface of this metal substrate 2 via a prepreg 13, and molded under heat and pressure. The prepreg 13 is created by using a glass cloth or the like as a substrate and impregnating it with a varnish of thermosetting resin such as epoxy resin or phenolic resin and drying the impregnated material. In this way, prepreg 13 and metal foil 1 are placed on metal substrate 2.
4 are overlapped and hot-press molded, the resin in the prepreg 13 melts and flows into the through hole 1 as insulating resin 4, filling the inside of the through hole 1 as shown in FIGS. 5b and 6b. Prepreg 13
The metal foil 14 is laminated on the metal substrate 2 by the insulating layer 3 which is melted and hardened, and the wiring board 5 can be created. A through hole 6 having a smaller diameter than the through hole 1 is formed concentrically with the through hole 1 at the through hole 1 portion of the wiring board 5, and then the metal foil 1 is formed by a common method such as etching.
4 and remove unnecessary portions, and as shown in FIG. A plating lead wire 15 is provided which is formed continuously with the plating lead wire 8, and metal plating such as copper plating is performed on the inner periphery of the through hole 6 as shown in FIG. 7 should be provided. After this, the outer shape of the wiring board 5 is punched out along lines l passing through each through hole 1 as shown by chain lines in FIG. A chip carrier A formed as an exposed terminal portion is obtained. In Chippukiyaria A created in this way,
The insulation layer 3 ensures insulation between the conductor circuit 9 and the metal substrate 2, and the insulation resin 4 ensures insulation between the through-hole plating layer 7 and the metal substrate 2. .

However, in this case, since the side end surface of the chip carrier A is the cut end surface of the wiring board 5 whose core material is the metal substrate 2, the end surface of the metal substrate 2 is exposed as shown in FIG. However, during the punching process, the cut end of the through-hole land 8 and the cut end of the metal substrate 2 sag in the punching direction of the press cutter, and as shown in FIG. As a result, contact occurs between the through-hole land 8 and the metal substrate 2, and conduction occurs between the through-hole land 8 and the metal substrate 2, and the conductor circuit 9, the through-hole plating layer 7, and the metal substrate 2 become electrically connected. A problem arises in that the insulating layer between the two may be damaged.

[Objective of the Invention] The present invention has been made in view of the above points, and provides a method for manufacturing a chip carrier that is free from the risk of impairing the insulation between the conductor circuit or through-hole plating layer and the metal substrate. The purpose is to

[Disclosure of the Invention] The method for manufacturing a chip carrier according to the present invention includes laminating an insulating layer 3 on the surface of a metal substrate 2 provided with a plurality of through holes 1, and filling each through hole 1 with an insulating resin 4. A wiring board 5 is created using the above method, and a through hole 6 smaller than the diameter of the through hole 1 is formed in the through hole 1 of the wiring board 5 concentrically with the through hole 1, and the inner periphery of the through hole 6 is plated. layer 7
A through-hole plating layer 7 is formed on the surface of the insulating resin 4.
The through-hole land 8 that is continuous with the insulating layer 3
After providing a conductor circuit 9 continuous with the through-hole land 8 on the surface of the chip carrier A, the wiring board 5 is cut along a line passing through the through-hole 6.
When creating the through-hole part land 8
The outer diameter of the through-hole land 8 is smaller than the inner diameter of the through-hole 1, and the outer diameter of the through-hole land 8 is smaller than the inner diameter of the through-hole 1. The present invention is designed to prevent sagging during cutting from acting between the through-hole land 8 and the metal substrate 2, and the present invention will be described in detail below with reference to examples.

The wiring board 5 can be produced in the same manner as shown in FIGS. 5a, b, c, FIGS. 6a, b, c, and FIG. 7 described above. Then, a wiring board 5 is created as shown in FIG. 5b and FIG.
A circular through hole 6 is drilled concentrically with the metal foil 14, and unnecessary portions are removed by processing the metal foil 14 by common means such as etching, and a conductor circuit 9 is formed on the surface of the insulating layer 3 of the wiring board 5. A through-hole land 8 is formed in a ring shape at the periphery of the through-hole 6 on the surface of the insulating resin 4 so as to be continuous with the conductor circuit 9. A mating lead wire 15 is provided respectively. At this time, as shown in FIG. 2, the through-hole land 8 is formed so that its outer shape is concentric with the through-hole 1, and the outer diameter of the through-hole land 8 is the inner diameter of the through-hole 1. It is formed to have a smaller size than the actual size. Then, by applying current from the plating lead wire 15, metal plating such as copper plating is performed on the inner periphery of the through hole 6 as shown in FIG. 6c, thereby providing a through hole plating layer 7.

In this way, the wiring board 5 is coated with the through-hole plating layer 7, through-hole lands 8, and conductor circuits 9.
After forming the wiring board 5, the wiring board 5 is punched and cut along a line 1 passing through each through hole 6 shown by a chain line in FIG. 5c and FIG. can be obtained. When cutting the wiring board 5 by punching in this way, the through-hole land 8 is cut along the punching direction on the cut end surface of the chip carrier A as already explained in FIG.
Even if droop 16 occurs on the cut end surface of the metal substrate 2 or the cut end surface of the metal substrate 2, the outer diameter a of the through-hole land 8 is smaller than the inner diameter b of the through-hole 1, as shown in FIG. There is no overlapping part in the front and back direction between the metal board 2 and the through-hole land 8, and the sag 16 generated on the cut end surface of the through-hole land 8 may come into contact with the cut end surface of the metal substrate 2 or occur on the cut end surface of the metal substrate 2. This makes it possible to prevent the welt 16 from coming into contact with the cut end surface of the through-hole land 8. Therefore, short circuit between the through-hole land 8 and the metal substrate 2 is prevented,
This can prevent the insulation between the conductive circuit 9 and the through-hole plating layer 7 and the metal substrate 2 from being impaired.

And in this one, through hole part land 8
By making the outer diameter of the through hole smaller than the inner diameter of the through hole 1, short circuit between the through hole land 8 and the metal substrate 2 is prevented, and the short circuit between the conductor circuit 9, the through hole plating layer 7, and the metal substrate 2 is prevented. It is possible to prevent the insulation properties of the through hole 6 from being impaired, and there is no need to reduce the diameter of the through hole 6.
A sufficient wall surface area of the through-hole plating layer 7, which serves as the terminal portion of the chip carrier A, can be secured, and connection reliability when mounting the chip carrier A on a printed board etc. is not reduced. Furthermore, since the outer diameter of the through-hole land 8 is smaller than the inner diameter of the through-hole 1, it is possible to secure a large insulation distance between the through-hole land 8 and the metal substrate 2. Plating lead wire 1 when connecting 15 to form through-hole plating layer 7
5 and the metal substrate 2 will also be reliably prevented.

[Effects of the Invention] As described above, in the present invention, when creating a chip carrier by cutting a wiring board along a line passing through a through hole, the outer diameter of the through hole land is set to be smaller than the inner diameter of the through hole. Since the cut end surface of the chip carrier is formed to have a small size, even if there is a drop in the cut end surface of the through hole land or the cut end surface of the metal substrate in the punching direction on the cut end surface of the chip carrier, there will be no damage between the through hole land and the metal substrate. There are no overlapping parts in the front and back directions, and there is no risk of a short circuit between the through-hole land and the metal substrate due to droop occurring on the through-hole land or the cut end surface of the metal substrate, and there is no risk of short circuits between the through-hole land and the metal substrate, and there is no risk of short circuits between the through-hole land and the metal substrate. This can prevent the insulation between the hole plating layer and the metal substrate from being impaired.

[Brief explanation of drawings]

FIG. 1 is an enlarged perspective view of a part of the chip carrier manufactured according to the present invention, FIG. 2 is a plan view of a part of the same, FIG. 3 is a front view of the same, and FIG. 4 is a perspective view of the chip carrier. Figures 5a, b, and c are plan views of each step in the manufacturing process of chipukiyaria; Figures 6a, b, and
c is an enlarged cross-sectional view of a part of the same manufacturing process as above;
Fig. 7 is an enlarged exploded cross-sectional view of a part of the same manufacturing process as above, Fig. 8 is an enlarged perspective view of a part of the conventional chip carrier, and Fig. 9 is a cross-section taken along line L-L in Fig. 8. It is a diagram. 1 is a through hole, 2 is a metal substrate, 3 is an insulating layer, 4 is an insulating resin, 5 is a wiring board, 6 is a through hole, 7
8 is a through-hole plating layer, 8 is a through-hole land, and 9 is a conductor circuit.

Claims (1)

[Claims] 1. A wiring board is created by laminating an insulating layer on the surface of a metal board with a plurality of through holes and filling each through hole with insulating resin. A small through hole is formed concentrically with the through hole, a through hole plating layer is formed on the inner periphery of the through hole, a through hole part land continuous with the through hole plating layer is formed on the surface of the insulating resin, and a through hole is formed on the surface of the insulating layer. After providing conductor circuits continuous with the through-hole lands, cut the wiring board along the line passing through the through-holes to create a chip carrier. A method for manufacturing a metal-based chip carrier characterized by forming a metal base chip carrier.