JPH0379737B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to in-circuit emulators, and more particularly to improvements in emulation sample trace functionality.

(Prior Art) Many devices and products that utilize microprocessors (hereinafter referred to as μP) have been appearing.
Although it has become possible for such devices and products to have diversified functions, simplified designs, and reduced manufacturing costs, inspection, maintenance, troubleshooting, etc. have become increasingly difficult. This is because it is becoming difficult to detect the cause of a failure due to the intervention of software, the use of LSI circuits, and the complicated interaction between software and hardware. No.

Recently, an in-circuit emulator has emerged as one of the suitable devices for analyzing the operation of such μP applied equipment. The in-circuit emulator is configured so that it can emulate the microprocessor by removing the target microprocessor LSI from the IC socket on the board under test and then connecting a probe.

Among these in-circuit emulators, those that support microprocessors that perform prefetching (prefetching instruction codes) have conventionally separated bus trace data and queue trace data and separately latch the data. The method used was to write the sample into the trace memory after sampling it. FIG. 3 is a block diagram showing an example of a circuit portion having a sample trace function in such an in-circuit emulator. In the figure, 10 is a personal module created according to the target microprocessor, which includes an instruction prefetch tracking circuit 12 for prefetching instruction codes on a bus 11 connected to the target microprocessor. have

Reference numeral 20 denotes an emulation memory for storing information necessary for emulating the target microprocessor.

21 and 22 are buses, respectively.

30 is a trace module, which includes data latches 31 and 32 for latching bus trace data and queue trace data, respectively, and a sample memory for storing the bus trace data and queue trace data taken into the data latches. It has 33.

(Problems to be Solved by the Invention) In such a conventional emulator, buses 21 and 2 for bus trace and queue trace
2 were provided separately and independently, which was uneconomical.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an in-circuit emulator having a sample trace function that allows prefetch-compatible tracing to be performed using one bus without providing two independent buses.

(Means for Solving the Problem) In order to achieve such an object, the present invention prefetches an instruction, determines whether or not the instruction has been executed, and outputs the result to the emulation bus. an instruction prefetch tracking circuit configured, an emulation memory connected to an emulation bus, and a sample memory connected to the emulation bus for sampling and storing queue fetch information, The present invention is characterized in that the emulation bus is used as a transfer bus for queue fetch information in a time-division manner at the inactive timing of the bus fetch operation, and the queue fetch information is sampled in the trace memory.

(Example) The present invention will be explained in detail below using the drawings. FIG. 1 is a block diagram of the main parts of an in-circuit emulator according to the present invention. Parts equivalent to those in Figure 3 are given the same symbols. In the personal module 10, 13 is a buffer, and 14 is a bidirectional buffer. Control of the bidirectional buffer 14 (directional control) is performed by a central processing unit (host) (not shown).
Controlled by control signals from CPU). The output of the buffer 13 is OR-combined with the bidirectional buffer side and connected to one bus 23. This bus 23 is connected to a data latch 31 of a trace module 30.

The operation in such a configuration will be explained next.
An example of a microprocessor is the 8-bit microcomputer 6303 series manufactured by Hitachi (a CMOS one-chip microcomputer with ROM and RAM, which has program compatibility at the assembly level with the 6803 microprocessor manufactured by Motorola). Take a microprocessor as an example.

FIG. 2 shows the operation of this microprocessor bus. In section A, the microprocessor is actually taking in data from the memory via the bus. The in-circuit emulator sends data from the emulation memory 20 to the microprocessor via the bus 11 during this interval A when the memory space is allocated to the emulation memory, and also sends data to the sample memory via the latch 31. This data is stored in 32.

In the present invention, the timing of section B is further utilized to obtain queue fetch information (logic circuit output for determining whether or not a prefetched instruction has been executed) generated by the instruction prefetch tracking circuit 12' in the personal module 10. The data is transferred to the sample memory 32 and sampled.

(Effects of the Invention) As explained above, according to the present invention, the conventional method in which two sets of independent buses are prepared to trace prefetched data is changed to a one-bus method. The number of bus connection lines can be reduced and an economical system can be realized.

The in-circuit emulator of the present invention is not limited to the 6303 series microprocessor, but can also be applied to a synchronous prefetch type microprocessor.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the main parts of an embodiment of the in-circuit emulator according to the present invention, Fig. 2 is a time chart for explaining the operation, and Fig. 3 is an example of the main parts of a conventional in-circuit emulator. FIG. 10...Personal module, 11, 23...
...Bus, 12,12'...Instruction preemption...Tracking circuit,
20... Emulation memory, 30... Trace module, 31... Data latch, 32...
sample memory.

Claims (1)

[Scope of Claims] 1. An instruction prefetch tracking circuit configured to prefetch an instruction from a target microprocessor, determine whether the instruction has been executed, and output the result; an emulation memory for storing information necessary for emulating the microprocessor; a sample memory for sampling and storing queue fetch information; and a sample memory connected to the target microprocessor. It is connected to the output side of the buffer provided at the rear stage of the instruction preemption tracking circuit which performs an OR connection with a bidirectional buffer provided at the bus, and also connects to the data latch and the emulation circuit provided at the front stage of the sample memory. An in-circuit emulator comprising an emulation bus connected to a memory and configured to be used as a transfer bus for queue fetch information in a time-sharing manner during inactive timings of bus fetch operations.