JP2535984B2 - Instruction execution detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is for determining whether a prefetched instruction is transferred to an execution process or ignored in an in-circuit emulator for a microprocessor that performs instruction prefetch. Of equipment.

[Prior Art] In recent years, in particular, 16-bit or more microprocessors often perform instruction prefetch in order to improve the processing speed. Such a microprocessor has a built-in buffer memory called an instruction queue for matching, and fetches an instruction having an address up to several bytes ahead of the instruction actually executed in the microprocessor.

However, not all instructions fetched in the instruction queue are executed, and when a JUMP instruction or the like is executed, the instruction queue is cleared and a new instruction is fetched. Therefore, in-circuit emulators compatible with such microprocessors often include a circuit that determines in real time whether an instruction at a certain address is actually executed or is discarded from the instruction queue, as one of its functions. are doing.

Generally, this decision circuit knows the internal state of the instruction queue by directly reading the queue status output by the microprocessor or by an indirect method by preparing a memory in which the total number of instruction cycles is registered and referring to it. It is realized by

[Problems to be Solved by the Invention] However, some microprocessors, such as Intel's 80286 and 80386, which do not output the queue status to the outside have appeared, and the conventional method cannot be applied to such a microprocessor. Therefore, it is difficult to determine the instruction execution in real time without affecting the processing operation of the microprocessor.

The object of the present invention has been made in view of the above circumstances, and an instruction at an address to be executed is determined for a microprocessor that cannot determine whether to execute the instruction by monitoring a signal from outside the microprocessor. An object of the present invention is to provide an instruction execution detecting device which can easily judge the instruction execution by forcibly replacing the code with another specific instruction code.

[Means for Solving Problems] In order to achieve such an object, according to the present invention, an in-circuit emulator equipped with a target microprocessor that performs instruction prefetch is based on a status signal of the microprocessor. Address decoder that generates a signal indicating a bus cycle of instruction code fetch by comparing the address on the address bus of the microprocessor with a given comparison address and outputs a match signal when they match. A circuit, a signal indicating an instruction injection cycle based on the output of the status decoder and the output of the address match detection circuit, and a period for monitoring whether or not an instruction fetch of the same address occurs after the instruction injection. A gate signal generation circuit for generating a signal, and the address An address to be given to the match detection circuit is generated, and an address for which execution decision is normally made is generated, but an instruction is injected only during a period when the instruction injection cycle is active based on the output of the gate signal generation circuit. A comparison address generation circuit for generating an address, a means for generating an instruction swap signal indicating an instruction swap period from the output of the address match detection circuit and the output of the gate signal generation circuit, and data during the instruction injection cycle. Buffer means for inhibiting the fetching of the original instruction code output on the bus; instruction injection means for outputting a branch instruction code on the data bus during the instruction injection cycle; and output of the address match detection circuit. , The address for which execution decision is made from the signal indicating the monitoring period from the gate signal generation circuit Characterized by comprising a gate means for outputting a signal indicating that the instruction has been executed.

[Operation] In the present invention, a bus cycle in which an instruction code at a specified address is prefetched by a microprocessor is detected, and an instruction code that unconditionally branches to a known address instead of the instruction code to be originally fetched is used as the bus cycle. The address match detection circuit detects whether the branch destination address is output to the address bus within a certain number of instruction fetches after that, and if a branch occurs, the branch instruction is executed again. So that the original instruction code is fetched from the injected address,
It is possible to detect whether the instruction code of the designated address prefetched by the output signal of the gate means has been processed by the instruction execution unit in the microprocessor.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a structural diagram of a main part showing an embodiment of an instruction execution detecting device according to the present invention. In the figure, reference numeral 1 is a target microprocessor of the type which is mounted on an in-circuit emulator and performs instruction prefetch.
2 is a coincidence detection circuit for detecting address coincidence, 3 is a gate signal generation circuit, 4 is a comparison address generation circuit, 5 is a 3-state buffer, 6 is an instruction port, and 7 is a branch (JUM).
P) instruction memory, 8 is an address counter, 9 is a status decoder, and 10 and 11 are gates.

The coincidence detection circuit 2 is the address of the microprocessor.
The address on the bus (ADRS BUS) 12 is compared with the address given from the comparison address generation circuit 4, and when both match, a coincidence signal ▲ ▼ is output.

The gate signal generation circuit 3 indicates the instruction injection cycle based on the output of the status decoder 9, that is, the signal indicating the instruction code fetch bus cycle, and the output of the coincidence detection circuit 2. And a signal indicating the period for monitoring whether or not an instruction fetch of the same address occurs after the instruction injection is generated.

The comparison address generation circuit 4 generates a comparison address to be given to the match detection circuit 2. This comparison address is usually an address for which execution judgment is to be attempted, but an address for which an instruction is to be injected is used as a comparison address, especially when the above-mentioned {circle around ()} is active.

The three-state buffer 5 is connected to the data bus (DATA BUS) 13 of the microprocessor and has a function of inhibiting the original instruction code fetch by the output ▲ ▼ of the gate 10.

The address counter 8 receives the output ▲ ▼ of the gate signal generation circuit 3 and the output ▲ ▼ of the status decoder 9, and
While is active, the address is updated in synchronization with ▲ ▼.

In the JUMP instruction memory 7, a relative JUMP instruction code having a displacement that returns to the same address as the address given from the address counter 8 is written in advance, and the instruction code is the instruction injection port. The data bus of the microprocessor at the timing of the output ▲ ▼ signal of the gate 10 via
Output on DATA BUS.

The gate 11 outputs the output of the coincidence detection circuit 2
▼ and the output of the gate signal generation circuit 3 ▲ ▼
And indicates that the instruction at the address for which the execution decision was made was actually executed.
▼ Output a signal.

The operation in such a configuration will be described below. First, the operating principle of the present invention will be described. For simplicity of explanation, it is assumed that the instruction queue in the microprocessor is 4 bytes and the injected JUMP instruction is 1 byte. Generally, when it is necessary to judge the execution of an instruction, it is a point such as address N in the flowchart of FIG. That is, the instruction E of the address N is taken into the instruction queue by the prefetch processing of the microprocessor before the execution processing of the immediately preceding conditional branch instruction D, but the instruction queue is not executed depending on the execution result of the instruction D. This is because it may be cleared.

Therefore, in the present invention, as the instruction of the address N to be judged as shown in FIG. 3B, the instruction (relative jump instruction: JMP.N) for unconditionally branching to the same address is forcibly fetched. Then the program processing proceeds and the third
If a branch occurs after the conditional branch instruction D moves to the execution unit as shown in FIG. 6B, the instruction queue is cleared and the instruction H at branch address N + 3 is newly added to the instruction queue as shown in FIG. Taken in.

On the other hand, when the branch of the instruction D does not occur, the instruction queue is cleared and the instruction E of the branch destination address N is newly fetched as shown in FIG.

Therefore, if the fetch cycle of the address N occurs again during the bus cycle corresponding to the capacity of the instruction queue after the injection of the relative jump instruction, the instruction E of the address N can be determined to be the instruction to be surely executed. At this time, a loss time corresponding to the time to execute the injected JMP.N instruction occurs, but in most cases it can be ignored considering the processing time of the entire program.

It is basically the same even if the injected JUMP instruction is 2 bytes or more. However, it is necessary to stop the instruction injection when the branch by the previously fetched branch instruction occurs during the instruction injection period. Therefore, a circuit for monitoring the instruction injection address is needed.

Now, the operation of FIG. 1 will be described below with reference to the time chart of FIG. In this embodiment, it is assumed that two bus cycles are required to inject the relative JUMP instruction. When the address for which execution determination is to be made is N, the value N is output from the comparison address generation circuit 4 as the comparison address, and the microprocessor 1 outputs the address N on the address bus for prefetch. In the cycle, the output ▲ ▼ of the coincidence detection circuit 2 becomes active as shown in FIG. From this signal, the gate signal generation circuit 3 outputs a ▲ ▼ signal for the bus cycle necessary for injecting the relative JUMP instruction ((e) in the figure).
Is generated and given to the gate 10.

In the instruction fetch bus cycle that occurs during the period in which this signal is active, it is obtained by the logical product with the above signal.
▼ Depending on the signal, J on DATA BUS 13 as shown in the figure
The relative JUMP instruction indicated by MP0 and JMP1 is output.

When the injection of the relative JUMP instruction is completed, the gate signal generation circuit 3 again generates a gate signal that defines a period for monitoring the appearance of N addresses on ADDRES BUS.

▲ ▼ Output from the address match detection circuit while the gate signal is active ▲
Only when the signal becomes active, the signal indicating that the instruction at the address N is determined to be executed in the microprocessor becomes active.

Here, it is necessary to consider the case where the execution unit in the microprocessor executes a branch instruction during the active period. In this case, ▲
The ▼ must be immediately canceled to stop the command injection. Therefore, during the period ▼, the address given to the address match detection circuit 2 is set as the address N + 1 of the instruction of JMP1, and when a branch occurs and an instruction fetch of an address other than N + 1 occurs,
▼ The gate signal generation circuit 3 cancels ▲ ▼ by detecting that the signal remains negative. In FIG. 4, the situation at this time is shown by a broken line.

As described above, it is possible to determine from the bus signal of the microprocessor that the instruction code of the prefetched specified address has been processed by the instruction execution unit in the microprocessor.

The present invention is not limited to the above-mentioned embodiment, but can be carried out as follows.

In the case of the microprocessor in which the injection of the relative JUMP instruction is completed in one bus cycle, the address counter and the JUMP instruction memory shown in FIG. 1 are unnecessary, and the relative injection JUMP instruction code can be directly given to the instruction injection port 6. Further, it is not necessary to generate the gate signal.

In the embodiment, the execution judgment is made at one address. However, when the execution judgment is made at a plurality of points in the address space, the RAM 51 of 1-bit xn configuration is connected to the address bus and "1" is set in advance. There is a method of detecting an address match when the address in which (or "0") was written is accessed by the microprocessor.

In this case, the configuration as shown in FIG.
▼ Indicates that the instruction injection address matches ▲
▼ Indicates that the signal matches the effective judgment address ▲
▼ It is necessary to be able to separate the signal.

The instruction to be injected may be an absolute JUMP instruction to a fixed address as shown in FIG. 6 in addition to the relative JUMP instruction to the same address. At that time, the JUMP instruction for returning to the address where the instruction was injected again is executed at the JUMP destination. Address matching is detected by monitoring the appearance of JUMP destination addresses.

[Effects of the Invention] As described above, according to the present invention, even if the microprocessor cannot judge the execution of the specified address instruction only by monitoring the status signal from the outside of the microprocessor, it is known that the prefetch is performed. It is possible to inject an instruction to branch to an address and judge whether the branch destination address is accessed by the microprocessor or not. Therefore, a very small amount of invalid processing can be performed when the instruction at the specified address is executed in the in-circuit emulator. Only by adding time, it is possible to realize various types of debugging with program addresses as event conditions in near real time.

For example, in high-level language debugging, if you trace using each line No. or the address corresponding to the function module name as a sample condition, the real-time line No.
Traces, etc. are possible.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential part showing an embodiment of an instruction execution detecting device according to the present invention, FIG. 2 is a view showing an example of the flow of an execution program, and FIG. 3 is for explaining the operating principle of the present invention. FIG. 4, FIG. 4 is a time chart of the operation in the configuration of FIG. 1, FIG. 5 is a configuration diagram of a main part of another embodiment of the present invention, and FIG. 6 is for explaining another embodiment of the present invention. FIG. 1 ... Target microprocessor, 2 ... Address match detection circuit, 3 ... Gate signal generation circuit, 4 ... Comparison address generation circuit, 5 ... 3-state buffer, 6
...... Instruction injection port, 7 ...... JUMP instruction memory, 8 ...... Address counter, 9 ...... Status decoder, 10,1
1 …… Gate, 12 …… Address bus, 13 …… Data
bus.

Claims (1)

(57) [Claims] 1. An in-circuit emulator equipped with a target microprocessor that performs instruction prefetch, and a status decoder that generates a signal indicating a bus cycle of instruction code fetch based on a status signal of the microprocessor; An address match detection circuit that compares an address on the address bus of the processor with a given comparison address and outputs a match signal when they match, based on the output of the status decoder and the output of the address match detection circuit. A gate signal generation circuit for generating a signal indicating an instruction injection cycle, a signal for indicating a period for monitoring whether an instruction fetch of the same address occurs after instruction injection, and an address given to the address coincidence detection circuit. Something to generate, usually run A comparison address generation circuit for generating an address for which a decision is to be made, and for generating an address for which an instruction is to be injected only during an active period of the instruction injection cycle based on the output of the gate signal generation circuit; Means for generating an instruction swap signal indicating an instruction swap period from the output and the output of the gate signal generation circuit; and for inhibiting the fetch of the original instruction code output on the data bus during the instruction injection cycle. Execution judgment based on buffer means, instruction injection means for outputting a branch instruction code onto the data bus during the instruction injection cycle, output of the address coincidence detection circuit, and a signal indicating the monitoring period from the gate signal generation circuit And a gate means for outputting a signal indicating that the instruction of the address that has tried to execute is executed. , Detects the bus cycle in which the instruction code of the specified address is prefetched by the microprocessor, and forcibly fetches the instruction code that unconditionally branches to a known address instead of the instruction code that should be originally fetched during that bus cycle. Then, the address match detection circuit detects whether or not the branch destination address is output on the address bus during a certain number of instruction fetches,
When a branch occurs, the original instruction code is fetched again from the address into which the branch instruction is injected, and the instruction code of the designated address prefetched by the output signal of the gate means is processed by the instruction execution unit in the microprocessor. An instruction execution detection device characterized in that it is possible to detect whether or not it has been hit.